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/linux-6.12.1/drivers/net/wireless/intel/iwlwifi/cfg/
D8000.c20 #define IWL8000_NVM_VERSION 0x0a1d
23 #define IWL8260_DCCM_OFFSET 0x800000
24 #define IWL8260_DCCM_LEN 0x18000
25 #define IWL8260_DCCM2_OFFSET 0x880000
26 #define IWL8260_DCCM2_LEN 0x8000
27 #define IWL8260_SMEM_OFFSET 0x400000
28 #define IWL8260_SMEM_LEN 0x68000
97 .min_umac_error_event_table = 0x800000
D9000.c19 #define IWL9000_NVM_VERSION 0x0a1d
22 #define IWL9000_DCCM_OFFSET 0x800000
23 #define IWL9000_DCCM_LEN 0x18000
24 #define IWL9000_DCCM2_OFFSET 0x880000
25 #define IWL9000_DCCM2_LEN 0x8000
26 #define IWL9000_SMEM_OFFSET 0x400000
27 #define IWL9000_SMEM_LEN 0x68000
92 .mac_addr_from_csr = 0x380, \
95 .min_umac_error_event_table = 0x800000, \
96 .d3_debug_data_base_addr = 0x401000, \
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/sound/
Dqcom,lpass-cpu.yaml78 const: 0
81 "^dai-link@[0-9a-f]+$":
254 reg = <0 0x62d87000 0 0x68000>,
255 <0 0x62f00000 0 0x29000>;
258 iommus = <&apps_smmu 0x1020 0>,
259 <&apps_smmu 0x1032 0>;
260 power-domains = <&lpass_hm 0>;
273 interrupts = <0 160 1>,
274 <0 268 1>;
280 #size-cells = <0>;
[all …]
/linux-6.12.1/drivers/accel/habanalabs/include/gaudi/asic_reg/
Dmme0_qm_regs.h22 #define mmMME0_QM_GLBL_CFG0 0x68000
24 #define mmMME0_QM_GLBL_CFG1 0x68004
26 #define mmMME0_QM_GLBL_PROT 0x68008
28 #define mmMME0_QM_GLBL_ERR_CFG 0x6800C
30 #define mmMME0_QM_GLBL_SECURE_PROPS_0 0x68010
32 #define mmMME0_QM_GLBL_SECURE_PROPS_1 0x68014
34 #define mmMME0_QM_GLBL_SECURE_PROPS_2 0x68018
36 #define mmMME0_QM_GLBL_SECURE_PROPS_3 0x6801C
38 #define mmMME0_QM_GLBL_SECURE_PROPS_4 0x68020
40 #define mmMME0_QM_GLBL_NON_SECURE_PROPS_0 0x68024
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/hdcp/
Dhdcp_msg.c77 [HDCP_MESSAGE_ID_READ_BKSV] = 0x0,
78 [HDCP_MESSAGE_ID_READ_RI_R0] = 0x8,
79 [HDCP_MESSAGE_ID_READ_PJ] = 0xA,
80 [HDCP_MESSAGE_ID_WRITE_AKSV] = 0x10,
81 [HDCP_MESSAGE_ID_WRITE_AINFO] = 0x15,
82 [HDCP_MESSAGE_ID_WRITE_AN] = 0x18,
83 [HDCP_MESSAGE_ID_READ_VH_X] = 0x20,
84 [HDCP_MESSAGE_ID_READ_VH_0] = 0x20,
85 [HDCP_MESSAGE_ID_READ_VH_1] = 0x24,
86 [HDCP_MESSAGE_ID_READ_VH_2] = 0x28,
[all …]
/linux-6.12.1/drivers/gpu/drm/i915/display/
Dintel_color_regs.h12 #define _PALETTE_A 0xa000
13 #define _PALETTE_B 0xa800
14 #define _CHV_PALETTE_C 0xc000
18 #define PALETTE_BLUE_MASK REG_GENMASK(7, 0)
22 #define PALETTE_10BIT_BLUE_LDW_MASK REG_GENMASK(7, 0)
32 #define PALETTE_10BIT_BLUE_UDW_MASK REG_GENMASK(1, 0)
40 #define _PIPEAGCMAX 0x70010
41 #define _PIPEBGCMAX 0x71010
45 #define _LGC_PALETTE_A 0x4a000
46 #define _LGC_PALETTE_B 0x4a800
[all …]
Dintel_tv_regs.h12 #define TV_CTL _MMIO(0x68000)
20 # define TV_ENC_OUTPUT_COMPOSITE (0 << 28)
31 # define TV_OVERSAMPLE_4X (0 << 18)
54 # define TV_CTL_SAVE ((1 << 11) | (3 << 9) | (7 << 6) | 0xf)
57 # define TV_FUSE_STATE_ENABLED (0 << 4)
63 # define TV_TEST_MODE_NORMAL (0 << 0)
65 # define TV_TEST_MODE_PATTERN_1 (1 << 0)
67 # define TV_TEST_MODE_PATTERN_2 (2 << 0)
69 # define TV_TEST_MODE_PATTERN_3 (3 << 0)
71 # define TV_TEST_MODE_PATTERN_4 (4 << 0)
[all …]
/linux-6.12.1/arch/arm64/boot/dts/amlogic/
Damlogic-c3.dtsi19 #size-cells = <0>;
21 cpu0: cpu@0 {
24 reg = <0x0 0x0>;
31 reg = <0x0 0x1>;
53 #clock-cells = <0>;
67 reg = <0x0 0x07f50e00 0x0 0x100>;
70 ranges = <0 0x0 0x07f50e00 0x100>;
72 scmi_shmem: sram@0 {
74 reg = <0x0 0x100>;
81 arm,smc-id = <0x820000C1>;
[all …]
Dmeson-s4.dtsi18 #size-cells = <0>;
20 cpu0: cpu@0 {
23 reg = <0x0 0x0>;
30 reg = <0x0 0x1>;
37 reg = <0x0 0x2>;
44 reg = <0x0 0x3>;
66 #clock-cells = <0>;
89 #address-cells = <0>;
91 reg = <0x0 0xfff01000 0 0x1000>,
92 <0x0 0xfff02000 0 0x2000>,
[all …]
/linux-6.12.1/drivers/parisc/
Dsuperio.c32 * Function 0 is an IDE controller. It is identical to a PC87415 IDE
54 * 0x5A: FDC, SP1, IDE1, SP2, IDE2, PAR, Reserved, P92
55 * 0x5B: RTC, 8259, 8254, DMA1, DMA2, KBC, P61, APM
100 outb (OCW3_POLL,IC_PIC1+0); in superio_interrupt()
102 results = inb(IC_PIC1+0); in superio_interrupt()
105 * Bit 7: 1 = active Interrupt; 0 = no Interrupt pending in superio_interrupt()
107 * Bits 2-0: highest priority, active requesting interrupt ID (0-7) in superio_interrupt()
109 if ((results & 0x80) == 0) { in superio_interrupt()
118 local_irq = results & 0x0f; in superio_interrupt()
129 outb(OCW3_ISR,IC_PIC1+0); in superio_interrupt()
[all …]
/linux-6.12.1/arch/powerpc/boot/dts/fsl/
Dt4240si-post.dtsi37 alloc-ranges = <0 0 0x10000 0>;
42 alloc-ranges = <0 0 0x10000 0>;
47 alloc-ranges = <0 0 0x10000 0>;
54 interrupts = <25 2 0 0>;
57 /* controller at 0x240000 */
59 compatible = "fsl,t4240-pcie", "fsl,qoriq-pcie-v3.0";
63 bus-range = <0x0 0xff>;
64 interrupts = <20 2 0 0>;
65 pcie@0 {
70 reg = <0 0 0 0 0>;
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/display/modules/hdcp/
Dhdcp_ddc.c31 #define HDCP_I2C_ADDR 0x3a /* 0x74 >> 1*/
32 #define KSV_READ_SIZE 0xf /* 0x6803b - 0x6802c */
42 MOD_HDCP_MESSAGE_ID_READ_BKSV = 0,
83 [MOD_HDCP_MESSAGE_ID_READ_BKSV] = 0x0,
84 [MOD_HDCP_MESSAGE_ID_READ_RI_R0] = 0x8,
85 [MOD_HDCP_MESSAGE_ID_WRITE_AKSV] = 0x10,
86 [MOD_HDCP_MESSAGE_ID_WRITE_AINFO] = 0x15,
87 [MOD_HDCP_MESSAGE_ID_WRITE_AN] = 0x18,
88 [MOD_HDCP_MESSAGE_ID_READ_VH_X] = 0x20,
89 [MOD_HDCP_MESSAGE_ID_READ_VH_0] = 0x20,
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/mmhub/
Dmmhub_4_1_0_offset.h29 // base address: 0x68000
30 …DAGB0_RDCLI0 0x0000
31 …e regDAGB0_RDCLI0_BASE_IDX 0
32 …DAGB0_RDCLI1 0x0001
33 …e regDAGB0_RDCLI1_BASE_IDX 0
34 …DAGB0_RDCLI2 0x0002
35 …e regDAGB0_RDCLI2_BASE_IDX 0
36 …DAGB0_RDCLI3 0x0003
37 …e regDAGB0_RDCLI3_BASE_IDX 0
38 …DAGB0_RDCLI4 0x0004
[all …]
Dmmhub_3_0_2_offset.h29 // base address: 0x68000
30 …DAGB0_RDCLI0 0x0000
31 …e regDAGB0_RDCLI0_BASE_IDX 0
32 …DAGB0_RDCLI1 0x0001
33 …e regDAGB0_RDCLI1_BASE_IDX 0
34 …DAGB0_RDCLI2 0x0002
35 …e regDAGB0_RDCLI2_BASE_IDX 0
36 …DAGB0_RDCLI3 0x0003
37 …e regDAGB0_RDCLI3_BASE_IDX 0
38 …DAGB0_RDCLI4 0x0004
[all …]
Dmmhub_3_3_0_offset.h29 // base address: 0x68000
30 …DAGB0_RDCLI0 0x0000
32 …DAGB0_RDCLI1 0x0001
34 …DAGB0_RDCLI2 0x0002
36 …DAGB0_RDCLI3 0x0003
38 …DAGB0_RDCLI4 0x0004
40 …DAGB0_RDCLI5 0x0005
42 …DAGB0_RDCLI6 0x0006
44 …DAGB0_RDCLI7 0x0007
46 …DAGB0_RDCLI8 0x0008
[all …]
Dmmhub_3_0_0_offset.h29 // base address: 0x68000
30 …DAGB0_RDCLI0 0x0000
31 …e regDAGB0_RDCLI0_BASE_IDX 0
32 …DAGB0_RDCLI1 0x0001
33 …e regDAGB0_RDCLI1_BASE_IDX 0
34 …DAGB0_RDCLI2 0x0002
35 …e regDAGB0_RDCLI2_BASE_IDX 0
36 …DAGB0_RDCLI3 0x0003
37 …e regDAGB0_RDCLI3_BASE_IDX 0
38 …DAGB0_RDCLI4 0x0004
[all …]
Dmmhub_2_0_0_offset.h27 // base address: 0x68000
28 …DAGB0_RDCLI0 0x0000
29 …ne mmDAGB0_RDCLI0_BASE_IDX 0
30 …DAGB0_RDCLI1 0x0001
31 …ne mmDAGB0_RDCLI1_BASE_IDX 0
32 …DAGB0_RDCLI2 0x0002
33 …ne mmDAGB0_RDCLI2_BASE_IDX 0
34 …DAGB0_RDCLI3 0x0003
35 …ne mmDAGB0_RDCLI3_BASE_IDX 0
36 …DAGB0_RDCLI4 0x0004
[all …]
Dmmhub_3_0_1_offset.h29 // base address: 0x68000
30 …DAGB0_RDCLI0 0x0000
32 …DAGB0_RDCLI1 0x0001
34 …DAGB0_RDCLI2 0x0002
36 …DAGB0_RDCLI3 0x0003
38 …DAGB0_RDCLI4 0x0004
40 …DAGB0_RDCLI5 0x0005
42 …DAGB0_RDCLI6 0x0006
44 …DAGB0_RDCLI7 0x0007
46 …DAGB0_RDCLI8 0x0008
[all …]
Dmmhub_9_1_offset.h27 // base address: 0x68000
28 …DAGB0_RDCLI0 0x0000
29 …ne mmDAGB0_RDCLI0_BASE_IDX 0
30 …DAGB0_RDCLI1 0x0001
31 …ne mmDAGB0_RDCLI1_BASE_IDX 0
32 …DAGB0_RDCLI2 0x0002
33 …ne mmDAGB0_RDCLI2_BASE_IDX 0
34 …DAGB0_RDCLI3 0x0003
35 …ne mmDAGB0_RDCLI3_BASE_IDX 0
36 …DAGB0_RDCLI4 0x0004
[all …]
Dmmhub_9_3_0_offset.h27 // base address: 0x68000
28 …DAGB0_RDCLI0 0x0000
29 …ne mmDAGB0_RDCLI0_BASE_IDX 0
30 …DAGB0_RDCLI1 0x0001
31 …ne mmDAGB0_RDCLI1_BASE_IDX 0
32 …DAGB0_RDCLI2 0x0002
33 …ne mmDAGB0_RDCLI2_BASE_IDX 0
34 …DAGB0_RDCLI3 0x0003
35 …ne mmDAGB0_RDCLI3_BASE_IDX 0
36 …DAGB0_RDCLI4 0x0004
[all …]
Dmmhub_1_0_offset.h27 // base address: 0x68000
28 …DAGB0_RDCLI0 0x0000
29 …ne mmDAGB0_RDCLI0_BASE_IDX 0
30 …DAGB0_RDCLI1 0x0001
31 …ne mmDAGB0_RDCLI1_BASE_IDX 0
32 …DAGB0_RDCLI2 0x0002
33 …ne mmDAGB0_RDCLI2_BASE_IDX 0
34 …DAGB0_RDCLI3 0x0003
35 …ne mmDAGB0_RDCLI3_BASE_IDX 0
36 …DAGB0_RDCLI4 0x0004
[all …]
Dmmhub_2_3_0_offset.h27 // base address: 0x68000
28 …DAGB0_RDCLI0 0x0000
30 …DAGB0_RDCLI1 0x0001
32 …DAGB0_RDCLI2 0x0002
34 …DAGB0_RDCLI3 0x0003
36 …DAGB0_RDCLI4 0x0004
38 …DAGB0_RDCLI5 0x0005
40 …DAGB0_RDCLI6 0x0006
42 …DAGB0_RDCLI7 0x0007
44 …DAGB0_RDCLI8 0x0008
[all …]
/linux-6.12.1/drivers/net/wireless/ath/ath10k/
Dcoredump.c19 {0x800, 0x810},
20 {0x820, 0x82C},
21 {0x830, 0x8F4},
22 {0x90C, 0x91C},
23 {0xA14, 0xA18},
24 {0xA84, 0xA94},
25 {0xAA8, 0xAD4},
26 {0xADC, 0xB40},
27 {0x1000, 0x10A4},
28 {0x10BC, 0x111C},
[all …]
/linux-6.12.1/arch/arm/boot/dts/ti/omap/
Ddra7-l4.dtsi1 &l4_cfg { /* 0x4a000000 */
4 clocks = <&l4cfg_clkctrl DRA7_L4CFG_L4_CFG_CLKCTRL 0>;
6 reg = <0x4a000000 0x800>,
7 <0x4a000800 0x800>,
8 <0x4a001000 0x1000>;
12 ranges = <0x00000000 0x4a000000 0x100000>, /* segment 0 */
13 <0x00100000 0x4a100000 0x100000>, /* segment 1 */
14 <0x00200000 0x4a200000 0x100000>; /* segment 2 */
16 segment@0 { /* 0x4a000000 */
20 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
[all …]
/linux-6.12.1/include/drm/display/
Ddrm_dp.h44 #define DP_MSA_MISC_SYNC_CLOCK (1 << 0)
46 #define DP_MSA_MISC_STEREO_NO_3D (0 << 9)
50 #define DP_MSA_MISC_6_BPC (0 << 5)
66 #define DP_MSA_MISC_COLOR_RGB _DP_MSA_MISC_COLOR(0, 0, 0, 0)
67 #define DP_MSA_MISC_COLOR_CEA_RGB _DP_MSA_MISC_COLOR(0, 0, 1, 0)
68 #define DP_MSA_MISC_COLOR_RGB_WIDE_FIXED _DP_MSA_MISC_COLOR(0, 3, 0, 0)
69 #define DP_MSA_MISC_COLOR_RGB_WIDE_FLOAT _DP_MSA_MISC_COLOR(0, 3, 0, 1)
70 #define DP_MSA_MISC_COLOR_Y_ONLY _DP_MSA_MISC_COLOR(1, 0, 0, 0)
71 #define DP_MSA_MISC_COLOR_RAW _DP_MSA_MISC_COLOR(1, 1, 0, 0)
72 #define DP_MSA_MISC_COLOR_YCBCR_422_BT601 _DP_MSA_MISC_COLOR(0, 1, 1, 0)
[all …]

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