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/linux-6.12.1/Documentation/devicetree/bindings/regulator/
Dst,stm32mp1-pwr-reg.yaml46 reg = <0x50001000 0x10>;
/linux-6.12.1/arch/arm64/boot/dts/bitmain/
Dbm1880.dtsi19 #size-cells = <0>;
21 cpu0: cpu@0 {
24 reg = <0x0>;
31 reg = <0x1>;
42 reg = <0x1 0x00000000 0x0 0x20000>;
47 reg = <0x1 0x30000000 0x0 0x08000000>; // 128M
52 reg = <0x1 0x38000000 0x0 0x08000000>; // 128M
73 #clock-cells = <0>;
84 reg = <0x0 0x50001000 0x0 0x1000>,
85 <0x0 0x50002000 0x0 0x2000>;
[all …]
/linux-6.12.1/arch/arm/boot/dts/renesas/
Dr9a06g032.dtsi19 #size-cells = <0>;
21 cpu@0 {
24 reg = <0>;
34 cpu-release-addr = <0 0x4000c204>;
39 #clock-cells = <0>;
41 clock-frequency = <0>;
45 #clock-cells = <0>;
51 #clock-cells = <0>;
53 clock-frequency = <0>;
57 #clock-cells = <0>;
[all …]
/linux-6.12.1/arch/arm/boot/dts/st/
Dstm32h743.dtsi54 #clock-cells = <0>;
56 clock-frequency = <0>;
60 #clock-cells = <0>;
66 #clock-cells = <0>;
68 clock-frequency = <0>;
75 reg = <0x40000c00 0x400>;
82 #size-cells = <0>;
84 reg = <0x40002400 0x400>;
95 trigger@0 {
97 reg = <0>;
[all …]
Dstm32mp131.dtsi16 #size-cells = <0>;
18 cpu0: cpu@0 {
21 reg = <0>;
43 #size-cells = <0>;
44 linaro,optee-channel-id = <0>;
47 reg = <0x14>;
52 reg = <0x16>;
57 reg = <0x17>;
61 #size-cells = <0>;
63 scmi_reg11: regulator@0 {
[all …]
Dstm32mp151.dtsi16 #size-cells = <0>;
18 cpu0: cpu@0 {
22 reg = <0>;
42 reg = <0xa0021000 0x1000>,
43 <0xa0022000 0x2000>;
58 #clock-cells = <0>;
64 #clock-cells = <0>;
70 #clock-cells = <0>;
76 #clock-cells = <0>;
82 #clock-cells = <0>;
[all …]