Searched +full:0 +full:x43f00000 (Results 1 – 9 of 9) sorted by relevance
21 (addr) - (module ## _BASE_ADDR) + (module ## _BASE_ADDR_VIRT) : 0)35 * whole address space to [0xf4000000, 0xf5ffffff]. So [0xf6000000,0xfeffffff]41 * IO 0x00200000+0x100000 -> 0xf4000000+0x10000043 * AIPI 0x10000000+0x100000 -> 0xf4400000+0x10000044 * SAHB1 0x80000000+0x100000 -> 0xf5000000+0x10000045 * X_MEMC 0xdf000000+0x004000 -> 0xf5f00000+0x00400047 * AIPS1 0x43f00000+0x100000 -> 0xf5300000+0x10000048 * AIPS2 0x53f00000+0x100000 -> 0xf5700000+0x10000049 * AVIC 0x68000000+0x100000 -> 0xf5800000+0x10000051 * AIPI 0x10000000+0x100000 -> 0xf4400000+0x100000[all …]
5 #define MX35_AIPS1_BASE_ADDR 0x43f000007 #define MX35_SPBA0_BASE_ADDR 0x500000009 #define MX35_AIPS2_BASE_ADDR 0x53f0000011 #define MX35_AVIC_BASE_ADDR 0x6800000013 #define MX35_X_MEMC_BASE_ADDR 0xb8000000
5 #define MX31_AIPS1_BASE_ADDR 0x43f000007 #define MX31_SPBA0_BASE_ADDR 0x500000009 #define MX31_AIPS2_BASE_ADDR 0x53f0000011 #define MX31_AVIC_BASE_ADDR 0x6800000013 #define MX31_X_MEMC_BASE_ADDR 0xb8000000
36 #define MX3x_L2CC_BASE_ADDR 0x3000000042 #define MX3x_AIPS1_BASE_ADDR 0x43f0000044 #define MX3x_MAX_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x04000)45 #define MX3x_EVTMON_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x08000)46 #define MX3x_CLKCTL_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x0c000)47 #define MX3x_ETB_SLOT4_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x10000)48 #define MX3x_ETB_SLOT5_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x14000)49 #define MX3x_ECT_CTIO_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x18000)50 #define MX3x_I2C_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x80000)51 #define MX3x_I2C3_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x84000)[all …]
45 implementation defined. Some SoCs can use 0x00000000-0x0fffffff and46 0x40000000-0x4fffffff, while other SoCs only 0x40000000-0x4fffffff.53 bank 0 to 0x42000000-0x43ffffff, bank 5 to 0x46000000-0x46ffffff55 bank 0 to 0x48000000-0x49ffffff, bank 5 to 0x44000000-0x44ffffff61 "^.*@[1-5],[1-9a-f][0-9a-f]+$":77 // - the Ethernet device is connected at the offset 0x01f00000 of CS1 and78 // mapped to 0x43f00000 of the parent bus.79 // - the UART device is connected at the offset 0x00200000 of CS5 and80 // mapped to 0x46200000 of the parent bus.84 reg = <0x58c00000 0x400>;[all …]
47 #size-cells = <0>;49 cpu@0 {52 reg = <0>;60 reg = <0x68000000 0x8000000>;66 #clock-cells = <0>;73 #phy-cells = <0>;78 #phy-cells = <0>;92 reg = <0x43f00000 0x100000>;97 reg = <0x43f00000 0x4000>;102 #size-cells = <0>;[all …]
35 #size-cells = <0>;37 cpu@0 {40 reg = <0>;48 reg = <0x68000000 0x100000>;60 reg = <0x1fffc000 0x4000>;63 ranges = <0 0x1fffc000 0x4000>;70 reg = <0x43f00000 0x100000>;75 reg = <0x43f80000 0x4000>;79 #size-cells = <0>;85 reg = <0x43f84000 0x4000>;[all …]
39 #size-cells = <0>;41 cpu@0 {44 reg = <0>;52 reg = <0x68000000 0x10000000>;64 reg = <0x30000000 0x1000>;73 reg = <0x43f00000 0x100000>;78 #size-cells = <0>;80 reg = <0x43f80000 0x4000>;89 #size-cells = <0>;91 reg = <0x43f84000 0x4000>;[all …]
37 #define FLOAT_ZERO 0x0000000038 #define FLOAT_ONE 0x3f80000039 #define FLOAT_TWO 0x4000000040 #define FLOAT_THREE 0x4040000041 #define FLOAT_FIVE 0x40a0000042 #define FLOAT_SIX 0x40c0000043 #define FLOAT_EIGHT 0x4100000044 #define FLOAT_MINUS_5 0xc0a0000046 #define UNSOL_TAG_DSP 0x1655 #define MASTERCONTROL 0x80[all …]