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12

/linux-6.12.1/arch/arm64/boot/dts/arm/
Dcorstone1000-mps3.dts18 reg = <0x40100000 0x10000>;
27 reg = <0x40200000 0x100000>;
Dcorstone1000-fvp.dts18 reg = <0x40100000 0x10000>;
34 reg = <0x40300000 0x1000>;
44 reg = <0x50000000 0x10000>;
/linux-6.12.1/arch/arm/boot/dts/ti/omap/
Domap5-l4-abe.dtsi1 &l4_abe { /* 0x40100000 */
3 reg = <0x40100000 0x400>,
4 <0x40100400 0x400>;
10 ranges = <0x00000000 0x40100000 0x100000>, /* segment 0 */
11 <0x49000000 0x49000000 0x100000>;
12 segment@0 { /* 0x40100000 */
18 <0x00000000 0x00000000 0x000400>, /* ap 0 */
19 <0x00000400 0x00000400 0x000400>, /* ap 1 */
20 <0x00022000 0x00022000 0x001000>, /* ap 2 */
21 <0x00023000 0x00023000 0x001000>, /* ap 3 */
[all …]
Domap4-l4-abe.dtsi1 &l4_abe { /* 0x40100000 */
3 reg = <0x40100000 0x400>,
4 <0x40100400 0x400>;
10 ranges = <0x00000000 0x40100000 0x100000>, /* segment 0 */
11 <0x49000000 0x49000000 0x100000>;
12 segment@0 { /* 0x40100000 */
18 <0x00000000 0x00000000 0x000400>, /* ap 0 */
19 <0x00000400 0x00000400 0x000400>, /* ap 1 */
20 <0x00022000 0x00022000 0x001000>, /* ap 2 */
21 <0x00023000 0x00023000 0x001000>, /* ap 3 */
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/net/
Dsmsc,lan91c111.yaml57 reg = <0x40100000 0x10000>;
/linux-6.12.1/Documentation/devicetree/bindings/watchdog/
Dxlnx,xps-timebase-wdt.yaml47 enum: [0, 1]
62 reg = <0x40100000 0x1000>;
65 xlnx,wdt-enable-once = <0x0>;
66 xlnx,wdt-interval = <0x1b>;
/linux-6.12.1/Documentation/devicetree/bindings/pci/
Drockchip-dw-pcie-ep.yaml63 reg = <0xa 0x40000000 0x0 0x00100000>,
64 <0xa 0x40100000 0x0 0x00100000>,
65 <0x0 0xfe150000 0x0 0x00010000>,
66 <0x9 0x00000000 0x0 0x40000000>,
67 <0xa 0x40300000 0x0 0x00100000>;
75 interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0>,
76 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>,
77 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>,
78 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>,
79 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>,
[all …]
Dqcom,pcie-sa8775p.yaml91 reg = <0x0 0x01c00000 0x0 0x3000>,
92 <0x0 0x40000000 0x0 0xf20>,
93 <0x0 0x40000f20 0x0 0xa8>,
94 <0x0 0x40001000 0x0 0x4000>,
95 <0x0 0x40100000 0x0 0x100000>,
96 <0x0 0x01c03000 0x0 0x1000>;
98 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
99 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
101 bus-range = <0x00 0xff>;
103 linux,pci-domain = <0>;
[all …]
Dqcom,pcie-sc7280.yaml95 reg = <0 0x01c08000 0 0x3000>,
96 <0 0x40000000 0 0xf1d>,
97 <0 0x40000f20 0 0xa8>,
98 <0 0x40001000 0 0x1000>,
99 <0 0x40100000 0 0x100000>;
101 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
102 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
104 bus-range = <0x00 0xff>;
156 interrupt-map-mask = <0 0 0 0x7>;
157 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>,
[all …]
/linux-6.12.1/arch/arm/boot/dts/intel/pxa/
Dpxa2xx.dtsi64 reg = <0x40d00000 0xd0>;
69 #address-cells = <0x1>;
70 #size-cells = <0x1>;
71 reg = <0x40e00000 0x10000>;
73 #gpio-cells = <0x2>;
77 #interrupt-cells = <0x2>;
81 reg = <0x40e00000 0x4>;
85 reg = <0x40e00004 0x4>;
89 reg = <0x40e00008 0x4>;
92 reg = <0x40e0000c 0x4>;
[all …]
/linux-6.12.1/arch/arm64/boot/dts/qcom/
Dsa8540p.dtsi184 linux,pci-domain = <0>;
201 reg = <0x0 0x01c10000 0x0 0x3000>,
202 <0x0 0x40000000 0x0 0xf1d>,
203 <0x0 0x40000f20 0x0 0xa8>,
204 <0x0 0x40001000 0x0 0x1000>,
205 <0x0 0x40100000 0x0 0x100000>;
208 ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>,
209 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1d00000>;
216 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 541 IRQ_TYPE_LEVEL_HIGH>,
217 <0 0 0 2 &intc 0 0 GIC_SPI 542 IRQ_TYPE_LEVEL_HIGH>,
[all …]
Dsc8180x.dtsi29 #clock-cells = <0>;
35 #clock-cells = <0>;
43 #size-cells = <0>;
45 CPU0: cpu@0 {
48 reg = <0x0 0x0>;
52 qcom,freq-domain = <&cpufreq_hw 0>;
59 clocks = <&cpufreq_hw 0>;
77 reg = <0x0 0x100>;
81 qcom,freq-domain = <&cpufreq_hw 0>;
88 clocks = <&cpufreq_hw 0>;
[all …]
Dsm8350.dtsi38 #clock-cells = <0>;
46 #clock-cells = <0>;
52 #size-cells = <0>;
54 CPU0: cpu@0 {
57 reg = <0x0 0x0>;
58 clocks = <&cpufreq_hw 0>;
61 qcom,freq-domain = <&cpufreq_hw 0>;
81 reg = <0x0 0x100>;
82 clocks = <&cpufreq_hw 0>;
85 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
/linux-6.12.1/arch/arm/mach-pxa/
Ddevices.c52 [0] = {
53 .start = 0x41100000,
54 .end = 0x41100fff,
69 .id = 0, in pxa_set_mci_info()
74 .dma_mask = 0xffffffffUL, in pxa_set_mci_info()
91 [0] = {
92 .start = 0x40600000,
93 .end = 0x4060ffff,
103 static u64 udc_dma_mask = ~(u32)0;
128 [0] = {
[all …]
/linux-6.12.1/arch/arm64/boot/dts/rockchip/
Drk3588-extra.dtsi12 reg = <0x0 0xfc400000 0x0 0x400000>;
13 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH 0>;
32 reg = <0x0 0xfd5b8000 0x0 0x10000>;
37 reg = <0x0 0xfd5c0000 0x0 0x100>;
42 reg = <0x0 0xfd5cc000 0x0 0x4000>;
47 reg = <0x0 0xfd5d4000 0x0 0x4000>;
53 reg = <0x4000 0x10>;
54 #clock-cells = <0>;
58 interrupts = <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH 0>;
64 #phy-cells = <0>;
[all …]
/linux-6.12.1/arch/arm/boot/dts/qcom/
Dqcom-ipq4019.dtsi21 #address-cells = <0x1>;
22 #size-cells = <0x1>;
26 reg = <0x87e00000 0x080000>;
31 reg = <0x87e80000 0x180000>;
45 #size-cells = <0>;
46 cpu@0 {
53 reg = <0x0>;
55 clock-frequency = <0>;
67 reg = <0x1>;
69 clock-frequency = <0>;
[all …]
Dqcom-sdx55.dtsi20 qcom,msm-id = <357 0x10000>, <368 0x10000>, <418 0x10000>;
25 reg = <0 0>;
31 #clock-cells = <0>;
38 #clock-cells = <0>;
44 #clock-cells = <0>;
51 #size-cells = <0>;
53 cpu0: cpu@0 {
56 reg = <0x0>;
108 reg = <0x8fc00000 0x80000>;
113 reg = <0x8fc80000 0x40000>;
[all …]
/linux-6.12.1/drivers/gpu/drm/nouveau/nvkm/engine/gr/
Dctxnv40.c31 * - On context save, NVIDIA set 0x400314 bit 0 to 1 if the "3D state"
35 * opcode 0x60000d is called before resuming normal operation.
37 * checks: ((nsource & 0x0857) || (0x400718 & 0x0100) || (intr & 0x0001))
38 * and calls 0x60000d before resuming normal operation.
40 * and if true 0x800001 is called with count=0, pos=0, the flag is cleared
44 * flag 10. If it's set, they only transfer the small 0x300 byte block
50 * - There's a number of places where context offset 0 (where we place
51 * the PRAMIN offset of the context) is loaded into either 0x408000,
52 * 0x408004 or 0x408008. Not sure what's up there either.
53 * - The ctxprogs for some cards save 0x400a00 again during the cleanup
[all …]
/linux-6.12.1/arch/arm64/boot/dts/st/
Dstm32mp251.dtsi17 #size-cells = <0>;
19 cpu0: cpu@0 {
22 reg = <0>;
38 arm,smc-id = <0xb200005a>;
44 #clock-cells = <0>;
46 clock-frequency = <0>;
50 #clock-cells = <0>;
67 #size-cells = <0>;
68 linaro,optee-channel-id = <0>;
71 reg = <0x14>;
[all …]
/linux-6.12.1/drivers/net/wireless/realtek/rtl8xxxu/
D8710b.c18 {0x421, 0x0F}, {0x428, 0x0A}, {0x429, 0x10}, {0x430, 0x00},
19 {0x431, 0x00}, {0x432, 0x00}, {0x433, 0x01}, {0x434, 0x04},
20 {0x435, 0x05}, {0x436, 0x07}, {0x437, 0x08}, {0x43C, 0x04},
21 {0x43D, 0x05}, {0x43E, 0x07}, {0x43F, 0x08}, {0x440, 0x5D},
22 {0x441, 0x01}, {0x442, 0x00}, {0x444, 0x10}, {0x445, 0x00},
23 {0x446, 0x00}, {0x447, 0x00}, {0x448, 0x00}, {0x449, 0xF0},
24 {0x44A, 0x0F}, {0x44B, 0x3E}, {0x44C, 0x10}, {0x44D, 0x00},
25 {0x44E, 0x00}, {0x44F, 0x00}, {0x450, 0x00}, {0x451, 0xF0},
26 {0x452, 0x0F}, {0x453, 0x00}, {0x456, 0x5E}, {0x460, 0x66},
27 {0x461, 0x66}, {0x4C8, 0xFF}, {0x4C9, 0x08}, {0x4CC, 0xFF},
[all …]
/linux-6.12.1/drivers/net/wireless/realtek/rtw88/
Drtw8723d_table.c10 0x020, 0x00000013,
11 0x02F, 0x00000010,
12 0x077, 0x00000007,
13 0x421, 0x0000000F,
14 0x428, 0x0000000A,
15 0x429, 0x00000010,
16 0x430, 0x00000000,
17 0x431, 0x00000000,
18 0x432, 0x00000000,
19 0x433, 0x00000001,
[all …]
Drtw8703b.c17 #define WLAN_RL_VAL 0x3030
19 #define WLAN_BAR_VAL 0x0201ffff
20 #define WLAN_PIFS_VAL 0
21 #define WLAN_RX_PKT_LIMIT 0x18
22 #define WLAN_SLOT_TIME 0x09
23 #define WLAN_SPEC_SIFS 0x100a
24 #define WLAN_MAX_AGG_NR 0x1f
25 #define WLAN_AMPDU_MAX_TIME 0x70
28 #define TBTT_PROHIBIT_SETUP_TIME 0x04
29 #define TBTT_PROHIBIT_HOLD_TIME 0x80
[all …]
/linux-6.12.1/arch/arm/
DKconfig.debug146 0x80000000 | 0xf0000000 | UART0
147 0x80004000 | 0xf0004000 | UART1
148 0x80008000 | 0xf0008000 | UART2
149 0x8000c000 | 0xf000c000 | UART3
150 0x80010000 | 0xf0010000 | UART4
151 0x80014000 | 0xf0014000 | UART5
152 0x80018000 | 0xf0018000 | UART6
153 0x8001c000 | 0xf001c000 | UART7
154 0x80020000 | 0xf0020000 | UART8
155 0x80024000 | 0xf0024000 | UART9
[all …]
/linux-6.12.1/lib/crypto/
Ddes.c31 0x00, 0x00, 0x40, 0x04, 0x10, 0x10, 0x50, 0x14,
32 0x04, 0x40, 0x44, 0x44, 0x14, 0x50, 0x54, 0x54,
33 0x02, 0x02, 0x42, 0x06, 0x12, 0x12, 0x52, 0x16,
34 0x06, 0x42, 0x46, 0x46, 0x16, 0x52, 0x56, 0x56,
35 0x80, 0x08, 0xc0, 0x0c, 0x90, 0x18, 0xd0, 0x1c,
36 0x84, 0x48, 0xc4, 0x4c, 0x94, 0x58, 0xd4, 0x5c,
37 0x82, 0x0a, 0xc2, 0x0e, 0x92, 0x1a, 0xd2, 0x1e,
38 0x86, 0x4a, 0xc6, 0x4e, 0x96, 0x5a, 0xd6, 0x5e,
39 0x20, 0x20, 0x60, 0x24, 0x30, 0x30, 0x70, 0x34,
40 0x24, 0x60, 0x64, 0x64, 0x34, 0x70, 0x74, 0x74,
[all …]
/linux-6.12.1/drivers/net/ethernet/broadcom/bnx2x/
Dbnx2x_hsi.h17 #define FW_ENCODE_32BIT_PATTERN 0x1e1e1e1e
23 #define BNX2X_MAX_ISCSI_TRGT_CONN_MASK 0xFFFF
24 #define BNX2X_MAX_ISCSI_TRGT_CONN_SHIFT 0
25 #define BNX2X_MAX_ISCSI_INIT_CONN_MASK 0xFFFF0000
31 #define BNX2X_MAX_FCOE_TRGT_CONN_MASK 0xFFFF
32 #define BNX2X_MAX_FCOE_TRGT_CONN_SHIFT 0
33 #define BNX2X_MAX_FCOE_INIT_CONN_MASK 0xFFFF0000
42 #define PIN_CFG_NA 0x00000000
43 #define PIN_CFG_GPIO0_P0 0x00000001
44 #define PIN_CFG_GPIO1_P0 0x00000002
[all …]

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