Searched +full:0 +full:x4002c000 (Results 1 – 4 of 4) sorted by relevance
17 - fsl,ls1021a-v1.0-dspi33 - const: fsl,ls1021a-v1.0-dspi95 reg = <0x4002c000 0x1000>;97 #size-cells = <0>;102 bus-num = <0>;104 pinctrl-0 = <&pinctrl_dspi0_1>;107 flash@0 {109 reg = <0>;
20 #size-cells = <0>;22 cpu@0 {25 reg = <0x0>;32 #clock-cells = <0>;39 #clock-cells = <0>;49 ranges = <0x00000000 0x00000000 0x10000000>,50 <0x20000000 0x20000000 0x30000000>,51 <0xe0000000 0xe0000000 0x04000000>;55 reg = <0x08000000 0x20000>;59 ranges = <0x00000000 0x08000000 0x20000>;[all …]
17 * AHB 0 physical base addresses19 #define LPC32XX_SLC_BASE 0x2002000020 #define LPC32XX_SSP0_BASE 0x2008400021 #define LPC32XX_SPI1_BASE 0x2008800022 #define LPC32XX_SSP1_BASE 0x2008C00023 #define LPC32XX_SPI2_BASE 0x2009000024 #define LPC32XX_I2S0_BASE 0x2009400025 #define LPC32XX_SD_BASE 0x2009800026 #define LPC32XX_I2S1_BASE 0x2009C00027 #define LPC32XX_MLC_BASE 0x200A8000[all …]
33 #clock-cells = <0>;39 #clock-cells = <0>;46 offset = <0x0>;47 mask = <0x1000>;66 reg = <0x40000000 0x00070000>;71 reg = <0x40001000 0x800>;76 reg = <0x40001800 0x400>;85 reg = <0x40018000 0x2000>,86 <0x40024000 0x1000>,87 <0x40025000 0x1000>;[all …]