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/linux-6.12.1/Documentation/devicetree/bindings/interrupt-controller/
Dnxp,lpc3220-mic.txt25 reg = <0x40008000 0x4000>;
32 reg = <0x4000c000 0x4000>;
37 interrupts = <0 IRQ_TYPE_LEVEL_LOW>,
43 reg = <0x40010000 0x4000>;
55 reg = <0x40048000 0x1000>;
/linux-6.12.1/Documentation/devicetree/bindings/clock/
Drenesas,r9a06g032-sysctrl.yaml40 const: 0
67 reg = <0x4000c000 0x1000>;
72 #power-domain-cells = <0>;
/linux-6.12.1/arch/arm/boot/dts/nxp/lpc/
Dlpc32xx.dtsi20 #size-cells = <0>;
22 cpu@0 {
25 reg = <0x0>;
32 #clock-cells = <0>;
39 #clock-cells = <0>;
49 ranges = <0x00000000 0x00000000 0x10000000>,
50 <0x20000000 0x20000000 0x30000000>,
51 <0xe0000000 0xe0000000 0x04000000>;
55 reg = <0x08000000 0x20000>;
59 ranges = <0x00000000 0x08000000 0x20000>;
[all …]
/linux-6.12.1/arch/arm/boot/dts/renesas/
Dr9a06g032.dtsi19 #size-cells = <0>;
21 cpu@0 {
24 reg = <0>;
34 cpu-release-addr = <0 0x4000c204>;
39 #clock-cells = <0>;
41 clock-frequency = <0>;
45 #clock-cells = <0>;
51 #clock-cells = <0>;
53 clock-frequency = <0>;
57 #clock-cells = <0>;
[all …]
/linux-6.12.1/arch/arm/mach-lpc32xx/
Dlpc32xx.h17 * AHB 0 physical base addresses
19 #define LPC32XX_SLC_BASE 0x20020000
20 #define LPC32XX_SSP0_BASE 0x20084000
21 #define LPC32XX_SPI1_BASE 0x20088000
22 #define LPC32XX_SSP1_BASE 0x2008C000
23 #define LPC32XX_SPI2_BASE 0x20090000
24 #define LPC32XX_I2S0_BASE 0x20094000
25 #define LPC32XX_SD_BASE 0x20098000
26 #define LPC32XX_I2S1_BASE 0x2009C000
27 #define LPC32XX_MLC_BASE 0x200A8000
[all …]
/linux-6.12.1/arch/arm/boot/dts/st/
Dstm32mp131.dtsi16 #size-cells = <0>;
18 cpu0: cpu@0 {
21 reg = <0>;
43 #size-cells = <0>;
44 linaro,optee-channel-id = <0>;
47 reg = <0x14>;
52 reg = <0x16>;
57 reg = <0x17>;
61 #size-cells = <0>;
63 scmi_reg11: regulator@0 {
[all …]
Dstm32mp151.dtsi16 #size-cells = <0>;
18 cpu0: cpu@0 {
22 reg = <0>;
42 reg = <0xa0021000 0x1000>,
43 <0xa0022000 0x2000>;
58 #clock-cells = <0>;
64 #clock-cells = <0>;
70 #clock-cells = <0>;
76 #clock-cells = <0>;
82 #clock-cells = <0>;
[all …]
/linux-6.12.1/sound/pci/hda/
Dpatch_realtek.c166 snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_COEF_INDEX, coef_idx); in __alc_read_coefex_idx()
167 val = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_PROC_COEF, 0); in __alc_read_coefex_idx()
183 alc_read_coefex_idx(codec, 0x20, coef_idx)
188 snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_COEF_INDEX, coef_idx); in __alc_write_coefex_idx()
189 snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_PROC_COEF, coef_val); in __alc_write_coefex_idx()
201 alc_write_coefex_idx(codec, 0x20, coef_idx, coef_val)
224 alc_update_coefex_idx(codec, 0x20, coef_idx, mask, bits_set)
226 /* a special bypass for COEF 0; read the cached value at the second time */
232 spec->coef0 = alc_read_coef_idx(codec, 0); in alc_get_coef0()
247 #define WRITE_COEF(_idx, _val) WRITE_COEFEX(0x20, _idx, _val)
[all …]