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Searched +full:0 +full:x40004000 (Results 1 – 21 of 21) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/amd/amdgpu/
Dclearstate_gfx11.h28 0x00000000, // DB_RENDER_CONTROL
29 0x00000000, // DB_COUNT_CONTROL
30 0x00000000, // DB_DEPTH_VIEW
31 0x00000000, // DB_RENDER_OVERRIDE
32 0x00000000, // DB_RENDER_OVERRIDE2
33 0x00000000, // DB_HTILE_DATA_BASE
34 0, // HOLE
35 0x00000000, // DB_DEPTH_SIZE_XY
36 0x00000000, // DB_DEPTH_BOUNDS_MIN
37 0x00000000, // DB_DEPTH_BOUNDS_MAX
[all …]
Dclearstate_ci.h26 0x00000000, // DB_RENDER_CONTROL
27 0x00000000, // DB_COUNT_CONTROL
28 0x00000000, // DB_DEPTH_VIEW
29 0x00000000, // DB_RENDER_OVERRIDE
30 0x00000000, // DB_RENDER_OVERRIDE2
31 0x00000000, // DB_HTILE_DATA_BASE
32 0, // HOLE
33 0, // HOLE
34 0x00000000, // DB_DEPTH_BOUNDS_MIN
35 0x00000000, // DB_DEPTH_BOUNDS_MAX
[all …]
Dclearstate_vi.h26 0x00000000, // DB_RENDER_CONTROL
27 0x00000000, // DB_COUNT_CONTROL
28 0x00000000, // DB_DEPTH_VIEW
29 0x00000000, // DB_RENDER_OVERRIDE
30 0x00000000, // DB_RENDER_OVERRIDE2
31 0x00000000, // DB_HTILE_DATA_BASE
32 0, // HOLE
33 0, // HOLE
34 0x00000000, // DB_DEPTH_BOUNDS_MIN
35 0x00000000, // DB_DEPTH_BOUNDS_MAX
[all …]
Dclearstate_gfx9.h25 0x00000000, // DB_RENDER_CONTROL
26 0x00000000, // DB_COUNT_CONTROL
27 0x00000000, // DB_DEPTH_VIEW
28 0x00000000, // DB_RENDER_OVERRIDE
29 0x00000000, // DB_RENDER_OVERRIDE2
30 0x00000000, // DB_HTILE_DATA_BASE
31 0x00000000, // DB_HTILE_DATA_BASE_HI
32 0x00000000, // DB_DEPTH_SIZE
33 0x00000000, // DB_DEPTH_BOUNDS_MIN
34 0x00000000, // DB_DEPTH_BOUNDS_MAX
[all …]
Dclearstate_si.h25 0x00000000, // DB_RENDER_CONTROL
26 0x00000000, // DB_COUNT_CONTROL
27 0x00000000, // DB_DEPTH_VIEW
28 0x00000000, // DB_RENDER_OVERRIDE
29 0x00000000, // DB_RENDER_OVERRIDE2
30 0x00000000, // DB_HTILE_DATA_BASE
31 0, // HOLE
32 0, // HOLE
33 0x00000000, // DB_DEPTH_BOUNDS_MIN
34 0x00000000, // DB_DEPTH_BOUNDS_MAX
[all …]
Dclearstate_gfx10.h25 0x00000000, // DB_RENDER_CONTROL
26 0x00000000, // DB_COUNT_CONTROL
27 0x00000000, // DB_DEPTH_VIEW
28 0x00000000, // DB_RENDER_OVERRIDE
29 0x00000000, // DB_RENDER_OVERRIDE2
30 0x00000000, // DB_HTILE_DATA_BASE
31 0x00000000, // HOLE
32 0x00000000, // DB_DEPTH_SIZE_XY
33 0x00000000, // DB_DEPTH_BOUNDS_MIN
34 0x00000000, // DB_DEPTH_BOUNDS_MAX
[all …]
/linux-6.12.1/drivers/gpu/drm/radeon/
Dclearstate_ci.h27 0x00000000, // DB_RENDER_CONTROL
28 0x00000000, // DB_COUNT_CONTROL
29 0x00000000, // DB_DEPTH_VIEW
30 0x00000000, // DB_RENDER_OVERRIDE
31 0x00000000, // DB_RENDER_OVERRIDE2
32 0x00000000, // DB_HTILE_DATA_BASE
33 0, // HOLE
34 0, // HOLE
35 0x00000000, // DB_DEPTH_BOUNDS_MIN
36 0x00000000, // DB_DEPTH_BOUNDS_MAX
[all …]
Dclearstate_si.h27 0x00000000, // DB_RENDER_CONTROL
28 0x00000000, // DB_COUNT_CONTROL
29 0x00000000, // DB_DEPTH_VIEW
30 0x00000000, // DB_RENDER_OVERRIDE
31 0x00000000, // DB_RENDER_OVERRIDE2
32 0x00000000, // DB_HTILE_DATA_BASE
33 0, // HOLE
34 0, // HOLE
35 0x00000000, // DB_DEPTH_BOUNDS_MIN
36 0x00000000, // DB_DEPTH_BOUNDS_MAX
[all …]
Dclearstate_cayman.h27 0x00000000, // DB_RENDER_CONTROL
28 0x00000000, // DB_COUNT_CONTROL
29 0x00000000, // DB_DEPTH_VIEW
30 0x00000000, // DB_RENDER_OVERRIDE
31 0x00000000, // DB_RENDER_OVERRIDE2
32 0x00000000, // DB_HTILE_DATA_BASE
33 0, // HOLE
34 0, // HOLE
35 0, // HOLE
36 0, // HOLE
[all …]
Dclearstate_evergreen.h26 0x00000000, // DB_RENDER_CONTROL
27 0x00000000, // DB_COUNT_CONTROL
28 0x00000000, // DB_DEPTH_VIEW
29 0x00000000, // DB_RENDER_OVERRIDE
30 0x00000000, // DB_RENDER_OVERRIDE2
31 0x00000000, // DB_HTILE_DATA_BASE
32 0, // HOLE
33 0, // HOLE
34 0, // HOLE
35 0, // HOLE
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/serial/
Darm,mps2-uart.txt16 reg = <0x40004000 0x1000>;
17 interrupts = <0 1 12>;
/linux-6.12.1/Documentation/devicetree/bindings/sound/
Dst,stm32-spdifrx.yaml25 const: 0
75 #sound-dai-cells = <0>;
76 reg = <0x40004000 0x400>;
80 dmas = <&dmamux1 2 93 0x400 0x0>,
81 <&dmamux1 3 94 0x400 0x0>;
83 pinctrl-0 = <&spdifrx_pins>;
/linux-6.12.1/arch/sparc/
DKconfig386 default 0x40004000
390 This address is normally the base address of main memory + 0x4000.
394 default 0x00080000
403 default 0xf0004000
/linux-6.12.1/drivers/gpu/drm/i915/gt/
Dgen9_renderstate.c11 0x000007a8,
12 0x000007b4,
13 0x000007bc,
14 0x000007cc,
19 0x7a000004,
20 0x01000000,
21 0x00000000,
22 0x00000000,
23 0x00000000,
24 0x00000000,
[all …]
Dgen8_renderstate.c11 0x00000798,
12 0x000007a4,
13 0x000007ac,
14 0x000007bc,
19 0x7a000004,
20 0x01000000,
21 0x00000000,
22 0x00000000,
23 0x00000000,
24 0x00000000,
[all …]
/linux-6.12.1/arch/arm/boot/dts/nxp/lpc/
Dlpc32xx.dtsi20 #size-cells = <0>;
22 cpu@0 {
25 reg = <0x0>;
32 #clock-cells = <0>;
39 #clock-cells = <0>;
49 ranges = <0x00000000 0x00000000 0x10000000>,
50 <0x20000000 0x20000000 0x30000000>,
51 <0xe0000000 0xe0000000 0x04000000>;
55 reg = <0x08000000 0x20000>;
59 ranges = <0x00000000 0x08000000 0x20000>;
[all …]
Dlpc18xx.dtsi19 #define LPC_PIN(port, pin) (0x##port * 32 + pin)
28 #size-cells = <0>;
30 cpu@0 {
33 reg = <0x0>;
41 #clock-cells = <0>;
47 #clock-cells = <0>;
53 #clock-cells = <0>;
54 clock-frequency = <0>;
60 #clock-cells = <0>;
61 clock-frequency = <0>;
[all …]
/linux-6.12.1/arch/arm/mach-lpc32xx/
Dlpc32xx.h17 * AHB 0 physical base addresses
19 #define LPC32XX_SLC_BASE 0x20020000
20 #define LPC32XX_SSP0_BASE 0x20084000
21 #define LPC32XX_SPI1_BASE 0x20088000
22 #define LPC32XX_SSP1_BASE 0x2008C000
23 #define LPC32XX_SPI2_BASE 0x20090000
24 #define LPC32XX_I2S0_BASE 0x20094000
25 #define LPC32XX_SD_BASE 0x20098000
26 #define LPC32XX_I2S1_BASE 0x2009C000
27 #define LPC32XX_MLC_BASE 0x200A8000
[all …]
/linux-6.12.1/arch/x86/kernel/
Dsetup.c88 .start = 0,
89 .end = 0,
95 .start = 0,
96 .end = 0,
102 .start = 0,
103 .end = 0,
109 .start = 0,
110 .end = 0,
161 #define RAMDISK_IMAGE_START_MASK 0x07FF
162 #define RAMDISK_PROMPT_FLAG 0x8000
[all …]
/linux-6.12.1/arch/arm/boot/dts/st/
Dstm32mp131.dtsi16 #size-cells = <0>;
18 cpu0: cpu@0 {
21 reg = <0>;
43 #size-cells = <0>;
44 linaro,optee-channel-id = <0>;
47 reg = <0x14>;
52 reg = <0x16>;
57 reg = <0x17>;
61 #size-cells = <0>;
63 scmi_reg11: regulator@0 {
[all …]
Dstm32mp151.dtsi16 #size-cells = <0>;
18 cpu0: cpu@0 {
22 reg = <0>;
42 reg = <0xa0021000 0x1000>,
43 <0xa0022000 0x2000>;
58 #clock-cells = <0>;
64 #clock-cells = <0>;
70 #clock-cells = <0>;
76 #clock-cells = <0>;
82 #clock-cells = <0>;
[all …]