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/linux-6.12.1/drivers/accel/habanalabs/include/gaudi2/asic_reg/
Ddcore0_tpc0_eml_stm_regs.h23 #define mmDCORE0_TPC0_EML_STM_STMDMASTARTR 0x3C04
25 #define mmDCORE0_TPC0_EML_STM_STMDMASTOPR 0x3C08
27 #define mmDCORE0_TPC0_EML_STM_STMDMASTATR 0x3C0C
29 #define mmDCORE0_TPC0_EML_STM_STMDMACTLR 0x3C10
31 #define mmDCORE0_TPC0_EML_STM_STMDMAIDR 0x3CFC
33 #define mmDCORE0_TPC0_EML_STM_STMHEER 0x3D00
35 #define mmDCORE0_TPC0_EML_STM_STMHETER 0x3D20
37 #define mmDCORE0_TPC0_EML_STM_STMHEBSR 0x3D60
39 #define mmDCORE0_TPC0_EML_STM_STMHEMCR 0x3D64
41 #define mmDCORE0_TPC0_EML_STM_STMHEEXTMUXR 0x3D68
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_3_1_d.h27 #define mmUVD_SEMA_ADDR_LOW 0x3bc0
28 #define mmUVD_SEMA_ADDR_HIGH 0x3bc1
29 #define mmUVD_SEMA_CMD 0x3bc2
30 #define mmUVD_GPCOM_VCPU_CMD 0x3bc3
31 #define mmUVD_GPCOM_VCPU_DATA0 0x3bc4
32 #define mmUVD_GPCOM_VCPU_DATA1 0x3bc5
33 #define mmUVD_ENGINE_CNTL 0x3bc6
34 #define mmUVD_UDEC_ADDR_CONFIG 0x3bd3
35 #define mmUVD_UDEC_DB_ADDR_CONFIG 0x3bd4
36 #define mmUVD_UDEC_DBW_ADDR_CONFIG 0x3bd5
[all …]
Duvd_4_0_d.h26 #define ixUVD_CGC_CTRL2 0x00C1
27 #define ixUVD_CGC_MEM_CTRL 0x00C0
28 #define ixUVD_LMI_ADDR_EXT2 0x00AB
29 #define ixUVD_LMI_CACHE_CTRL 0x009B
30 #define ixUVD_LMI_SWAP_CNTL2 0x00AA
31 #define ixUVD_MIF_CURR_ADDR_CONFIG 0x0048
32 #define ixUVD_MIF_RECON1_ADDR_CONFIG 0x0114
33 #define ixUVD_MIF_REF_ADDR_CONFIG 0x004C
34 #define mmUVD_CGC_CTRL 0x3D2C
35 #define mmUVD_CGC_GATE 0x3D2A
[all …]
Duvd_4_2_d.h27 #define mmUVD_SEMA_ADDR_LOW 0x3bc0
28 #define mmUVD_SEMA_ADDR_HIGH 0x3bc1
29 #define mmUVD_SEMA_CMD 0x3bc2
30 #define mmUVD_GPCOM_VCPU_CMD 0x3bc3
31 #define mmUVD_GPCOM_VCPU_DATA0 0x3bc4
32 #define mmUVD_GPCOM_VCPU_DATA1 0x3bc5
33 #define mmUVD_ENGINE_CNTL 0x3bc6
34 #define mmUVD_UDEC_ADDR_CONFIG 0x3bd3
35 #define mmUVD_UDEC_DB_ADDR_CONFIG 0x3bd4
36 #define mmUVD_UDEC_DBW_ADDR_CONFIG 0x3bd5
[all …]
Duvd_5_0_d.h27 #define mmUVD_SEMA_ADDR_LOW 0x3bc0
28 #define mmUVD_SEMA_ADDR_HIGH 0x3bc1
29 #define mmUVD_SEMA_CMD 0x3bc2
30 #define mmUVD_GPCOM_VCPU_CMD 0x3bc3
31 #define mmUVD_GPCOM_VCPU_DATA0 0x3bc4
32 #define mmUVD_GPCOM_VCPU_DATA1 0x3bc5
33 #define mmUVD_ENGINE_CNTL 0x3bc6
34 #define mmUVD_UDEC_ADDR_CONFIG 0x3bd3
35 #define mmUVD_UDEC_DB_ADDR_CONFIG 0x3bd4
36 #define mmUVD_UDEC_DBW_ADDR_CONFIG 0x3bd5
[all …]
Duvd_6_0_d.h27 #define mmUVD_SEMA_ADDR_LOW 0x3bc0
28 #define mmUVD_SEMA_ADDR_HIGH 0x3bc1
29 #define mmUVD_SEMA_CMD 0x3bc2
30 #define mmUVD_GPCOM_VCPU_CMD 0x3bc3
31 #define mmUVD_GPCOM_VCPU_DATA0 0x3bc4
32 #define mmUVD_GPCOM_VCPU_DATA1 0x3bc5
33 #define mmUVD_ENGINE_CNTL 0x3bc6
34 #define mmUVD_UDEC_ADDR_CONFIG 0x3bd3
35 #define mmUVD_UDEC_DB_ADDR_CONFIG 0x3bd4
36 #define mmUVD_UDEC_DBW_ADDR_CONFIG 0x3bd5
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/i2c/
Di2c-mpc.yaml69 #size-cells = <0>;
71 reg = <0x1740 0x20>;
72 interrupts = <11 0x8>;
81 #size-cells = <0>;
83 reg = <0x3d00 0x40>;
84 interrupts = <2 15 0>;
93 #size-cells = <0>;
95 reg = <0x3100 0x100>;
/linux-6.12.1/Documentation/devicetree/bindings/phy/
Dmediatek,xsphy.yaml20 u2 port0 0x0000 MISC
21 0x0100 FMREG
22 0x0300 U2PHY_COM
23 u2 port1 0x1000 MISC
24 0x1100 FMREG
25 0x1300 U2PHY_COM
26 u2 port2 0x2000 MISC
28 u31 common 0x3000 DIG_GLB
29 0x3100 PHYA_GLB
30 u31 port0 0x3400 DIG_LN_TOP
[all …]
/linux-6.12.1/arch/powerpc/boot/dts/
Dep88xc.dts19 #size-cells = <0>;
21 PowerPC,885@0 {
23 reg = <0x0>;
28 timebase-frequency = <0>;
29 bus-frequency = <0>;
30 clock-frequency = <0>;
38 reg = <0x0 0x0>;
45 reg = <0xfa200100 0x40>;
48 0x0 0x0 0xfc000000 0x4000000
49 0x3 0x0 0xfa000000 0x1000000
[all …]
Dcharon.dts23 #size-cells = <0>;
25 PowerPC,5200@0 {
27 reg = <0>;
30 d-cache-size = <0x4000>; // L1, 16K
31 i-cache-size = <0x4000>; // L1, 16K
32 timebase-frequency = <0>; // from bootloader
33 bus-frequency = <0>; // from bootloader
34 clock-frequency = <0>; // from bootloader
38 memory@0 {
40 reg = <0x00000000 0x08000000>; // 128MB
[all …]
Dlite5200.dts20 #size-cells = <0>;
22 PowerPC,5200@0 {
24 reg = <0>;
27 d-cache-size = <0x4000>; // L1, 16K
28 i-cache-size = <0x4000>; // L1, 16K
29 timebase-frequency = <0>; // from bootloader
30 bus-frequency = <0>; // from bootloader
31 clock-frequency = <0>; // from bootloader
35 memory@0 {
37 reg = <0x00000000 0x04000000>; // 64MB
[all …]
Dmpc5200b.dtsi21 #size-cells = <0>;
23 powerpc: PowerPC,5200@0 {
25 reg = <0>;
28 d-cache-size = <0x4000>; // L1, 16K
29 i-cache-size = <0x4000>; // L1, 16K
30 timebase-frequency = <0>; // from bootloader
31 bus-frequency = <0>; // from bootloader
32 clock-frequency = <0>; // from bootloader
36 memory: memory@0 {
38 reg = <0x00000000 0x04000000>; // 64MB
[all …]
/linux-6.12.1/drivers/gpu/drm/mgag200/
Dmgag200_reg.h24 #define MGAREG_DWGCTL 0x1c00
25 #define MGAREG_MACCESS 0x1c04
27 #define MGAREG_MCTLWTST 0x1c08
28 #define MGAREG_ZORG 0x1c0c
30 #define MGAREG_PAT0 0x1c10
31 #define MGAREG_PAT1 0x1c14
32 #define MGAREG_PLNWT 0x1c1c
34 #define MGAREG_BCOL 0x1c20
35 #define MGAREG_FCOL 0x1c24
37 #define MGAREG_SRC0 0x1c30
[all …]
/linux-6.12.1/drivers/net/ethernet/amd/
Dariadne.h17 * Publication #16907, Rev. B, Amendment/0, May 1994
62 #define CSR0 0x0000 /* - PCnet-ISA Controller Status */
63 #define CSR1 0x0100 /* - IADR[15:0] */
64 #define CSR2 0x0200 /* - IADR[23:16] */
65 #define CSR3 0x0300 /* - Interrupt Masks and Deferral Control */
66 #define CSR4 0x0400 /* - Test and Features Control */
67 #define CSR6 0x0600 /* RCV/XMT Descriptor Table Length */
68 #define CSR8 0x0800 /* - Logical Address Filter, LADRF[15:0] */
69 #define CSR9 0x0900 /* - Logical Address Filter, LADRF[31:16] */
70 #define CSR10 0x0a00 /* - Logical Address Filter, LADRF[47:32] */
[all …]
/linux-6.12.1/drivers/scsi/
Dsun3_scsi.c91 #define UDC_MODE 0x38
92 #define UDC_CSR 0x2e /* command/status */
93 #define UDC_CHN_HI 0x26 /* chain high word */
94 #define UDC_CHN_LO 0x22 /* chain lo word */
95 #define UDC_CURA_HI 0x1a /* cur reg A high */
96 #define UDC_CURA_LO 0x0a /* cur reg A low */
97 #define UDC_CURB_HI 0x12 /* cur reg B high */
98 #define UDC_CURB_LO 0x02 /* cur reg B low */
99 #define UDC_MODE_HI 0x56 /* mode reg high */
100 #define UDC_MODE_LO 0x52 /* mode reg low */
[all …]
Dsense_codes.h7 SENSE_CODE(0x0000, "No additional sense information")
8 SENSE_CODE(0x0001, "Filemark detected")
9 SENSE_CODE(0x0002, "End-of-partition/medium detected")
10 SENSE_CODE(0x0003, "Setmark detected")
11 SENSE_CODE(0x0004, "Beginning-of-partition/medium detected")
12 SENSE_CODE(0x0005, "End-of-data detected")
13 SENSE_CODE(0x0006, "I/O process terminated")
14 SENSE_CODE(0x0007, "Programmable early warning detected")
15 SENSE_CODE(0x0011, "Audio play operation in progress")
16 SENSE_CODE(0x0012, "Audio play operation paused")
[all …]
/linux-6.12.1/drivers/media/i2c/
Dov9734.c21 #define OV9734_REG_CHIP_ID 0x300a
22 #define OV9734_CHIP_ID 0x9734
24 #define OV9734_REG_MODE_SELECT 0x0100
25 #define OV9734_MODE_STANDBY 0x00
26 #define OV9734_MODE_STREAMING 0x01
29 #define OV9734_REG_VTS 0x380e
30 #define OV9734_VTS_30FPS 0x0322
31 #define OV9734_VTS_30FPS_MIN 0x0322
32 #define OV9734_VTS_MAX 0x7fff
35 #define OV9734_REG_HTS 0x380c
[all …]
Dar0521.c31 #define AR0521_MIN_X_ADDR_START 0u
32 #define AR0521_MIN_Y_ADDR_START 0u
46 #define AR0521_ANA_GAIN_MIN 0x00
47 #define AR0521_ANA_GAIN_MAX 0x3f
48 #define AR0521_ANA_GAIN_STEP 0x01
49 #define AR0521_ANA_GAIN_DEFAULT 0x00
52 #define AR0521_REG_VT_PIX_CLK_DIV 0x0300
53 #define AR0521_REG_FRAME_LENGTH_LINES 0x0340
55 #define AR0521_REG_CHIP_ID 0x3000
56 #define AR0521_REG_COARSE_INTEGRATION_TIME 0x3012
[all …]
Dov5648.c30 #define OV5648_SW_STANDBY_REG 0x100
31 #define OV5648_SW_STANDBY_STREAM_ON BIT(0)
33 #define OV5648_SW_RESET_REG 0x103
34 #define OV5648_SW_RESET_RESET BIT(0)
36 #define OV5648_PAD_OEN0_REG 0x3000
37 #define OV5648_PAD_OEN1_REG 0x3001
38 #define OV5648_PAD_OEN2_REG 0x3002
39 #define OV5648_PAD_OUT0_REG 0x3008
40 #define OV5648_PAD_OUT1_REG 0x3009
42 #define OV5648_CHIP_ID_H_REG 0x300a
[all …]
/linux-6.12.1/drivers/media/dvb-frontends/
Ds5h1411.c42 } while (0)
50 { S5H1411_I2C_TOP_ADDR, 0x00, 0x0071, },
51 { S5H1411_I2C_TOP_ADDR, 0x08, 0x0047, },
52 { S5H1411_I2C_TOP_ADDR, 0x1c, 0x0400, },
53 { S5H1411_I2C_TOP_ADDR, 0x1e, 0x0370, },
54 { S5H1411_I2C_TOP_ADDR, 0x1f, 0x342c, },
55 { S5H1411_I2C_TOP_ADDR, 0x24, 0x0231, },
56 { S5H1411_I2C_TOP_ADDR, 0x25, 0x1011, },
57 { S5H1411_I2C_TOP_ADDR, 0x26, 0x0f07, },
58 { S5H1411_I2C_TOP_ADDR, 0x27, 0x0f04, },
[all …]
/linux-6.12.1/drivers/media/platform/renesas/vsp1/
Dvsp1_regs.h17 #define VI6_CMD(n) (0x0000 + (n) * 4)
19 #define VI6_CMD_STRCMD BIT(0)
21 #define VI6_CLK_DCSWT 0x0018
22 #define VI6_CLK_DCSWT_CSTPW_MASK (0xff << 8)
24 #define VI6_CLK_DCSWT_CSTRW_MASK (0xff << 0)
25 #define VI6_CLK_DCSWT_CSTRW_SHIFT 0
27 #define VI6_SRESET 0x0028
30 #define VI6_STATUS 0x0038
34 #define VI6_WPF_IRQ_ENB(n) (0x0048 + (n) * 12)
37 #define VI6_WPF_IRQ_ENB_FREE BIT(0)
[all …]
/linux-6.12.1/drivers/clk/qcom/
Dgcc-ipq806x.c33 .l_reg = 0x30c4,
34 .m_reg = 0x30c8,
35 .n_reg = 0x30cc,
36 .config_reg = 0x30d4,
37 .mode_reg = 0x30c0,
38 .status_reg = 0x30d8,
49 .enable_reg = 0x34c0,
50 .enable_mask = BIT(0),
62 .l_reg = 0x3164,
63 .m_reg = 0x3168,
[all …]
/linux-6.12.1/drivers/gpu/drm/meson/
Dmeson_registers.h18 #define VPP2_DUMMY_DATA 0x1900
19 #define VPP2_LINE_IN_LENGTH 0x1901
20 #define VPP2_PIC_IN_HEIGHT 0x1902
21 #define VPP2_SCALE_COEF_IDX 0x1903
22 #define VPP2_SCALE_COEF 0x1904
23 #define VPP2_VSC_REGION12_STARTP 0x1905
24 #define VPP2_VSC_REGION34_STARTP 0x1906
25 #define VPP2_VSC_REGION4_ENDP 0x1907
26 #define VPP2_VSC_START_PHASE_STEP 0x1908
27 #define VPP2_VSC_REGION0_PHASE_SLOPE 0x1909
[all …]
/linux-6.12.1/drivers/net/usb/
Dlan78xx.c50 #define FLOW_THRESHOLD(n) ((((n) + 511) / 512) & 0x7F)
51 #define FLOW_CTRL_THRESHOLD(on, off) ((FLOW_THRESHOLD(on) << 0) | \
63 #define DEFAULT_BULK_IN_DELAY (0x0800)
73 #define LAN78XX_USB_VENDOR_ID (0x0424)
74 #define LAN7800_USB_PRODUCT_ID (0x7800)
75 #define LAN7850_USB_PRODUCT_ID (0x7850)
76 #define LAN7801_USB_PRODUCT_ID (0x7801)
77 #define LAN78XX_EEPROM_MAGIC (0x78A5)
78 #define LAN78XX_OTP_MAGIC (0x78F3)
79 #define AT29M2AF_USB_VENDOR_ID (0x07C9)
[all …]
/linux-6.12.1/drivers/net/ethernet/broadcom/
Dtg3.h17 #define TG3_64BIT_REG_HIGH 0x00UL
18 #define TG3_64BIT_REG_LOW 0x04UL
21 #define TG3_BDINFO_HOST_ADDR 0x0UL /* 64-bit */
22 #define TG3_BDINFO_MAXLEN_FLAGS 0x8UL /* 32-bit */
23 #define BDINFO_FLAGS_USE_EXT_RECV 0x00000001 /* ext rx_buffer_desc */
24 #define BDINFO_FLAGS_DISABLED 0x00000002
25 #define BDINFO_FLAGS_MAXLEN_MASK 0xffff0000
27 #define TG3_BDINFO_NIC_ADDR 0xcUL /* 32-bit */
28 #define TG3_BDINFO_SIZE 0x10UL
41 #define TG3PCI_VENDOR 0x00000000
[all …]

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