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/linux-6.12.1/Documentation/devicetree/bindings/phy/
Damlogic,meson8-hdmi-tx-phy.yaml23 pattern: "^hdmi-phy@[0-9a-f]+$"
43 const: 0
55 reg = <0x3a0 0xc>;
57 #phy-cells = <0>;
62 reg = <0x3a0 0xc>;
64 #phy-cells = <0>;
/linux-6.12.1/arch/sh/drivers/pci/
Dfixups-se7751.c14 case 0: return evt2irq(0x3a0); in pcibios_map_platform_irq()
15 case 1: return evt2irq(0x3a0); /* AMD Ethernet controller */ in pcibios_map_platform_irq()
25 #define PCIMCR_MRSET_OFF 0xBFFFFFFF
26 #define PCIMCR_RFSH_OFF 0xFFFFFFFB
58 bcr1 = bcr1 | 0x00080000; /* Enable Bit 19, BREQEN */ in pci_fixup_pcic()
61 bcr1 = bcr1 | 0x40080000; /* Enable Bit 19 BREQEN, set PCIC to slave */ in pci_fixup_pcic()
72 PCIC_WRITE(SH7751_PCIINTM, 0x0000c3ff); in pci_fixup_pcic()
73 PCIC_WRITE(SH7751_PCIAINTM, 0x0000380f); in pci_fixup_pcic()
76 PCIC_WRITE(SH7751_PCICONF1, 0xF39000C7); /* Bus Master, Mem & I/O access */ in pci_fixup_pcic()
77 PCIC_WRITE(SH7751_PCICONF2, 0x00000000); /* PCI Class code & Revision ID */ in pci_fixup_pcic()
[all …]
/linux-6.12.1/arch/sh/include/mach-common/mach/
Dlboxre2.h12 #define IRQ_CF1 evt2irq(0x320) /* CF1 */
13 #define IRQ_CF0 evt2irq(0x340) /* CF0 */
14 #define IRQ_INTD evt2irq(0x360) /* INTD */
15 #define IRQ_ETH1 evt2irq(0x380) /* Ether1 */
16 #define IRQ_ETH0 evt2irq(0x3a0) /* Ether0 */
17 #define IRQ_INTA evt2irq(0x3c0) /* INTA */
/linux-6.12.1/include/linux/regulator/
Dmt6315-regulator.h14 MT6315_VBUCK1 = 0,
22 #define MT6315_TOP2_ELR7 0x139
23 #define MT6315_TOP_TMA_KEY 0x39F
24 #define MT6315_TOP_TMA_KEY_H 0x3A0
25 #define MT6315_BUCK_TOP_CON0 0x1440
26 #define MT6315_BUCK_TOP_CON1 0x1443
27 #define MT6315_BUCK_TOP_ELR0 0x1449
28 #define MT6315_BUCK_TOP_ELR2 0x144B
29 #define MT6315_BUCK_TOP_ELR4 0x144D
30 #define MT6315_BUCK_TOP_ELR6 0x144F
[all …]
/linux-6.12.1/arch/sh/include/mach-landisk/mach/
Diodata_landisk.h16 #define PA_USB 0xa4000000 /* USB Controller M66590 */
18 #define PA_ATARST 0xb0000000 /* ATA/FATA Access Control Register */
19 #define PA_LED 0xb0000001 /* LED Control Register */
20 #define PA_STATUS 0xb0000002 /* Switch Status Register */
21 #define PA_SHUTDOWN 0xb0000003 /* Shutdown Control Register */
22 #define PA_PCIPME 0xb0000004 /* PCI PME Status Register */
23 #define PA_IMASK 0xb0000005 /* Interrupt Mask Register */
25 #define PA_PWRINT_CLR 0xb0000006 /* Shutdown Interrupt clear Register */
27 #define PA_PIDE_OFFSET 0x40 /* CF IDE Offset */
28 #define PA_SIDE_OFFSET 0x40 /* HDD IDE Offset */
[all …]
/linux-6.12.1/arch/sh/include/mach-se/mach/
Dse7751.h19 #define PA_ROM 0x00000000 /* EPROM */
20 #define PA_ROM_SIZE 0x00400000 /* EPROM size 4M byte */
21 #define PA_FROM 0x01000000 /* EPROM */
22 #define PA_FROM_SIZE 0x00400000 /* EPROM size 4M byte */
23 #define PA_EXT1 0x04000000
24 #define PA_EXT1_SIZE 0x04000000
25 #define PA_EXT2 0x08000000
26 #define PA_EXT2_SIZE 0x04000000
27 #define PA_SDRAM 0x0c000000
28 #define PA_SDRAM_SIZE 0x04000000
[all …]
/linux-6.12.1/arch/arm64/boot/dts/freescale/
Dimx8mp-pinfunc.h13 #define MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x014 0x274 0x000 0x0 0x0
14 #define MX8MP_IOMUXC_GPIO1_IO00__CCM_ENET_PHY_REF_CLK_ROOT 0x014 0x274 0x000 0x1 0x0
15 #define MX8MP_IOMUXC_GPIO1_IO00__ISP_FL_TRIG_0 0x014 0x274 0x5D4 0x3 0x0
16 #define MX8MP_IOMUXC_GPIO1_IO00__CCM_EXT_CLK1 0x014 0x274 0x000 0x6 0x0
17 #define MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x018 0x278 0x000 0x0 0x0
18 #define MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x018 0x278 0x000 0x1 0x0
19 #define MX8MP_IOMUXC_GPIO1_IO01__ISP_SHUTTER_TRIG_0 0x018 0x278 0x5DC 0x3 0x0
20 #define MX8MP_IOMUXC_GPIO1_IO01__CCM_EXT_CLK2 0x018 0x278 0x000 0x6 0x0
21 #define MX8MP_IOMUXC_GPIO1_IO02__GPIO1_IO02 0x01C 0x27C 0x000 0x0 0x0
22 #define MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x01C 0x27C 0x000 0x1 0x0
[all …]
Dimx8mn-pinfunc.h14 …ne MX8MN_IOMUXC_BOOT_MODE2_CCMSRCGPCMIX_BOOT_MODE2 0x020 0x25C 0x000 0x0 0x0
15 …ne MX8MN_IOMUXC_BOOT_MODE2_I2C1_SCL 0x020 0x25C 0x55C 0x1 0x3
16 …ne MX8MN_IOMUXC_BOOT_MODE3_CCMSRCGPCMIX_BOOT_MODE3 0x024 0x260 0x000 0x0 0x0
17 …ne MX8MN_IOMUXC_BOOT_MODE3_I2C1_SDA 0x024 0x260 0x56C 0x1 0x3
18 …ne MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0x0
19 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x000 0x1 0x0
20 …ne MX8MN_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0x0
21 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0x0
22 …ne MX8MN_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0x0
23 …ne MX8MN_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0x0
[all …]
Dimx8mm-pinfunc.h14 #define MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0
15 #define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0
16 #define MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0
17 #define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0
18 #define MX8MM_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0
19 #define MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0
20 #define MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0
21 #define MX8MM_IOMUXC_GPIO1_IO01_ANAMIX_REF_CLK_24M 0x02C 0x294 0x4BC 0x5 0
22 #define MX8MM_IOMUXC_GPIO1_IO01_CCMSRCGPCMIX_EXT_CLK2 0x02C 0x294 0x000 0x6 0
23 #define MX8MM_IOMUXC_GPIO1_IO01_SJC_ACTIVE 0x02C 0x294 0x000 0x7 0
[all …]
/linux-6.12.1/arch/arm/boot/dts/nxp/imx/
Dimxrt1170-pinfunc.h10 #define IMX_PAD_SION 0x40000000
17 #define IOMUXC_GPIO_LPSR_00_FLEXCAN3_TX 0x000 0x040 0x0 0x0 0x0
18 #define IOMUXC_GPIO_LPSR_00_MIC_CLK 0x000 0x040 0x0 0x1 0x0
19 #define IOMUXC_GPIO_LPSR_00_MQS_RIGHT 0x000 0x040 0x0 0x2 0x0
20 #define IOMUXC_GPIO_LPSR_00_ARM_CM4_EVENTO 0x000 0x040 0x0 0x3 0x0
21 #define IOMUXC_GPIO_LPSR_00_GPIO_MUX6_IO00 0x000 0x040 0x0 0x5 0x0
22 #define IOMUXC_GPIO_LPSR_00_LPUART12_TXD 0x000 0x040 0x0B0 0x6 0x0
23 #define IOMUXC_GPIO_LPSR_00_SAI4_MCLK 0x000 0x040 0x0C8 0x7 0x0
24 #define IOMUXC_GPIO_LPSR_00_GPIO12_IO00 0x000 0x040 0x0 0xA 0x0
26 #define IOMUXC_GPIO_LPSR_01_FLEXCAN3_RX 0x004 0x044 0x080 0x0 0x0
[all …]
Dimxrt1050-pinfunc.h10 #define IMX_PAD_SION 0x40000000
17 #define MXRT1050_IOMUXC_GPIO_EMC_00_SEMC_DA00 0x014 0x204 0x000 0x0 0x0
18 #define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXPWM4_PWM0_A 0x014 0x204 0x494 0x1 0x0
19 #define MXRT1050_IOMUXC_GPIO_EMC_00_LPSPI2_SCK 0x014 0x204 0x500 0x2 0x1
20 #define MXRT1050_IOMUXC_GPIO_EMC_00_XBAR_INOUT2 0x014 0x204 0x60C 0x3 0x0
21 #define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXIO1_D00 0x014 0x204 0x000 0x4 0x0
22 #define MXRT1050_IOMUXC_GPIO_EMC_00_GPIO4_IO00 0x014 0x204 0x000 0x5 0x0
24 #define MXRT1050_IOMUXC_GPIO_EMC_01_SEMC_DA01 0x018 0x208 0x000 0x0 0x0
25 #define MXRT1050_IOMUXC_GPIO_EMC_01_FLEXPWM4_PWM0_B 0x018 0x208 0x000 0x1 0x0
26 #define MXRT1050_IOMUXC_GPIO_EMC_01_LPSPI2_PCS0 0x018 0x208 0x4FC 0x2 0x1
[all …]
Dimx25-pinfunc.h16 #define MX25_PAD_A10__A10 0x008 0x000 0x000 0x00 0x000
17 #define MX25_PAD_A10__GPIO_4_0 0x008 0x000 0x000 0x05 0x000
19 #define MX25_PAD_A13__A13 0x00c 0x22C 0x000 0x00 0x000
20 #define MX25_PAD_A13__GPIO_4_1 0x00c 0x22C 0x000 0x05 0x000
21 #define MX25_PAD_A13__LCDC_CLS 0x00c 0x22C 0x000 0x07 0x000
23 #define MX25_PAD_A14__A14 0x010 0x230 0x000 0x00 0x000
24 #define MX25_PAD_A14__GPIO_2_0 0x010 0x230 0x000 0x05 0x000
25 #define MX25_PAD_A14__SIM1_CLK1 0x010 0x230 0x000 0x06 0x000
26 #define MX25_PAD_A14__LCDC_SPL 0x010 0x230 0x000 0x07 0x000
28 #define MX25_PAD_A15__A15 0x014 0x234 0x000 0x00 0x000
[all …]
Dimx6q-pinfunc.h13 #define MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x04c 0x360 0x000 0x0 0x0
14 #define MX6QDL_PAD_SD2_DAT1__ECSPI5_SS0 0x04c 0x360 0x834 0x1 0x0
15 #define MX6QDL_PAD_SD2_DAT1__EIM_CS2_B 0x04c 0x360 0x000 0x2 0x0
16 #define MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x04c 0x360 0x7c8 0x3 0x0
17 #define MX6QDL_PAD_SD2_DAT1__KEY_COL7 0x04c 0x360 0x8f0 0x4 0x0
18 #define MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x04c 0x360 0x000 0x5 0x0
19 #define MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x050 0x364 0x000 0x0 0x0
20 #define MX6QDL_PAD_SD2_DAT2__ECSPI5_SS1 0x050 0x364 0x838 0x1 0x0
21 #define MX6QDL_PAD_SD2_DAT2__EIM_CS3_B 0x050 0x364 0x000 0x2 0x0
22 #define MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x050 0x364 0x7b8 0x3 0x0
[all …]
Dimx53-pinfunc.h13 #define MX53_PAD_GPIO_19__KPP_COL_5 0x020 0x348 0x840 0x0 0x0
14 #define MX53_PAD_GPIO_19__GPIO4_5 0x020 0x348 0x000 0x1 0x0
15 #define MX53_PAD_GPIO_19__CCM_CLKO 0x020 0x348 0x000 0x2 0x0
16 #define MX53_PAD_GPIO_19__SPDIF_OUT1 0x020 0x348 0x000 0x3 0x0
17 #define MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2 0x020 0x348 0x000 0x4 0x0
18 #define MX53_PAD_GPIO_19__ECSPI1_RDY 0x020 0x348 0x000 0x5 0x0
19 #define MX53_PAD_GPIO_19__FEC_TDATA_3 0x020 0x348 0x000 0x6 0x0
20 #define MX53_PAD_GPIO_19__SRC_INT_BOOT 0x020 0x348 0x000 0x7 0x0
21 #define MX53_PAD_KEY_COL0__KPP_COL_0 0x024 0x34c 0x000 0x0 0x0
22 #define MX53_PAD_KEY_COL0__GPIO4_6 0x024 0x34c 0x000 0x1 0x0
[all …]
/linux-6.12.1/drivers/net/wireless/intersil/p54/
Dp54usb.h19 #define NET2280_BASE 0x10000000
20 #define NET2280_BASE2 0x20000000
30 #define NET2280_CLK_STOP (0 << LOCAL_CLOCK_FREQUENCY)
44 #define NET2280_DEVINIT 0x00
45 #define NET2280_USBIRQENB1 0x24
46 #define NET2280_IRQSTAT1 0x2c
47 #define NET2280_FIFOCTL 0x38
48 #define NET2280_GPIOCTL 0x50
49 #define NET2280_RELNUM 0x88
50 #define NET2280_EPA_RSP 0x324
[all …]
/linux-6.12.1/drivers/phy/amlogic/
Dphy-meson8-hdmi-tx.c25 #define HHI_HDMI_PHY_CNTL0 0x3a0
27 #define HHI_HDMI_PHY_CNTL0_HDMI_CTL0 GENMASK(15, 0)
29 #define HHI_HDMI_PHY_CNTL1 0x3a4
31 #define HHI_HDMI_PHY_CNTL1_SOFT_RESET BIT(0)
33 #define HHI_HDMI_PHY_CNTL2 0x3a8
53 return 0; in phy_meson8_hdmi_tx_exit()
63 hdmi_ctl0 = 0x1e8b; in phy_meson8_hdmi_tx_power_on()
65 hdmi_ctl0 = 0x4d0b; in phy_meson8_hdmi_tx_power_on()
68 FIELD_PREP(HHI_HDMI_PHY_CNTL0_HDMI_CTL1, 0x08c3) | in phy_meson8_hdmi_tx_power_on()
71 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL1, 0x0); in phy_meson8_hdmi_tx_power_on()
[all …]
/linux-6.12.1/arch/sh/include/mach-sdk7786/mach/
Dfpga.h9 #define SRSTR 0x000
10 #define SRSTR_MAGIC 0x1971 /* Fixed magical read value */
12 #define INTASR 0x010
13 #define INTAMR 0x020
14 #define MODSWR 0x030
15 #define INTTESTR 0x040
16 #define SYSSR 0x050
17 #define NRGPR 0x060
19 #define NMISR 0x070
20 #define NMISR_MAN_NMI BIT(0)
[all …]
/linux-6.12.1/drivers/thermal/ti-soc-thermal/
Ddra752-bandgap.h27 * DRA752_BANDGAP_BASE 0x4a0021e0
34 #define DRA752_BANDGAP_CTRL_1_OFFSET 0x1a0
35 #define DRA752_BANDGAP_STATUS_1_OFFSET 0x1c8
36 #define DRA752_BANDGAP_CTRL_2_OFFSET 0x39c
37 #define DRA752_BANDGAP_STATUS_2_OFFSET 0x3b8
40 #define DRA752_STD_FUSE_OPP_BGAP_CORE_OFFSET 0x8
41 #define DRA752_TEMP_SENSOR_CORE_OFFSET 0x154
42 #define DRA752_BANDGAP_THRESHOLD_CORE_OFFSET 0x1ac
43 #define DRA752_DTEMP_CORE_1_OFFSET 0x20c
44 #define DRA752_DTEMP_CORE_2_OFFSET 0x210
[all …]
/linux-6.12.1/drivers/net/wireless/broadcom/b43/
Dphy_a.h9 #define B43_PHY_VERSION_OFDM B43_PHY_OFDM(0x00) /* Versioning register for A-PHY */
10 #define B43_PHY_BBANDCFG B43_PHY_OFDM(0x01) /* Baseband config */
11 #define B43_PHY_BBANDCFG_RXANT 0x180 /* RX Antenna selection */
13 #define B43_PHY_PWRDOWN B43_PHY_OFDM(0x03) /* Powerdown */
14 #define B43_PHY_CRSTHRES1_R1 B43_PHY_OFDM(0x06) /* CRS Threshold 1 (phy.rev 1 only) */
15 #define B43_PHY_LNAHPFCTL B43_PHY_OFDM(0x1C) /* LNA/HPF control */
16 #define B43_PHY_LPFGAINCTL B43_PHY_OFDM(0x20) /* LPF Gain control */
17 #define B43_PHY_ADIVRELATED B43_PHY_OFDM(0x27) /* FIXME rename */
18 #define B43_PHY_CRS0 B43_PHY_OFDM(0x29)
19 #define B43_PHY_CRS0_EN 0x4000
[all …]
/linux-6.12.1/arch/loongarch/include/asm/
Dloongson.h20 #define LOONGSON_LIO_BASE 0x18000000
21 #define LOONGSON_LIO_SIZE 0x00100000 /* 1M */
24 #define LOONGSON_BOOT_BASE 0x1c000000
25 #define LOONGSON_BOOT_SIZE 0x02000000 /* 32M */
28 #define LOONGSON_REG_BASE 0x1fe00000
29 #define LOONGSON_REG_SIZE 0x00100000 /* 1M */
34 #define LOONGSON_GPIODATA LOONGSON_REG(0x11c)
35 #define LOONGSON_GPIOIE LOONGSON_REG(0x120)
36 #define LOONGSON_REG_GPIO_BASE (LOONGSON_REG_BASE + 0x11c)
46 " st.w %[v], %[hw], 0 \n" in xconf_writel()
[all …]
/linux-6.12.1/drivers/pinctrl/mediatek/
Dpinctrl-mt2701.c38 /* 0E4E8SR 4/8/12/16 */
40 /* 0E2E4SR 2/4/6/8 */
43 MTK_DRV_GRP(2, 16, 0, 2, 2)
47 MTK_PIN_DRV_GRP(0, 0xf50, 0, 1),
48 MTK_PIN_DRV_GRP(1, 0xf50, 0, 1),
49 MTK_PIN_DRV_GRP(2, 0xf50, 0, 1),
50 MTK_PIN_DRV_GRP(3, 0xf50, 0, 1),
51 MTK_PIN_DRV_GRP(4, 0xf50, 0, 1),
52 MTK_PIN_DRV_GRP(5, 0xf50, 0, 1),
53 MTK_PIN_DRV_GRP(6, 0xf50, 0, 1),
[all …]
/linux-6.12.1/drivers/clk/meson/
Dgxbb.h17 #define SCR 0x2C /* 0x0b offset in data sheet */
18 #define TIMEOUT_VALUE 0x3c /* 0x0f offset in data sheet */
20 #define HHI_GP0_PLL_CNTL 0x40 /* 0x10 offset in data sheet */
21 #define HHI_GP0_PLL_CNTL2 0x44 /* 0x11 offset in data sheet */
22 #define HHI_GP0_PLL_CNTL3 0x48 /* 0x12 offset in data sheet */
23 #define HHI_GP0_PLL_CNTL4 0x4c /* 0x13 offset in data sheet */
24 #define HHI_GP0_PLL_CNTL5 0x50 /* 0x14 offset in data sheet */
25 #define HHI_GP0_PLL_CNTL1 0x58 /* 0x16 offset in data sheet */
27 #define HHI_XTAL_DIVN_CNTL 0xbc /* 0x2f offset in data sheet */
28 #define HHI_TIMER90K 0xec /* 0x3b offset in data sheet */
[all …]
/linux-6.12.1/drivers/infiniband/hw/hns/
Dhns_roce_common.h53 } while (0)
108 #define ROCEE_VENDOR_ID_REG 0x0
109 #define ROCEE_VENDOR_PART_ID_REG 0x4
111 #define ROCEE_SYS_IMAGE_GUID_L_REG 0xC
112 #define ROCEE_SYS_IMAGE_GUID_H_REG 0x10
114 #define ROCEE_PORT_GID_L_0_REG 0x50
115 #define ROCEE_PORT_GID_ML_0_REG 0x54
116 #define ROCEE_PORT_GID_MH_0_REG 0x58
117 #define ROCEE_PORT_GID_H_0_REG 0x5C
119 #define ROCEE_BT_CMD_H_REG 0x204
[all …]
/linux-6.12.1/drivers/net/wireless/realtek/rtw88/
Dpci.h17 #define RTK_PCI_CTRL 0x300
20 #define REG_DBI_WDATA_V1 0x03E8
21 #define REG_DBI_RDATA_V1 0x03EC
22 #define REG_DBI_FLAG_V1 0x03F0
28 #define REG_MDIO_V1 0x03F4
29 #define REG_PCIE_MIX_CFG 0x03F8
30 #define BITS_MDIO_ADDR_MASK GENMASK(4, 0)
33 #define RTW_PCI_MDIO_PG_OFFS_G1 0
37 #define RTK_PCIE_LINK_CFG 0x0719
40 #define BIT_CLKREQ_N_PAD BIT(0)
[all …]
/linux-6.12.1/drivers/crypto/qce/
Dregs-v5.h11 #define REG_VERSION 0x000
12 #define REG_STATUS 0x100
13 #define REG_STATUS2 0x104
14 #define REG_ENGINES_AVAIL 0x108
15 #define REG_FIFO_SIZES 0x10c
16 #define REG_SEG_SIZE 0x110
17 #define REG_GOPROC 0x120
18 #define REG_ENCR_SEG_CFG 0x200
19 #define REG_ENCR_SEG_SIZE 0x204
20 #define REG_ENCR_SEG_START 0x208
[all …]

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