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/linux-6.12.1/arch/arm64/boot/dts/qcom/
Dsa8540p-ride.dts34 regulators-0 {
163 pinctrl-0 = <&ethernet0_default>;
170 #size-cells = <0>;
174 compatible = "ethernet-phy-id0141.0dd4";
175 reg = <0x8>;
189 /* Set MODE[2:0] to RGMII_SGMII */
190 <0x12 0x14 0xfff8 0x4>,
191 /* Soft reset required after changing MODE[2:0] */
192 <0x12 0x14 0x7fff 0x8000>;
202 snps,map-to-dma-channel = <0x0>;
[all …]
Dsa8775p-ride.dtsi33 regulators-0 {
266 pinctrl-0 = <&ethernet0_default>;
278 #size-cells = <0>;
287 snps,map-to-dma-channel = <0x0>;
289 snps,priority = <0x1>;
294 snps,map-to-dma-channel = <0x1>;
300 snps,map-to-dma-channel = <0x2>;
306 snps,map-to-dma-channel = <0x3>;
307 snps,priority = <0xc>;
325 snps,send_slope = <0x1000>;
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/net/
Dsnps,dwmac.yaml218 "^queue[0-9]$":
356 "^queue[0-9]$":
370 Queue 0 is reserved for legacy traffic and so no AVB is
644 reg = <0xe0800000 0x8000>;
662 snps,wr_osr_lmt = <0xf>;
663 snps,rd_osr_lmt = <0xf>;
664 snps,blen = <256 128 64 32 0 0 0>;
672 snps,map-to-dma-channel = <0x0>;
673 snps,priority = <0x0>;
681 snps,weight = <0x10>;
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_12_0_0_offset.h29 // base address: 0x4980
30 …SDMA0_DEC_START 0x0000
31 …e regSDMA0_DEC_START_BASE_IDX 0
32 …SDMA0_MCU_MISC_CNTL 0x0001
33 …e regSDMA0_MCU_MISC_CNTL_BASE_IDX 0
34 …SDMA0_UCODE_REV 0x0003
35 …e regSDMA0_UCODE_REV_BASE_IDX 0
36 …SDMA0_GLOBAL_TIMESTAMP_LO 0x0005
37 …e regSDMA0_GLOBAL_TIMESTAMP_LO_BASE_IDX 0
38 …SDMA0_GLOBAL_TIMESTAMP_HI 0x0006
[all …]
Dgc_11_0_3_offset.h29 // base address: 0x4980
30 …SDMA0_DEC_START 0x0000
31 …e regSDMA0_DEC_START_BASE_IDX 0
32 …SDMA0_F32_MISC_CNTL 0x000b
33 …e regSDMA0_F32_MISC_CNTL_BASE_IDX 0
34 …SDMA0_GLOBAL_TIMESTAMP_LO 0x000f
35 …e regSDMA0_GLOBAL_TIMESTAMP_LO_BASE_IDX 0
36 …SDMA0_GLOBAL_TIMESTAMP_HI 0x0010
37 …e regSDMA0_GLOBAL_TIMESTAMP_HI_BASE_IDX 0
38 …SDMA0_POWER_CNTL 0x001a
[all …]
/linux-6.12.1/drivers/net/ethernet/broadcom/bnx2x/
Dbnx2x_dump.h22 #define DRV_DUMP_XSTORM_WAITP_ADDRESS 0x2b8a80
23 #define DRV_DUMP_TSTORM_WAITP_ADDRESS 0x1b8a80
24 #define DRV_DUMP_USTORM_WAITP_ADDRESS 0x338a80
25 #define DRV_DUMP_CSTORM_WAITP_ADDRESS 0x238a80
45 #define BNX2X_DUMP_VERSION 0x61111111
65 static const u32 page_vals_e2[] = {0, 128};
68 {0x58000, 4608, DUMP_CHIP_E2, 0x30}
74 static const u32 page_vals_e3[] = {0, 128};
77 {0x58000, 4608, DUMP_CHIP_E3A0 | DUMP_CHIP_E3B0, 0x30}
81 { 0x2000, 1, 0x1f, 0xfff},
[all …]