Searched +full:0 +full:x30a70000 (Results 1 – 4 of 4) sorted by relevance
9 #define IMX1_UART1_BASE_ADDR 0x0020600010 #define IMX1_UART2_BASE_ADDR 0x0020700014 #define IMX25_UART1_BASE_ADDR 0x43f9000015 #define IMX25_UART2_BASE_ADDR 0x43f9400016 #define IMX25_UART3_BASE_ADDR 0x5000c00017 #define IMX25_UART4_BASE_ADDR 0x5000800018 #define IMX25_UART5_BASE_ADDR 0x5002c00022 #define IMX27_UART1_BASE_ADDR 0x1000a00023 #define IMX27_UART2_BASE_ADDR 0x1000b00024 #define IMX27_UART3_BASE_ADDR 0x1000c000[all …]
65 maximum: 0xff77 port@0:106 - port@0129 reg = <0x30a70000 0x1000>;145 fsl,mipi-phy-gpr = <&iomuxc_gpr 0x88>;151 #size-cells = <0>;153 port@0 {154 reg = <0>;
56 #size-cells = <0>;63 arm,psci-suspend-param = <0x0010000>;71 cpu0: cpu@0 {74 reg = <0>;94 opp-supported-hw = <0xf>, <0xf>;100 #clock-cells = <0>;107 #clock-cells = <0>;116 #phy-cells = <0>;124 #phy-cells = <0>;143 #size-cells = <0>;[all …]
47 #clock-cells = <0>;54 #clock-cells = <0>;61 #clock-cells = <0>;68 #clock-cells = <0>;75 #clock-cells = <0>;82 #clock-cells = <0>;89 #clock-cells = <0>;96 #clock-cells = <0>;103 #size-cells = <0>;105 A53_0: cpu@0 {[all …]