Home
last modified time | relevance | path

Searched +full:0 +full:x280 (Results 1 – 25 of 349) sorted by relevance

12345678910>>...14

/linux-6.12.1/drivers/clk/mediatek/
Dclk-mt8365-mfg.c14 .set_ofs = 0x4,
15 .clr_ofs = 0x8,
16 .sta_ofs = 0x0,
20 .set_ofs = 0x280,
21 .clr_ofs = 0x280,
22 .sta_ofs = 0x280,
35 GATE_MFG0(CLK_MFG_BG3D, "mfg_bg3d", "mfg_sel", 0),
Dclk-mt6795-apmixedsys.c15 #define REG_REF2USB 0x8
16 #define REG_AP_PLL_CON7 0x1c
17 #define MD1_MTCMOS_OFF BIT(0)
23 #define MT6795_CON0_EN BIT(0)
43 .pll_en_bit = 0, \
47 PLL(CLK_APMIXED_ARMCA53PLL, "armca53pll", 0x200, 0x20c, 0, PLL_AO,
48 21, 0x204, 24, 0x0, 0x204, 0),
49 PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x220, 0x22c, 0xf0000101, HAVE_RST_BAR,
50 21, 0x220, 4, 0x0, 0x224, 0),
51 PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x230, 0x23c, 0xfe000101, HAVE_RST_BAR,
[all …]
Dclk-mt8173-apmixedsys.c17 #define REGOFF_REF2USB 0x8
18 #define REGOFF_HDMI_REF 0x40
52 { .div = 0, .freq = MT8173_PLL_FMAX },
61 PLL(CLK_APMIXED_ARMCA15PLL, "armca15pll", 0x200, 0x20c, 0, PLL_AO,
62 21, 0x204, 24, 0x0, 0x204, 0),
63 PLL(CLK_APMIXED_ARMCA7PLL, "armca7pll", 0x210, 0x21c, 0, PLL_AO,
64 21, 0x214, 24, 0x0, 0x214, 0),
65 PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x220, 0x22c, 0xf0000100, HAVE_RST_BAR, 21,
66 0x220, 4, 0x0, 0x224, 0),
67 PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x230, 0x23c, 0xfe000000, HAVE_RST_BAR, 7,
[all …]
/linux-6.12.1/drivers/gpu/drm/msm/disp/dpu1/catalog/
Ddpu_8_0_sc8280xp.h23 .base = 0x0, .len = 0x494,
26 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
27 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
28 [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
29 [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
30 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
31 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
32 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
33 [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
34 [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
[all …]
Ddpu_9_2_x1e80100.h11 .max_mixer_blendstages = 0xb,
22 .base = 0, .len = 0x494,
25 [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
33 .base = 0x15000, .len = 0x290,
38 .base = 0x16000, .len = 0x290,
43 .base = 0x17000, .len = 0x290,
48 .base = 0x18000, .len = 0x290,
53 .base = 0x19000, .len = 0x290,
58 .base = 0x1a000, .len = 0x290,
67 .base = 0x4000, .len = 0x344,
[all …]
Ddpu_4_0_sdm845.h12 .max_mixer_blendstages = 0xb,
25 .base = 0x0, .len = 0x45c,
28 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
29 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
30 [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
31 [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
32 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
33 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
34 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
35 [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
[all …]
Ddpu_3_0_msm8998.h12 .max_mixer_blendstages = 0x7,
25 .base = 0x0, .len = 0x458,
28 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
29 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
30 [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
31 [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
32 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
33 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
34 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 },
35 [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 12 },
[all …]
Ddpu_3_2_sdm660.h11 .max_mixer_blendstages = 0x7,
24 .base = 0x0, .len = 0x458,
27 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
28 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
29 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
30 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
31 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 },
32 [DPU_CLK_CTRL_CURSOR0] = { .reg_off = 0x3a8, .bit_off = 16 },
39 .base = 0x1000, .len = 0x94,
44 .base = 0x1200, .len = 0x94,
[all …]
Ddpu_5_1_sc8180x.h12 .max_mixer_blendstages = 0xb,
25 .base = 0x0, .len = 0x45c,
28 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
29 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
30 [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
31 [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
32 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
33 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
34 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
35 [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
[all …]
Ddpu_3_3_sdm630.h11 .max_mixer_blendstages = 0x7,
24 .base = 0x0, .len = 0x458,
27 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
28 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
29 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
30 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 },
31 [DPU_CLK_CTRL_CURSOR0] = { .reg_off = 0x3a8, .bit_off = 16 },
38 .base = 0x1000, .len = 0x94,
43 .base = 0x1200, .len = 0x94,
47 .base = 0x1400, .len = 0x94,
[all …]
/linux-6.12.1/drivers/clk/rockchip/
Dclk.h29 #define BOOST_PLL_H_CON(x) ((x) * 0x4)
30 #define BOOST_CLK_CON 0x0008
31 #define BOOST_BOOST_CON 0x000c
32 #define BOOST_SWITCH_CNT 0x0010
33 #define BOOST_HIGH_PERF_CNT0 0x0014
34 #define BOOST_HIGH_PERF_CNT1 0x0018
35 #define BOOST_STATIS_THRESHOLD 0x001c
36 #define BOOST_SHORT_SWITCH_CNT 0x0020
37 #define BOOST_SWITCH_THRESHOLD 0x0024
38 #define BOOST_FSM_STATUS 0x0028
[all …]
/linux-6.12.1/arch/sh/boards/
Dboard-sh2007.c21 REGULATOR_SUPPLY("vddvario", "smsc911x.0"),
22 REGULATOR_SUPPLY("vdd33a", "smsc911x.0"),
34 [0] = {
36 .end = SMC0_BASE + 0xff,
40 .start = evt2irq(0x240),
41 .end = evt2irq(0x240),
47 [0] = {
49 .end = SMC1_BASE + 0xff,
53 .start = evt2irq(0x280),
54 .end = evt2irq(0x280),
[all …]
/linux-6.12.1/drivers/clk/meson/
Dmeson8b.h16 * Register offsets from the HardKernel[0] data sheet are listed in comment
20 * [0] https://dn.odroid.com/S805/Datasheet/S805_Datasheet%20V0.8%2020150126.pdf
22 #define HHI_GP_PLL_CNTL 0x40 /* 0x10 offset in data sheet */
23 #define HHI_GP_PLL_CNTL2 0x44 /* 0x11 offset in data sheet */
24 #define HHI_GP_PLL_CNTL3 0x48 /* 0x12 offset in data sheet */
25 #define HHI_GP_PLL_CNTL4 0x4C /* 0x13 offset in data sheet */
26 #define HHI_GP_PLL_CNTL5 0x50 /* 0x14 offset in data sheet */
27 #define HHI_VIID_CLK_DIV 0x128 /* 0x4a offset in data sheet */
28 #define HHI_VIID_CLK_CNTL 0x12c /* 0x4b offset in data sheet */
29 #define HHI_GCLK_MPEG0 0x140 /* 0x50 offset in data sheet */
[all …]
/linux-6.12.1/drivers/soc/tegra/fuse/
Dfuse-tegra30.c21 #define FUSE_BEGIN 0x100
24 #define FUSE_VENDOR_CODE 0x100
25 #define FUSE_FAB_CODE 0x104
26 #define FUSE_LOT_CODE_0 0x108
27 #define FUSE_LOT_CODE_1 0x10c
28 #define FUSE_WAFER_ID 0x110
29 #define FUSE_X_COORDINATE 0x114
30 #define FUSE_Y_COORDINATE 0x118
32 #define FUSE_HAS_REVISION_INFO BIT(0)
46 return 0; in tegra30_fuse_read_early()
[all …]
/linux-6.12.1/arch/arm/boot/compressed/
Dhead-sharpsl.S29 mov r1, #0x10000000 @ Base address of TC6393 chip
30 mov r6, #0x03
31 ldrh r3, [r1, #8] @ Load TC6393XB Revison: This is 0x0003
36 mrc p15, 0, r4, c0, c0 @ Get Processor ID
37 and r4, r4, #0xffffff00
45 mov r6, #0x31 @ Load Magic Init value
46 str r6, [r1, #0x280] @ to SCRATCH_UMSK
47 mov r5, #0x3000
51 mov r6, #0x30 @ Load 2nd Magic Init value
52 str r6, [r1, #0x280] @ to SCRATCH_UMSK
[all …]
/linux-6.12.1/drivers/phy/qualcomm/
Dphy-qcom-qmp-qserdes-txrx-ufs-v6.h9 #define QSERDES_UFS_V6_TX_RES_CODE_LANE_TX 0x28
10 #define QSERDES_UFS_V6_TX_RES_CODE_LANE_RX 0x2c
11 #define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX 0x30
12 #define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_RX 0x34
13 #define QSERDES_UFS_V6_TX_LANE_MODE_1 0x7c
14 #define QSERDES_UFS_V6_TX_FR_DCC_CTRL 0x108
16 #define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE2 0x08
17 #define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4 0x10
18 #define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_SO_GAIN_RATE4 0x24
19 #define QSERDES_UFS_V6_RX_UCDR_SO_SATURATION 0x28
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/display/msm/
Dqcom,sdm670-mdss.yaml42 "^display-controller@[0-9a-f]+$":
50 "^displayport-controller@[0-9a-f]+$":
58 "^dsi@[0-9a-f]+$":
67 "^phy@[0-9a-f]+$":
91 reg = <0x0ae00000 0x1000>;
103 interconnects = <&mmss_noc MASTER_MDP_PORT0 0 &mem_noc SLAVE_EBI_CH0 0>,
104 <&mmss_noc MASTER_MDP_PORT1 0 &mem_noc SLAVE_EBI_CH0 0>;
107 iommus = <&apps_smmu 0x880 0x8>,
108 <&apps_smmu 0xc80 0x8>;
116 reg = <0x0ae01000 0x8f000>,
[all …]
Dqcom,msm8998-mdss.yaml39 "^display-controller@[0-9a-f]+$":
47 "^dsi@[0-9a-f]+$":
57 "^phy@[0-9a-f]+$":
79 reg = <0x0c900000 0x1000>;
93 iommus = <&mmss_smmu 0>;
100 reg = <0x0c901000 0x8f000>,
101 <0x0c9a8e00 0xf0>,
102 <0x0c9b0000 0x2008>,
103 <0x0c9b8000 0x1040>;
114 interrupts = <0>;
[all …]
Dqcom,sdm845-mdss.yaml43 "^display-controller@[0-9a-f]+$":
51 "^displayport-controller@[0-9a-f]+$":
59 "^dsi@[0-9a-f]+$":
69 "^phy@[0-9a-f]+$":
94 reg = <0x0ae00000 0x1000>;
106 iommus = <&apps_smmu 0x880 0x8>,
107 <&apps_smmu 0xc80 0x8>;
112 reg = <0x0ae01000 0x8f000>,
113 <0x0aeb0000 0x2008>;
124 interrupts = <0>;
[all …]
Dqcom,sm8650-mdss.yaml38 "^display-controller@[0-9a-f]+$":
45 "^displayport-controller@[0-9a-f]+$":
52 "^dsi@[0-9a-f]+$":
61 "^phy@[0-9a-f]+$":
81 reg = <0x0ae00000 0x1000>;
97 iommus = <&apps_smmu 0x1c00 0x2>;
105 reg = <0x0ae01000 0x8f000>,
106 <0x0aeb0000 0x2008>;
127 interrupts = <0>;
131 #size-cells = <0>;
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/rtc/
Dsprd,sc2731-rtc.yaml40 #size-cells = <0>;
44 reg = <0x280>;
/linux-6.12.1/drivers/gpu/drm/i915/gt/
Dintel_lrc.c32 * [5:0]: Number of NOPs or registers to set values to in case of
37 * is used for offsets smaller than 0x200 while the latter is for values bigger
42 * [6:0]: Register offset, without considering the engine base.
53 #define POSTED BIT(0) in set_offsets()
54 #define REG(x) (((x) >> 2) | BUILD_BUG_ON_ZERO(x >= 0x200)) in set_offsets()
56 (((x) >> 9) | BIT(7) | BUILD_BUG_ON_ZERO(x >= 0x10000)), \ in set_offsets()
57 (((x) >> 2) & 0x7f) in set_offsets()
58 #define END 0 in set_offsets()
71 count = *data & 0x3f; in set_offsets()
84 u32 offset = 0; in set_offsets()
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/reset/
Damlogic,meson-axg-audio-arb.yaml52 reg = <0x0 0x280 0x0 0x4>;
/linux-6.12.1/Documentation/fault-injection/
Dnvme-fault-injection.rst33 name fault_inject, interval 1, probability 100, space 0, times 1
34 CPU: 0 PID: 0 Comm: swapper/0 Not tainted 4.15.0-rc8+ #2
39 dump_stack+0x5c/0x7d
40 should_fail+0x148/0x170
41 nvme_should_fail+0x2f/0x50 [nvme_core]
42 nvme_process_cq+0xe7/0x1d0 [nvme]
43 nvme_irq+0x1e/0x40 [nvme]
44 __handle_irq_event_percpu+0x3a/0x190
45 handle_irq_event_percpu+0x30/0x70
46 handle_irq_event+0x36/0x60
[all …]
/linux-6.12.1/drivers/net/wireless/ath/ath9k/
Dar9003_aic.h22 #define ATH_AIC_MIN_ROT_DIR_ATT_DB 0
23 #define ATH_AIC_MIN_ROT_QUAD_ATT_DB 0
26 #define ATH_AIC_SRAM_AUTO_INCREMENT 0x80000000
27 #define ATH_AIC_SRAM_GAIN_TABLE_OFFSET 0x280
28 #define ATH_AIC_SRAM_CAL_OFFSET 0x140
29 #define ATH_AIC_SRAM_OFFSET 0x00
31 #define ATH_AIC_BT_JUPITER_CTRL 0x66820
32 #define ATH_AIC_BT_AIC_ENABLE 0x02
35 AIC_CAL_STATE_IDLE = 0,

12345678910>>...14