Searched +full:0 +full:x2655 (Results 1 – 15 of 15) sorted by relevance
65 bits[0:9] - Specifies MID/RID value of a SSI channel as below66 MID/RID value of SSI rx0 = 0x25667 MID/RID value of SSI tx0 = 0x25568 MID/RID value of SSI rx1 = 0x25a69 MID/RID value of SSI tx1 = 0x25970 MID/RID value of SSI rt2 = 0x25f71 MID/RID value of SSI rx3 = 0x26272 MID/RID value of SSI tx3 = 0x26175 bit[11] - LVL = 0, Detects based on the edge77 bit[15] - TM = 0, Single transfer mode[all …]
17 #clock-cells = <0>;19 clock-frequency = <0>;24 #clock-cells = <0>;26 clock-frequency = <0>;32 #clock-cells = <0>;33 clock-frequency = <0>;39 #clock-cells = <0>;41 clock-frequency = <0>;44 cluster0_opp: opp-table-0 {80 reg = <0 0x10001200 0 0xb00>;[all …]
18 #clock-cells = <0>;20 clock-frequency = <0>;25 #clock-cells = <0>;27 clock-frequency = <0>;33 #clock-cells = <0>;34 clock-frequency = <0>;40 #clock-cells = <0>;42 clock-frequency = <0>;45 cluster0_opp: opp-table-0 {74 #size-cells = <0>;[all …]
26 #define ixCLIPPER_DEBUG_REG00 0x000027 #define ixCLIPPER_DEBUG_REG01 0x000128 #define ixCLIPPER_DEBUG_REG02 0x000229 #define ixCLIPPER_DEBUG_REG03 0x000330 #define ixCLIPPER_DEBUG_REG04 0x000431 #define ixCLIPPER_DEBUG_REG05 0x000532 #define ixCLIPPER_DEBUG_REG06 0x000633 #define ixCLIPPER_DEBUG_REG07 0x000734 #define ixCLIPPER_DEBUG_REG08 0x000835 #define ixCLIPPER_DEBUG_REG09 0x0009[all …]
27 #define mmCB_BLEND_RED 0xa10528 #define mmCB_BLEND_GREEN 0xa10629 #define mmCB_BLEND_BLUE 0xa10730 #define mmCB_BLEND_ALPHA 0xa10831 #define mmCB_COLOR_CONTROL 0xa20232 #define mmCB_BLEND0_CONTROL 0xa1e033 #define mmCB_BLEND1_CONTROL 0xa1e134 #define mmCB_BLEND2_CONTROL 0xa1e235 #define mmCB_BLEND3_CONTROL 0xa1e336 #define mmCB_BLEND4_CONTROL 0xa1e4[all …]
27 #define mmCB_BLEND_RED 0xa10528 #define mmCB_BLEND_GREEN 0xa10629 #define mmCB_BLEND_BLUE 0xa10730 #define mmCB_BLEND_ALPHA 0xa10831 #define mmCB_DCC_CONTROL 0xa10932 #define mmCB_COLOR_CONTROL 0xa20233 #define mmCB_BLEND0_CONTROL 0xa1e034 #define mmCB_BLEND1_CONTROL 0xa1e135 #define mmCB_BLEND2_CONTROL 0xa1e236 #define mmCB_BLEND3_CONTROL 0xa1e3[all …]
29 #define TAHITI_GB_ADDR_CONFIG_GOLDEN 0x1201100330 #define VERDE_GB_ADDR_CONFIG_GOLDEN 0x1201000231 #define HAINAN_GB_ADDR_CONFIG_GOLDEN 0x0201000139 #define SI_MAX_BACKENDS_MASK 0xFF40 #define SI_MAX_BACKENDS_PER_SE_MASK 0x0F42 #define SI_MAX_SIMDS_MASK 0x0FFF43 #define SI_MAX_SIMDS_PER_SE_MASK 0x00FF45 #define SI_MAX_PIPES_MASK 0xFF46 #define SI_MAX_PIPES_PER_SIMD_MASK 0x3F47 #define SI_MAX_LDS_NUM 0xFFFF[all …]
27 // base address: 0x4828 …dispdec_VGA_MEM_WRITE_PAGE_ADDR 0x001229 …ne mmdispdec_VGA_MEM_WRITE_PAGE_ADDR_BASE_IDX 033 // base address: 0x4c34 …dispdec_VGA_MEM_READ_PAGE_ADDR 0x001435 …ne mmdispdec_VGA_MEM_READ_PAGE_ADDR_BASE_IDX 039 // base address: 0x040 …DC_PERFMON0_PERFCOUNTER_CNTL 0x002042 …DC_PERFMON0_PERFCOUNTER_CNTL2 0x002144 …DC_PERFMON0_PERFCOUNTER_STATE 0x0022[all …]
27 // base address: 0x130000031 // base address: 0x130000035 // base address: 0x130000039 // base address: 0x130000043 // base address: 0x130000047 // base address: 0x130002051 // base address: 0x130004055 // base address: 0x130006059 // base address: 0x130008063 // base address: 0x13000a0[all …]
27 // base address: 0x028 …VGA_MEM_WRITE_PAGE_ADDR 0x000029 …ne mmVGA_MEM_WRITE_PAGE_ADDR_BASE_IDX 030 …VGA_MEM_READ_PAGE_ADDR 0x000131 …ne mmVGA_MEM_READ_PAGE_ADDR_BASE_IDX 032 …VGA_RENDER_CONTROL 0x000034 …VGA_SEQUENCER_RESET_CONTROL 0x000136 …VGA_MODE_CONTROL 0x000238 …VGA_SURFACE_PITCH_SELECT 0x000340 …VGA_MEMORY_BASE_ADDRESS 0x0004[all …]
8 // base address: 0x09 …VGA_MEM_WRITE_PAGE_ADDR 0x000010 …VGA_MEM_WRITE_PAGE_ADDR 0x000011 …ne mmVGA_MEM_WRITE_PAGE_ADDR_BASE_IDX 012 …VGA_MEM_READ_PAGE_ADDR 0x000113 …ne mmVGA_MEM_READ_PAGE_ADDR_BASE_IDX 014 …VGA_RENDER_CONTROL 0x000016 …VGA_SEQUENCER_RESET_CONTROL 0x000118 …VGA_MODE_CONTROL 0x000220 …VGA_SURFACE_PITCH_SELECT 0x0003[all …]