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/linux-6.12.1/sound/soc/codecs/
Dmt6351.h12 #define MT6351_AFE_UL_DL_CON0 (0x2000 + 0x0000)
13 #define MT6351_AFE_DL_SRC2_CON0_H (0x2000 + 0x0002)
14 #define MT6351_AFE_DL_SRC2_CON0_L (0x2000 + 0x0004)
15 #define MT6351_AFE_DL_SDM_CON0 (0x2000 + 0x0006)
16 #define MT6351_AFE_DL_SDM_CON1 (0x2000 + 0x0008)
17 #define MT6351_AFE_UL_SRC_CON0_H (0x2000 + 0x000a)
18 #define MT6351_AFE_UL_SRC_CON0_L (0x2000 + 0x000c)
19 #define MT6351_AFE_UL_SRC_CON1_H (0x2000 + 0x000e)
20 #define MT6351_AFE_UL_SRC_CON1_L (0x2000 + 0x0010)
21 #define MT6351_AFE_TOP_CON0 (0x2000 + 0x0012)
[all …]
/linux-6.12.1/arch/arm/boot/dts/nxp/mxs/
Dimx23.dtsi32 #size-cells = <0>;
34 cpu@0 {
37 reg = <0>;
45 reg = <0x80000000 0x80000>;
52 reg = <0x80000000 0x40000>;
59 reg = <0x80000000 0x2000>;
64 reg = <0x80004000 0x2000>;
65 interrupts = <0>, <14>, <20>, <0>,
73 reg = <0x80008000 0x2000>;
81 reg = <0x8000c000 0x2000>, <0x8000a000 0x2000>;
[all …]
Dimx28.dtsi43 #size-cells = <0>;
45 cpu@0 {
48 reg = <0>;
56 reg = <0x80000000 0x80000>;
63 reg = <0x80000000 0x3c900>;
70 reg = <0x80000000 0x2000>;
74 reg = <0x80002000 0x2000>;
83 reg = <0x80004000 0x2000>;
87 <87>, <86>, <0>, <0>;
94 reg = <0x80006000 0x800>;
[all …]
/linux-6.12.1/drivers/clk/axs10x/
Di2s_pll_clock.c19 #define PLL_IDIV_REG 0x0
20 #define PLL_FBDIV_REG 0x4
21 #define PLL_ODIV0_REG 0x8
22 #define PLL_ODIV1_REG 0xC
34 { 1024000, 0x104, 0x451, 0x10E38, 0x2000 },
35 { 1411200, 0x104, 0x596, 0x10D35, 0x2000 },
36 { 1536000, 0x208, 0xA28, 0x10B2C, 0x2000 },
37 { 2048000, 0x82, 0x451, 0x10E38, 0x2000 },
38 { 2822400, 0x82, 0x596, 0x10D35, 0x2000 },
39 { 3072000, 0x104, 0xA28, 0x10B2C, 0x2000 },
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/inc/hw/
Ddpp.h44 * - video format conversion from 4:2:0 or 4:2:2 to 4:4:4
99 { 0x2000, 0, 0, 0,
100 0, 0x2000, 0, 0,
101 0, 0, 0x2000, 0 } },
103 { 0x2000, 0, 0, 0,
104 0, 0x2000, 0, 0,
105 0, 0, 0x2000, 0 } },
107 { 0x2cdd, 0x2000, 0, 0xe991,
108 0xe926, 0x2000, 0xf4fd, 0x10ef,
109 0, 0x2000, 0x38b4, 0xe3a6 } },
[all …]
/linux-6.12.1/arch/arm/boot/dts/ti/omap/
Dam57-pruss.dtsi11 reg = <0x4b226000 0x4>,
12 <0x4b226004 0x4>;
23 clocks = <&l4per2_clkctrl DRA7_L4PER2_PRUSS1_CLKCTRL 0>;
27 ranges = <0x00000000 0x4b200000 0x80000>;
29 pruss1: pruss@0 {
31 reg = <0x0 0x80000>;
36 pruss1_mem: memories@0 {
37 reg = <0x0 0x2000>,
38 <0x2000 0x2000>,
39 <0x10000 0x8000>;
[all …]
Ddm816x.dtsi27 #size-cells = <0>;
28 cpu@0 {
31 reg = <0>;
61 reg = <0x44000000 0x10000>;
69 reg = <0x48180000 0x4000>;
72 ranges = <0 0x48180000 0x4000>;
76 #size-cells = <0>;
85 reg = <0x48140000 0x21000>;
89 ranges = <0 0x48140000 0x21000>;
93 reg = <0x800 0x50a>;
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/devfreq/event/
Dsamsung,exynos-ppmu.yaml43 '^ppmu-event[0-9]+(-[a-z0-9]+){,2}$':
80 reg = <0x106a0000 0x2000>;
103 reg = <0x112a0000 0x2000>;
118 reg = <0x10480000 0x2000>;
123 reg = <0x10490000 0x2000>;
134 reg = <0x104a0000 0x2000>;
139 reg = <0x104b0000 0x2000>;
144 reg = <0x104c0000 0x2000>;
149 reg = <0x104d0000 0x2000>;
158 reg = <0x106a0000 0x2000>;
/linux-6.12.1/drivers/reset/
Dreset-uniphier.c19 #define UNIPHIER_RESET_ACTIVE_LOW BIT(0)
44 UNIPHIER_RESETX(2, 0x2000, 2), /* NAND */
45 UNIPHIER_RESETX(8, 0x2000, 10), /* STDMAC (Ether, HSC, MIO) */
50 UNIPHIER_RESETX(2, 0x2000, 2), /* NAND */
51 UNIPHIER_RESETX(6, 0x2000, 12), /* Ether */
52 UNIPHIER_RESETX(8, 0x2000, 10), /* STDMAC (HSC, MIO, RLE) */
53 UNIPHIER_RESETX(12, 0x2000, 6), /* GIO (Ether, SATA, USB3) */
54 UNIPHIER_RESETX(14, 0x2000, 17), /* USB30 */
55 UNIPHIER_RESETX(15, 0x2004, 17), /* USB31 */
56 UNIPHIER_RESETX(28, 0x2000, 18), /* SATA0 */
[all …]
/linux-6.12.1/arch/mips/include/asm/mach-db1x00/
Dbcsr.h23 #define DB1000_BCSR_PHYS_ADDR 0x0E000000
24 #define DB1000_BCSR_HEXLED_OFS 0x01000000
26 #define DB1550_BCSR_PHYS_ADDR 0x0F000000
27 #define DB1550_BCSR_HEXLED_OFS 0x00400000
29 #define PB1550_BCSR_PHYS_ADDR 0x0F000000
30 #define PB1550_BCSR_HEXLED_OFS 0x00800000
32 #define DB1200_BCSR_PHYS_ADDR 0x19800000
33 #define DB1200_BCSR_HEXLED_OFS 0x00400000
35 #define PB1200_BCSR_PHYS_ADDR 0x0D800000
36 #define PB1200_BCSR_HEXLED_OFS 0x00400000
[all …]
/linux-6.12.1/drivers/gpu/drm/nouveau/nvkm/subdev/fb/
Dramnv40.c43 ret = nvbios_pll_parse(bios, 0x04, &pll); in nv40_ram_calc()
50 if (ret < 0) in nv40_ram_calc()
53 ram->ctrl = 0x80000000 | (log2P << 16); in nv40_ram_calc()
56 ram->ctrl |= 0x00000100; in nv40_ram_calc()
59 ram->ctrl |= 0x40000000; in nv40_ram_calc()
63 return 0; in nv40_ram_calc()
74 u32 crtc_mask = 0; in nv40_ram_prog()
79 for (i = 0; i < 2; i++) { in nv40_ram_prog()
80 u32 vbl = nvkm_rd32(device, 0x600808 + (i * 0x2000)); in nv40_ram_prog()
81 u32 cnt = 0; in nv40_ram_prog()
[all …]
/linux-6.12.1/arch/arc/boot/dts/
Dhaps_hs.dts19 reg = <0x0 0x80000000 0x0 0x40000000 /* 1 GB low mem */
20 0x1 0x00000000 0x0 0x40000000>; /* 1 GB highmem */
24 …bootargs = "earlycon=uart8250,mmio32,0xf0000000,115200n8 console=ttyS0,115200n8 debug print-fatal-…
38 ranges = <0x80000000 0x0 0x80000000 0x80000000>;
41 #clock-cells = <0>;
54 reg = <0xf0000000 0x2000>;
71 reg = <0xf0100000 0x2000>;
77 reg = <0xf0102000 0x2000>;
83 reg = <0xf0104000 0x2000>;
89 reg = <0xf0106000 0x2000>;
[all …]
/linux-6.12.1/arch/arm64/boot/dts/actions/
Ds700.dtsi19 #size-cells = <0>;
21 cpu0: cpu@0 {
24 reg = <0x0 0x0>;
31 reg = <0x0 0x1>;
38 reg = <0x0 0x2>;
45 reg = <0x0 0x3>;
56 reg = <0x0 0x1f000000 0x0 0x1000000>;
90 #clock-cells = <0>;
96 #clock-cells = <0>;
107 reg = <0x0 0xe00f1000 0x0 0x1000>,
[all …]
Ds900.dtsi19 #size-cells = <0>;
21 cpu0: cpu@0 {
24 reg = <0x0 0x0>;
31 reg = <0x0 0x1>;
38 reg = <0x0 0x2>;
45 reg = <0x0 0x3>;
56 reg = <0x0 0x1f000000 0x0 0x1000000>;
90 #clock-cells = <0>;
96 #clock-cells = <0>;
102 #clock-cells = <0>;
[all …]
/linux-6.12.1/drivers/accel/habanalabs/include/gaudi2/asic_reg/
Dgaudi2_blocks_linux_driver.h16 #define mmDCORE0_TPC0_ROM_TABLE_BASE 0x0ull
17 #define DCORE0_TPC0_ROM_TABLE_MAX_OFFSET 0x1000
18 #define DCORE0_TPC0_ROM_TABLE_SECTION 0x1000
19 #define mmDCORE0_TPC0_EML_SPMU_BASE 0x1000ull
20 #define DCORE0_TPC0_EML_SPMU_MAX_OFFSET 0x1000
21 #define DCORE0_TPC0_EML_SPMU_SECTION 0x1000
22 #define mmDCORE0_TPC0_EML_ETF_BASE 0x2000ull
23 #define DCORE0_TPC0_EML_ETF_MAX_OFFSET 0x1000
24 #define DCORE0_TPC0_EML_ETF_SECTION 0x1000
25 #define mmDCORE0_TPC0_EML_STM_BASE 0x3000ull
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/soc/ti/
Dti,pruss.yaml36 0x0, but also has access to a secondary Data RAM (primary to the other PRU
37 core) at its address 0x2000. A shared Data RAM, if present, can be accessed
60 pattern: "^(pruss|icssg)@[0-9a-f]+$"
65 - ti,am4376-pruss0 # for AM437x SoC family and PRUSS unit 0
161 const: 0
175 const: 0
209 const: 0
317 "^(pru|rtu|txpru)@[0-9a-f]+$":
370 pruss: pruss@0 {
372 reg = <0x0 0x80000>;
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/remoteproc/
Dti,pru-rproc.yaml19 The K3 SoCs containing ICSSG v1.0 (eg: AM65x SR1.0) also have two Auxiliary
21 containing the revised ICSSG v1.1 (eg: J721E, AM65x SR2.0) have an extra two
46 - ti,am654-tx-pru # for Tx_PRUs in K3 AM65x SR2.0 SoCs
90 pattern: "^rtu@[0-9a-f]+$"
102 pattern: "^txpru@[0-9a-f]+"
106 pattern: "^pru@[0-9a-f]+$"
119 pruss_tm: target-module@300000 { /* 0x4a300000, ap 9 04.0 */
123 ranges = <0x0 0x300000 0x80000>;
125 pruss: pruss@0 {
127 reg = <0x0 0x80000>;
[all …]
/linux-6.12.1/drivers/crypto/inside-secure/
Dsafexcel.h20 #define EIP197_HIA_VERSION_BE 0xca35
21 #define EIP197_HIA_VERSION_LE 0x35ca
22 #define EIP97_VERSION_LE 0x9e61
23 #define EIP196_VERSION_LE 0x3bc4
24 #define EIP197_VERSION_LE 0x3ac5
25 #define EIP96_VERSION_LE 0x9f60
26 #define EIP201_VERSION_LE 0x36c9
27 #define EIP206_VERSION_LE 0x31ce
28 #define EIP207_VERSION_LE 0x30cf
29 #define EIP197_REG_LO16(reg) (reg & 0xffff)
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/net/
Dcortina,gemini-ethernet.yaml38 "^ethernet-port@[0-9]+$":
92 #size-cells = <0>;
106 reg = <0x60000000 0x4000>, /* Global registers, queue */
107 <0x60004000 0x2000>, /* V-bit */
108 <0x60006000 0x2000>; /* A-bit */
113 gmac0: ethernet-port@0 {
115 reg = <0x60008000 0x2000>, /* Port 0 DMA/TOE */
116 <0x6000a000 0x2000>; /* Port 0 GMAC */
128 reg = <0x6000c000 0x2000>, /* Port 1 DMA/TOE */
129 <0x6000e000 0x2000>; /* Port 1 GMAC */
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dce110/
Ddce110_opp_csc_v.c39 /* constrast:0 - 2.0, default 1.0 */
42 #define UNDERLAY_CONTRAST_MIN 0
46 /* Saturation: 0 - 2.0; default 1.0 */
48 #define UNDERLAY_SATURATION_MIN 0
56 #define UNDERLAY_HUE_DEFAULT 0
71 #define UNDERLAY_BRIGHTNESS_DEFAULT 0
79 { 0x2000, 0, 0, 0, 0, 0x2000, 0, 0, 0, 0, 0x2000, 0} },
81 { 0x1B60, 0, 0, 0x200, 0, 0x1B60, 0, 0x200, 0, 0, 0x1B60, 0x200} },
83 { 0xE00, 0xF447, 0xFDB9, 0x1000, 0x82F, 0x1012, 0x31F, 0x200, 0xFB47,
84 0xF6B9, 0xE00, 0x1000} },
[all …]
/linux-6.12.1/include/linux/mfd/wm8350/
Dcore.h27 #define WM8350_RESET_ID 0x00
28 #define WM8350_ID 0x01
29 #define WM8350_REVISION 0x02
30 #define WM8350_SYSTEM_CONTROL_1 0x03
31 #define WM8350_SYSTEM_CONTROL_2 0x04
32 #define WM8350_SYSTEM_HIBERNATE 0x05
33 #define WM8350_INTERFACE_CONTROL 0x06
34 #define WM8350_POWER_MGMT_1 0x08
35 #define WM8350_POWER_MGMT_2 0x09
36 #define WM8350_POWER_MGMT_3 0x0A
[all …]
/linux-6.12.1/drivers/net/ethernet/cirrus/
Dcs89x0.h18 #define PP_ChipID 0x0000 /* offset 0h -> Corp -ID */
22 #define PP_ISAIOB 0x0020 /* IO base address */
23 #define PP_CS8900_ISAINT 0x0022 /* ISA interrupt select */
24 #define PP_CS8920_ISAINT 0x0370 /* ISA interrupt select */
25 #define PP_CS8900_ISADMA 0x0024 /* ISA Rec DMA channel */
26 #define PP_CS8920_ISADMA 0x0374 /* ISA Rec DMA channel */
27 #define PP_ISASOF 0x0026 /* ISA DMA offset */
28 #define PP_DmaFrameCnt 0x0028 /* ISA DMA Frame count */
29 #define PP_DmaByteCnt 0x002A /* ISA DMA Byte count */
30 #define PP_CS8900_ISAMemB 0x002C /* Memory base */
[all …]
/linux-6.12.1/arch/arm64/boot/dts/broadcom/bcmbca/
Dbcm6856.dtsi18 #size-cells = <0>;
20 B53_0: cpu@0 {
23 reg = <0x0 0x0>;
31 reg = <0x0 0x1>;
61 #clock-cells = <0>;
67 #clock-cells = <0>;
81 ranges = <0x0 0x0 0x81000000 0x8000>;
87 reg = <0x1000 0x1000>, /* GICD */
88 <0x2000 0x2000>, /* GICC */
89 <0x4000 0x2000>, /* GICH */
[all …]
/linux-6.12.1/arch/arm/boot/dts/broadcom/
Dbcm6846.dtsi18 #size-cells = <0>;
20 CA7_0: cpu@0 {
23 reg = <0x0>;
31 reg = <0x1>;
62 #clock-cells = <0>;
68 #clock-cells = <0>;
82 ranges = <0 0x81000000 0x8000>;
89 reg = <0x1000 0x1000>,
90 <0x2000 0x2000>,
91 <0x4000 0x2000>,
[all …]
Dbcm63148.dtsi18 #size-cells = <0>;
20 B15_0: cpu@0 {
23 reg = <0x0>;
31 reg = <0x1>;
61 #clock-cells = <0>;
67 #clock-cells = <0>;
81 ranges = <0 0x80030000 0x8000>;
87 reg = <0x1000 0x1000>,
88 <0x2000 0x2000>,
89 <0x4000 0x2000>,
[all …]

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