/linux-6.12.1/drivers/media/dvb-frontends/ |
D | stv090x_reg.h | 13 #define STV090x_MID 0xf100 16 #define STV090x_OFFST_MRELEASE_FIELD 0 19 #define STV090x_DACR1 0xf113 22 #define STV090x_OFFST_DACR1_VALUE_FIELD 0 25 #define STV090x_DACR2 0xf114 26 #define STV090x_OFFST_DACR2_VALUE_FIELD 0 29 #define STV090x_OUTCFG 0xf11c 39 #define STV090x_MODECFG 0xf11d 41 #define STV090x_IRQSTATUS3 0xf120 52 #define STV090x_OFFST_SDVBS1_PRF_1_FIELD 0 [all …]
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/linux-6.12.1/drivers/media/pci/cx25821/ |
D | cx25821-medusa-video.c | 24 u32 value = 0; in medusa_enable_bluefield_output() 25 u32 tmp = 0; in medusa_enable_bluefield_output() 63 value = cx25821_i2c_read(&dev->i2c_bus[0], out_ctrl, &tmp); in medusa_enable_bluefield_output() 64 value &= 0xFFFFFF7F; /* clear BLUE_FIELD_EN */ in medusa_enable_bluefield_output() 66 value |= 0x00000080; /* set BLUE_FIELD_EN */ in medusa_enable_bluefield_output() 67 cx25821_i2c_write(&dev->i2c_bus[0], out_ctrl, value); in medusa_enable_bluefield_output() 69 value = cx25821_i2c_read(&dev->i2c_bus[0], out_ctrl_ns, &tmp); in medusa_enable_bluefield_output() 70 value &= 0xFFFFFF7F; in medusa_enable_bluefield_output() 72 value |= 0x00000080; /* set BLUE_FIELD_EN */ in medusa_enable_bluefield_output() 73 cx25821_i2c_write(&dev->i2c_bus[0], out_ctrl_ns, value); in medusa_enable_bluefield_output() [all …]
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/linux-6.12.1/arch/arm/boot/dts/microchip/ |
D | sam9x60.dtsi | 37 #size-cells = <0>; 39 cpu@0 { 42 reg = <0>; 48 reg = <0x20000000 0x10000000>; 54 #clock-cells = <0>; 59 #clock-cells = <0>; 65 reg = <0x00300000 0x100000>; 68 ranges = <0 0x00300000 0x100000>; 79 #size-cells = <0>; 81 reg = <0x00500000 0x100000 [all …]
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D | lan966x.dtsi | 27 #size-cells = <0>; 29 cpu@0 { 33 reg = <0x0>; 40 #clock-cells = <0>; 46 #clock-cells = <0>; 52 #clock-cells = <0>; 58 #clock-cells = <0>; 68 reg = <0xe00c00a8 0x38>, <0xe00c02cc 0x4>; 90 reg = <0x00200000 0x80000>, 91 <0xe0808000 0x400>; [all …]
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D | sama5d2.dtsi | 29 #size-cells = <0>; 31 cpu@0 { 34 reg = <0>; 41 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 0>; 46 reg = <0x740000 0x1000>; 62 reg = <0x73c000 0x1000>; 78 reg = <0x20000000 0x20000000>; 84 #clock-cells = <0>; 85 clock-frequency = <0>; 90 #clock-cells = <0>; [all …]
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D | sama7g5.dtsi | 31 #size-cells = <0>; 33 cpu0: cpu@0 { 36 reg = <0x0>; 88 hysteresis = <0>; 94 hysteresis = <0>; 100 hysteresis = <0>; 122 #clock-cells = <0>; 127 #clock-cells = <0>; 132 #clock-cells = <0>; 151 reg = <0x100000 0x20000>; [all …]
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D | at91sam9260.dtsi | 41 #size-cells = <0>; 43 cpu@0 { 46 reg = <0>; 52 reg = <0x20000000 0x04000000>; 58 #clock-cells = <0>; 59 clock-frequency = <0>; 64 #clock-cells = <0>; 65 clock-frequency = <0>; 70 #clock-cells = <0>; 77 reg = <0x002ff000 0x2000>; [all …]
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D | at91sam9261.dtsi | 38 #size-cells = <0>; 40 cpu@0 { 43 reg = <0>; 49 reg = <0x20000000 0x08000000>; 55 #clock-cells = <0>; 56 clock-frequency = <0>; 61 #clock-cells = <0>; 62 clock-frequency = <0>; 68 reg = <0x00300000 0x28000>; 71 ranges = <0 0x00300000 0x28000>; [all …]
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D | at91sam9263.dtsi | 40 #size-cells = <0>; 42 cpu@0 { 45 reg = <0>; 51 reg = <0x20000000 0x08000000>; 57 #clock-cells = <0>; 58 clock-frequency = <0>; 63 #clock-cells = <0>; 64 clock-frequency = <0>; 70 reg = <0x00300000 0x14000>; 73 ranges = <0 0x00300000 0x14000>; [all …]
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D | at91sam9rl.dtsi | 43 #size-cells = <0>; 45 cpu@0 { 48 reg = <0>; 54 reg = <0x20000000 0x04000000>; 60 #clock-cells = <0>; 61 clock-frequency = <0>; 66 #clock-cells = <0>; 67 clock-frequency = <0>; 72 #clock-cells = <0>; 79 reg = <0x00300000 0x10000>; [all …]
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/linux-6.12.1/arch/mips/boot/dts/mobileye/ |
D | eyeq6h-pins.dtsi | 9 * [0] | MUX_SEL | 0 - GPIO, 1 - alternative func 14 * [13:12] | PUD | pull-up/pull-down. 0, 3 - no, 1 - PD, 2 - PU 27 0x000 0x200 // I2C0_SCL pin 28 0x004 0x200 // I2C0_SDA pin 33 0x008 0x200 // I2C1_SCL pin 34 0x00c 0x200 // I2C1_SDA pin 39 0x080 1 // GPIO_C4__SMA0_MDC pin 40 0x084 1 // GPIO_C5__SMA0_MDIO pin 44 pinctrl-single,pins = <0x0a8 1>; // UART0 pin group 47 pinctrl-single,pins = <0x0a0 1>; // UART1 pin group [all …]
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/linux-6.12.1/drivers/clk/pistachio/ |
D | clk-pistachio.c | 19 GATE(CLK_MIPS, "mips", "mips_div", 0x104, 0), 20 GATE(CLK_AUDIO_IN, "audio_in", "audio_clk_in_gate", 0x104, 1), 21 GATE(CLK_AUDIO, "audio", "audio_div", 0x104, 2), 22 GATE(CLK_I2S, "i2s", "i2s_div", 0x104, 3), 23 GATE(CLK_SPDIF, "spdif", "spdif_div", 0x104, 4), 24 GATE(CLK_AUDIO_DAC, "audio_dac", "audio_dac_div", 0x104, 5), 25 GATE(CLK_RPU_V, "rpu_v", "rpu_v_div", 0x104, 6), 26 GATE(CLK_RPU_L, "rpu_l", "rpu_l_div", 0x104, 7), 27 GATE(CLK_RPU_SLEEP, "rpu_sleep", "rpu_sleep_div", 0x104, 8), 28 GATE(CLK_WIFI_PLL_GATE, "wifi_pll_gate", "wifi_pll_mux", 0x104, 9), [all …]
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/linux-6.12.1/arch/arm64/boot/dts/ti/ |
D | k3-j721s2-main.dtsi | 13 #clock-cells = <0>; 15 clock-frequency = <0>; 22 reg = <0x0 0x70000000 0x0 0x400000>; 25 ranges = <0x0 0x0 0x70000000 0x400000>; 27 atf-sram@0 { 28 reg = <0x0 0x20000>; 32 reg = <0x1f0000 0x10000>; 36 reg = <0x200000 0x200000>; 42 reg = <0x00 0x00104000 0x00 0x18000>; 45 ranges = <0x00 0x00 0x00104000 0x18000>; [all …]
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/linux-6.12.1/drivers/pmdomain/renesas/ |
D | r8a774a1-sysc.c | 17 { "always-on", 0, 0, R8A774A1_PD_ALWAYS_ON, -1, PD_ALWAYS_ON }, 18 { "ca57-scu", 0x1c0, 0, R8A774A1_PD_CA57_SCU, R8A774A1_PD_ALWAYS_ON, 20 { "ca57-cpu0", 0x80, 0, R8A774A1_PD_CA57_CPU0, R8A774A1_PD_CA57_SCU, 22 { "ca57-cpu1", 0x80, 1, R8A774A1_PD_CA57_CPU1, R8A774A1_PD_CA57_SCU, 24 { "ca53-scu", 0x140, 0, R8A774A1_PD_CA53_SCU, R8A774A1_PD_ALWAYS_ON, 26 { "ca53-cpu0", 0x200, 0, R8A774A1_PD_CA53_CPU0, R8A774A1_PD_CA53_SCU, 28 { "ca53-cpu1", 0x200, 1, R8A774A1_PD_CA53_CPU1, R8A774A1_PD_CA53_SCU, 30 { "ca53-cpu2", 0x200, 2, R8A774A1_PD_CA53_CPU2, R8A774A1_PD_CA53_SCU, 32 { "ca53-cpu3", 0x200, 3, R8A774A1_PD_CA53_CPU3, R8A774A1_PD_CA53_SCU, 34 { "a3vc", 0x380, 0, R8A774A1_PD_A3VC, R8A774A1_PD_ALWAYS_ON }, [all …]
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D | r8a77960-sysc.c | 17 { "always-on", 0, 0, R8A7796_PD_ALWAYS_ON, -1, PD_ALWAYS_ON }, 18 { "ca57-scu", 0x1c0, 0, R8A7796_PD_CA57_SCU, R8A7796_PD_ALWAYS_ON, 20 { "ca57-cpu0", 0x80, 0, R8A7796_PD_CA57_CPU0, R8A7796_PD_CA57_SCU, 22 { "ca57-cpu1", 0x80, 1, R8A7796_PD_CA57_CPU1, R8A7796_PD_CA57_SCU, 24 { "ca53-scu", 0x140, 0, R8A7796_PD_CA53_SCU, R8A7796_PD_ALWAYS_ON, 26 { "ca53-cpu0", 0x200, 0, R8A7796_PD_CA53_CPU0, R8A7796_PD_CA53_SCU, 28 { "ca53-cpu1", 0x200, 1, R8A7796_PD_CA53_CPU1, R8A7796_PD_CA53_SCU, 30 { "ca53-cpu2", 0x200, 2, R8A7796_PD_CA53_CPU2, R8A7796_PD_CA53_SCU, 32 { "ca53-cpu3", 0x200, 3, R8A7796_PD_CA53_CPU3, R8A7796_PD_CA53_SCU, 34 { "cr7", 0x240, 0, R8A7796_PD_CR7, R8A7796_PD_ALWAYS_ON }, [all …]
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D | r8a77961-sysc.c | 17 { "always-on", 0, 0, R8A7796_PD_ALWAYS_ON, -1, PD_ALWAYS_ON }, 18 { "ca57-scu", 0x1c0, 0, R8A7796_PD_CA57_SCU, R8A7796_PD_ALWAYS_ON, 20 { "ca57-cpu0", 0x80, 0, R8A7796_PD_CA57_CPU0, R8A7796_PD_CA57_SCU, 22 { "ca57-cpu1", 0x80, 1, R8A7796_PD_CA57_CPU1, R8A7796_PD_CA57_SCU, 24 { "ca53-scu", 0x140, 0, R8A7796_PD_CA53_SCU, R8A7796_PD_ALWAYS_ON, 26 { "ca53-cpu0", 0x200, 0, R8A7796_PD_CA53_CPU0, R8A7796_PD_CA53_SCU, 28 { "ca53-cpu1", 0x200, 1, R8A7796_PD_CA53_CPU1, R8A7796_PD_CA53_SCU, 30 { "ca53-cpu2", 0x200, 2, R8A7796_PD_CA53_CPU2, R8A7796_PD_CA53_SCU, 32 { "ca53-cpu3", 0x200, 3, R8A7796_PD_CA53_CPU3, R8A7796_PD_CA53_SCU, 34 { "cr7", 0x240, 0, R8A7796_PD_CR7, R8A7796_PD_ALWAYS_ON }, [all …]
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D | r8a774e1-sysc.c | 17 { "always-on", 0, 0, R8A774E1_PD_ALWAYS_ON, -1, PD_ALWAYS_ON }, 18 { "ca57-scu", 0x1c0, 0, R8A774E1_PD_CA57_SCU, R8A774E1_PD_ALWAYS_ON, PD_SCU }, 19 { "ca57-cpu0", 0x80, 0, R8A774E1_PD_CA57_CPU0, R8A774E1_PD_CA57_SCU, PD_CPU_NOCR }, 20 { "ca57-cpu1", 0x80, 1, R8A774E1_PD_CA57_CPU1, R8A774E1_PD_CA57_SCU, PD_CPU_NOCR }, 21 { "ca57-cpu2", 0x80, 2, R8A774E1_PD_CA57_CPU2, R8A774E1_PD_CA57_SCU, PD_CPU_NOCR }, 22 { "ca57-cpu3", 0x80, 3, R8A774E1_PD_CA57_CPU3, R8A774E1_PD_CA57_SCU, PD_CPU_NOCR }, 23 { "ca53-scu", 0x140, 0, R8A774E1_PD_CA53_SCU, R8A774E1_PD_ALWAYS_ON, PD_SCU }, 24 { "ca53-cpu0", 0x200, 0, R8A774E1_PD_CA53_CPU0, R8A774E1_PD_CA53_SCU, PD_CPU_NOCR }, 25 { "ca53-cpu1", 0x200, 1, R8A774E1_PD_CA53_CPU1, R8A774E1_PD_CA53_SCU, PD_CPU_NOCR }, 26 { "ca53-cpu2", 0x200, 2, R8A774E1_PD_CA53_CPU2, R8A774E1_PD_CA53_SCU, PD_CPU_NOCR }, [all …]
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D | r8a77980-sysc.c | 17 { "always-on", 0, 0, R8A77980_PD_ALWAYS_ON, -1, PD_ALWAYS_ON }, 18 { "ca53-scu", 0x140, 0, R8A77980_PD_CA53_SCU, R8A77980_PD_ALWAYS_ON, 20 { "ca53-cpu0", 0x200, 0, R8A77980_PD_CA53_CPU0, R8A77980_PD_CA53_SCU, 22 { "ca53-cpu1", 0x200, 1, R8A77980_PD_CA53_CPU1, R8A77980_PD_CA53_SCU, 24 { "ca53-cpu2", 0x200, 2, R8A77980_PD_CA53_CPU2, R8A77980_PD_CA53_SCU, 26 { "ca53-cpu3", 0x200, 3, R8A77980_PD_CA53_CPU3, R8A77980_PD_CA53_SCU, 28 { "cr7", 0x240, 0, R8A77980_PD_CR7, R8A77980_PD_ALWAYS_ON, 30 { "a3ir", 0x180, 0, R8A77980_PD_A3IR, R8A77980_PD_ALWAYS_ON }, 31 { "a2ir0", 0x400, 0, R8A77980_PD_A2IR0, R8A77980_PD_A3IR }, 32 { "a2ir1", 0x400, 1, R8A77980_PD_A2IR1, R8A77980_PD_A3IR }, [all …]
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D | r8a7795-sysc.c | 17 { "always-on", 0, 0, R8A7795_PD_ALWAYS_ON, -1, PD_ALWAYS_ON }, 18 { "ca57-scu", 0x1c0, 0, R8A7795_PD_CA57_SCU, R8A7795_PD_ALWAYS_ON, 20 { "ca57-cpu0", 0x80, 0, R8A7795_PD_CA57_CPU0, R8A7795_PD_CA57_SCU, 22 { "ca57-cpu1", 0x80, 1, R8A7795_PD_CA57_CPU1, R8A7795_PD_CA57_SCU, 24 { "ca57-cpu2", 0x80, 2, R8A7795_PD_CA57_CPU2, R8A7795_PD_CA57_SCU, 26 { "ca57-cpu3", 0x80, 3, R8A7795_PD_CA57_CPU3, R8A7795_PD_CA57_SCU, 28 { "ca53-scu", 0x140, 0, R8A7795_PD_CA53_SCU, R8A7795_PD_ALWAYS_ON, 30 { "ca53-cpu0", 0x200, 0, R8A7795_PD_CA53_CPU0, R8A7795_PD_CA53_SCU, 32 { "ca53-cpu1", 0x200, 1, R8A7795_PD_CA53_CPU1, R8A7795_PD_CA53_SCU, 34 { "ca53-cpu2", 0x200, 2, R8A7795_PD_CA53_CPU2, R8A7795_PD_CA53_SCU, [all …]
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/linux-6.12.1/drivers/memory/tegra/ |
D | tegra124.c | 16 .id = 0x00, 21 .reg = 0x34c, 22 .shift = 0, 23 .mask = 0xff, 24 .def = 0x0, 28 .id = 0x01, 33 .reg = 0x228, 37 .reg = 0x2e8, 38 .shift = 0, 39 .mask = 0xff, [all …]
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D | tegra210.c | 12 .id = 0x00, 16 .id = 0x01, 21 .reg = 0x228, 25 .reg = 0x2e8, 26 .shift = 0, 27 .mask = 0xff, 28 .def = 0x1e, 32 .id = 0x02, 37 .reg = 0x228, 41 .reg = 0x2f4, [all …]
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/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/bif/ |
D | bif_4_1_sh_mask.h | 27 #define MM_INDEX__MM_OFFSET_MASK 0x7fffffff 28 #define MM_INDEX__MM_OFFSET__SHIFT 0x0 29 #define MM_INDEX__MM_APER_MASK 0x80000000 30 #define MM_INDEX__MM_APER__SHIFT 0x1f 31 #define MM_INDEX_HI__MM_OFFSET_HI_MASK 0xffffffff 32 #define MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0 33 #define MM_DATA__MM_DATA_MASK 0xffffffff 34 #define MM_DATA__MM_DATA__SHIFT 0x0 35 #define CC_BIF_BX_FUSESTRAP0__STRAP_BIF_PX_CAPABLE_MASK 0x2 36 #define CC_BIF_BX_FUSESTRAP0__STRAP_BIF_PX_CAPABLE__SHIFT 0x1 [all …]
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/linux-6.12.1/Documentation/devicetree/bindings/thermal/ |
D | rcar-gen3-thermal.yaml | 110 reg = <0xe6198000 0x100>, 111 <0xe61a0000 0x100>, 112 <0xe61a8000 0x100>; 126 thermal-sensors = <&tsc 0>; 144 reg = <0xe6190000 0x200>, 145 <0xe6198000 0x200>, 146 <0xe61a0000 0x200>, 147 <0xe61a8000 0x200>, 148 <0xe61b0000 0x200>;
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/linux-6.12.1/arch/arm64/boot/dts/arm/ |
D | rtsm_ve-motherboard-rs2.dtsi | 15 reg = <0x140000 0x200>; 21 reg = <0x150000 0x200>; 27 reg = <0x200000 0x200>;
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/linux-6.12.1/arch/arm/boot/dts/ti/omap/ |
D | omap2430.dtsi | 18 ranges = <0 0x49000000 0x31000>; 22 reg = <0x6000 0x1000>; 26 #size-cells = <0>; 35 reg = <0x2000 0x1000>; 39 ranges = <0 0x2000 0x1000>; 44 reg = <0x30 0x0154>; 46 #size-cells = <0>; 49 pinctrl-single,function-mask = <0x3f>; 55 reg = <0x270 0x240>; 58 ranges = <0 0x270 0x240>; [all …]
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