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/linux-6.12.1/arch/mips/include/asm/mach-loongson32/
Dloongson1.h18 #define LS1X_MUX_BASE 0x1fd00420
19 #define LS1X_INTC_BASE 0x1fd01040
20 #define LS1X_GPIO0_BASE 0x1fd010c0
21 #define LS1X_GPIO1_BASE 0x1fd010c4
22 #define LS1X_DMAC_BASE 0x1fd01160
23 #define LS1X_CBUS_BASE 0x1fd011c0
24 #define LS1X_EHCI_BASE 0x1fe00000
25 #define LS1X_OHCI_BASE 0x1fe08000
26 #define LS1X_GMAC0_BASE 0x1fe10000
27 #define LS1X_GMAC1_BASE 0x1fe20000
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/linux-6.12.1/Documentation/devicetree/bindings/interrupt-controller/
Dloongson,eiointc.yaml50 reg = <0x1fe10000 0x10000>;
/linux-6.12.1/Documentation/devicetree/bindings/net/
Dloongson,ls1b-gmac.yaml90 reg = <0x1fe10000 0x10000>;
107 #size-cells = <0>;
110 phy0: ethernet-phy@0 {
111 reg = <0x0>;
Dloongson,ls1c-emac.yaml89 reg = <0x1fe10000 0x10000>;
106 #size-cells = <0>;
110 reg = <0x13>;
/linux-6.12.1/drivers/net/ethernet/stmicro/stmmac/
Ddwmac-loongson1.c18 #define LS1B_GMAC0_BASE (0x1fe10000)
19 #define LS1B_GMAC1_BASE (0x1fe20000)
22 #define LS1X_SYSCON0 (0x0)
23 #define LS1X_SYSCON1 (0x4)
35 #define GMAC0_USE_PWM01 BIT(0)
41 #define PHY_INTF_MII FIELD_PREP(PHY_INTF_SELI, 0)
57 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); in ls1b_dwmac_syscon_init()
69 0); in ls1b_dwmac_syscon_init()
82 regmap_update_bits(regmap, LS1X_SYSCON0, GMAC0_SHUT, 0); in ls1b_dwmac_syscon_init()
92 0); in ls1b_dwmac_syscon_init()
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