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/linux-6.12.1/drivers/net/ethernet/qualcomm/emac/
Demac-phy.c15 #define EMAC_MDIO_CTRL 0x001414
16 #define EMAC_PHY_STS 0x001418
17 #define EMAC_MDIO_EX_CTRL 0x001440
24 #define MDIO_CLK_SEL_BMSK 0x7000000
29 #define MDIO_REG_ADDR_BMSK 0x1f0000
31 #define MDIO_DATA_BMSK 0xffff
32 #define MDIO_DATA_SHFT 0
35 #define PHY_ADDR_BMSK 0x1f0000
38 #define MDIO_CLK_25_4 0
88 return 0; in emac_mdio_write()
[all …]
/linux-6.12.1/drivers/media/rc/
Dir-sony-decoder.c44 return 0; in ir_sony_decode()
62 data->count = 0; in ir_sony_decode()
64 return 0; in ir_sony_decode()
74 return 0; in ir_sony_decode()
88 return 0; in ir_sony_decode()
101 return 0; in ir_sony_decode()
119 device = bitrev8((data->bits << 3) & 0xF8); in ir_sony_decode()
120 subdevice = 0; in ir_sony_decode()
121 function = bitrev8((data->bits >> 4) & 0xFE); in ir_sony_decode()
128 device = bitrev8((data->bits >> 0) & 0xFF); in ir_sony_decode()
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/clock/
Dqcom,gcc-sm6115.yaml48 reg = <0x01400000 0x1f0000>;
Dqcom,gcc-sm6125.yaml48 reg = <0x01400000 0x1f0000>;
Dqcom,sm6375-gcc.yaml43 reg = <0x01400000 0x1f0000>;
Dqcom,gcc-sm8150.yaml49 reg = <0x00100000 0x1f0000>;
Dqcom,gcc-sdx55.yaml49 reg = <0x00100000 0x1f0000>;
Dqcom,gcc-qcm2290.yaml48 reg = <0x01400000 0x1f0000>;
Dqcom,gcc-sm6350.yaml50 reg = <0x00100000 0x1f0000>;
Dqcom,gcc-sm8250.yaml51 reg = <0x00100000 0x1f0000>;
Dqcom,gcc-sc8180x.yaml56 reg = <0x00100000 0x1f0000>;
Dqcom,gcc-sc7180.yaml57 reg = <0x00100000 0x1f0000>;
Dqcom,gcc-sc7280.yaml27 - description: PCIE-0 pipe clock source
29 - description: USF phy rx symbol 0 clock source
31 - description: USF phy tx symbol 0 clock source
68 reg = <0x00100000 0x1f0000>;
Dqcom,gcc-sdm845.yaml72 - description: PCIE 0 Pipe clock source
90 reg = <0x100000 0x1f0000>;
Dqcom,gcc-sm8350.yaml26 - description: PCIE 0 Pipe clock source (Optional clock)
28 - description: UFS card Rx symbol 0 clock source (Optional clock)
30 - description: UFS card Tx symbol 0 clock source (Optional clock)
31 - description: UFS phy Rx symbol 0 clock source (Optional clock)
33 - description: UFS phy Tx symbol 0 clock source (Optional clock)
70 reg = <0x00100000 0x1f0000>;
Dqcom,gcc-sc8280xp.yaml82 reg = <0x00100000 0x1f0000>;
/linux-6.12.1/Documentation/i2c/
Di2c-stub.rst26 explicitly by setting the respective bits (0x03000000) in the functionality
52 value 0x1f0000 would only enable the quick, byte and byte data
/linux-6.12.1/drivers/accel/habanalabs/include/goya/asic_reg/
Dmme_masks.h23 #define MME_ARCH_STATUS_A_SHIFT 0
24 #define MME_ARCH_STATUS_A_MASK 0x1
26 #define MME_ARCH_STATUS_B_MASK 0x2
28 #define MME_ARCH_STATUS_CIN_MASK 0x4
30 #define MME_ARCH_STATUS_COUT_MASK 0x8
32 #define MME_ARCH_STATUS_TE_MASK 0x10
34 #define MME_ARCH_STATUS_LD_MASK 0x20
36 #define MME_ARCH_STATUS_ST_MASK 0x40
38 #define MME_ARCH_STATUS_SB_A_EMPTY_MASK 0x80
40 #define MME_ARCH_STATUS_SB_B_EMPTY_MASK 0x100
[all …]
Dgoya_masks.h180 ) & 0x7FFFFF)
191 #define GOYA_IRQ_HBW_ID_MASK 0x1FFF
192 #define GOYA_IRQ_HBW_ID_SHIFT 0
193 #define GOYA_IRQ_HBW_INTERNAL_ID_MASK 0xE000
195 #define GOYA_IRQ_HBW_AGENT_ID_MASK 0x1F0000
197 #define GOYA_IRQ_HBW_Y_MASK 0xE00000
199 #define GOYA_IRQ_HBW_X_MASK 0x7000000
201 #define GOYA_IRQ_LBW_ID_MASK 0xFF
202 #define GOYA_IRQ_LBW_ID_SHIFT 0
203 #define GOYA_IRQ_LBW_INTERNAL_ID_MASK 0x700
[all …]
/linux-6.12.1/drivers/net/mdio/
Dmdio-moxart.c16 #define REG_PHY_CTRL 0
22 #define REGAD_MASK 0x3e00000
23 #define PHYAD_MASK 0x1f0000
24 #define MIIRDATA_MASK 0xffff
27 #define MIIWDATA_MASK 0xffff
36 u32 ctrl = 0; in moxart_mdio_read()
54 } while (count > 0); in moxart_mdio_read()
65 u32 ctrl = 0; in moxart_mdio_write()
82 return 0; in moxart_mdio_write()
86 } while (count > 0); in moxart_mdio_write()
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/oss/
Doss_2_4_sh_mask.h27 #define IH_VMID_0_LUT__PASID_MASK 0xffff
28 #define IH_VMID_0_LUT__PASID__SHIFT 0x0
29 #define IH_VMID_1_LUT__PASID_MASK 0xffff
30 #define IH_VMID_1_LUT__PASID__SHIFT 0x0
31 #define IH_VMID_2_LUT__PASID_MASK 0xffff
32 #define IH_VMID_2_LUT__PASID__SHIFT 0x0
33 #define IH_VMID_3_LUT__PASID_MASK 0xffff
34 #define IH_VMID_3_LUT__PASID__SHIFT 0x0
35 #define IH_VMID_4_LUT__PASID_MASK 0xffff
36 #define IH_VMID_4_LUT__PASID__SHIFT 0x0
[all …]
Doss_2_0_sh_mask.h27 #define IH_VMID_0_LUT__PASID_MASK 0xffff
28 #define IH_VMID_0_LUT__PASID__SHIFT 0x0
29 #define IH_VMID_1_LUT__PASID_MASK 0xffff
30 #define IH_VMID_1_LUT__PASID__SHIFT 0x0
31 #define IH_VMID_2_LUT__PASID_MASK 0xffff
32 #define IH_VMID_2_LUT__PASID__SHIFT 0x0
33 #define IH_VMID_3_LUT__PASID_MASK 0xffff
34 #define IH_VMID_3_LUT__PASID__SHIFT 0x0
35 #define IH_VMID_4_LUT__PASID_MASK 0xffff
36 #define IH_VMID_4_LUT__PASID__SHIFT 0x0
[all …]
/linux-6.12.1/arch/arm64/boot/dts/freescale/
Dimx8mm-kontron-sl.dtsi19 reg = <0x0 0x40000000 0 0x80000000>;
61 pinctrl-0 = <&pinctrl_ecspi1>;
65 flash@0 {
68 reg = <0>;
75 partition@0 {
77 reg = <0x0 0x1e0000>;
82 reg = <0x1e0000 0x10000>;
87 reg = <0x1f0000 0x10000>;
96 pinctrl-0 = <&pinctrl_i2c1>;
101 reg = <0x25>;
[all …]
/linux-6.12.1/drivers/gpu/drm/xe/regs/
Dxe_engine_regs.h18 #define RENDER_RING_BASE 0x02000
19 #define BSD_RING_BASE 0x1c0000
20 #define BSD2_RING_BASE 0x1c4000
21 #define BSD3_RING_BASE 0x1d0000
22 #define BSD4_RING_BASE 0x1d4000
23 #define XEHP_BSD5_RING_BASE 0x1e0000
24 #define XEHP_BSD6_RING_BASE 0x1e4000
25 #define XEHP_BSD7_RING_BASE 0x1f0000
26 #define XEHP_BSD8_RING_BASE 0x1f4000
27 #define VEBOX_RING_BASE 0x1c8000
[all …]
/linux-6.12.1/arch/arm64/boot/dts/arm/
Drtsm_ve-motherboard.dtsi13 #clock-cells = <0>;
20 #clock-cells = <0>;
27 #clock-cells = <0>;
49 #clock-cells = <0>;
55 arm,vexpress-sysreg,func = <5 0>;
60 arm,vexpress-sysreg,func = <7 0>;
65 arm,vexpress-sysreg,func = <8 0>;
70 arm,vexpress-sysreg,func = <9 0>;
75 arm,vexpress-sysreg,func = <11 0>;
83 ranges = <0 0x8000000 0 0x8000000 0x18000000>;
[all …]

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