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/linux-6.12.1/Documentation/devicetree/bindings/media/
Dmediatek,mt8195-jpegenc.yaml39 "^jpgenc@[0-9a-f]+$":
116 reg = <0 0x1a030000 0 0x10000>;
121 interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH 0>;
129 reg = <0 0x1b030000 0 0x10000>;
134 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH 0>;
/linux-6.12.1/drivers/clk/samsung/
Dclk-exynosautov9.c33 /* Register Offset definitions for CMU_TOP (0x1b240000) */
34 #define PLL_LOCKTIME_PLL_SHARED0 0x0000
35 #define PLL_LOCKTIME_PLL_SHARED1 0x0004
36 #define PLL_LOCKTIME_PLL_SHARED2 0x0008
37 #define PLL_LOCKTIME_PLL_SHARED3 0x000c
38 #define PLL_LOCKTIME_PLL_SHARED4 0x0010
39 #define PLL_CON0_PLL_SHARED0 0x0100
40 #define PLL_CON3_PLL_SHARED0 0x010c
41 #define PLL_CON0_PLL_SHARED1 0x0140
42 #define PLL_CON3_PLL_SHARED1 0x014c
[all …]
/linux-6.12.1/arch/arm64/boot/dts/exynos/
Dexynosautov9.dtsi47 #size-cells = <0>;
81 cpu0: cpu@0 {
84 reg = <0x0>;
91 reg = <0x100>;
98 reg = <0x200>;
105 reg = <0x300>;
112 reg = <0x10000>;
119 reg = <0x10100>;
126 reg = <0x10200>;
133 reg = <0x10300>;
[all …]
/linux-6.12.1/arch/arm64/boot/dts/mediatek/
Dmt8195.dtsi51 #size-cells = <0>;
53 cpu0: cpu@0 {
56 reg = <0x000>;
58 performance-domains = <&performance 0>;
75 reg = <0x100>;
77 performance-domains = <&performance 0>;
94 reg = <0x200>;
96 performance-domains = <&performance 0>;
113 reg = <0x300>;
115 performance-domains = <&performance 0>;
[all …]