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/linux-6.12.1/arch/sparc/include/asm/
Dcontregs.h12 #define AC_M_PCR 0x0000 /* shv Processor Control Reg */
13 #define AC_M_CTPR 0x0100 /* shv Context Table Pointer Reg */
14 #define AC_M_CXR 0x0200 /* shv Context Register */
15 #define AC_M_SFSR 0x0300 /* shv Synchronous Fault Status Reg */
16 #define AC_M_SFAR 0x0400 /* shv Synchronous Fault Address Reg */
17 #define AC_M_AFSR 0x0500 /* hv Asynchronous Fault Status Reg */
18 #define AC_M_AFAR 0x0600 /* hv Asynchronous Fault Address Reg */
19 #define AC_M_RESET 0x0700 /* hv Reset Reg */
20 #define AC_M_RPR 0x1000 /* hv Root Pointer Reg */
21 #define AC_M_TSUTRCR 0x1000 /* s TLB Replacement Ctrl Reg */
[all …]
/linux-6.12.1/arch/arm64/boot/dts/amd/
Damd-seattle-soc.dtsi20 reg = <0x0 0xe1110000 0 0x1000>,
21 <0x0 0xe112f000 0 0x2000>,
22 <0x0 0xe1140000 0 0x2000>,
23 <0x0 0xe1160000 0 0x2000>;
24 interrupts = <1 9 0xf04>;
25 ranges = <0 0 0 0xe1100000 0 0x100000>;
29 reg = <0x0 0x00080000 0 0x1000>;
35 interrupts = <1 13 0xff04>,
36 <1 14 0xff04>,
37 <1 11 0xff04>,
[all …]
/linux-6.12.1/arch/m68k/include/asm/
Dcontregs.h15 #define AC_IDPROM 0x00000000 /* 34 ID PROM, R/O, byte, 32 bytes */
16 #define AC_PAGEMAP 0x10000000 /* 3 Pagemap R/W, long */
17 #define AC_SEGMAP 0x20000000 /* 3 Segment map, byte */
18 #define AC_CONTEXT 0x30000000 /* 34c current mmu-context */
19 #define AC_SENABLE 0x40000000 /* 34c system dvma/cache/reset enable reg*/
20 #define AC_UDVMA_ENB 0x50000000 /* 34 Not used on Sun boards, byte */
21 #define AC_BUS_ERROR 0x60000000 /* 34 Not cleared on read, byte. */
22 #define AC_SYNC_ERR 0x60000000 /* c fault type */
23 #define AC_SYNC_VA 0x60000004 /* c fault virtual address */
24 #define AC_ASYNC_ERR 0x60000008 /* c asynchronous fault type */
[all …]
/linux-6.12.1/arch/arm64/boot/dts/qcom/
Dpm8916.dtsi17 hysteresis = <0>;
23 hysteresis = <0>;
29 hysteresis = <0>;
38 pm8916_0: pmic@0 {
40 reg = <0x0 SPMI_USID>;
42 #size-cells = <0>;
46 reg = <0x800>;
47 mode-bootloader = <0x2>;
48 mode-recovery = <0x1>;
52 interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>;
[all …]
Dpmk8550.dtsi16 mode-recovery = <0x01>;
17 mode-bootloader = <0x02>;
22 pmk8550: pmic@0 {
24 reg = <0x0 SPMI_USID>;
26 #size-cells = <0>;
30 reg = <0x1300>, <0x800>;
35 interrupts = <0x0 0x13 0x7 IRQ_TYPE_EDGE_BOTH>;
42 interrupts = <0x0 0x13 0x6 IRQ_TYPE_EDGE_BOTH>;
49 reg = <0x6100>, <0x6200>;
51 interrupts = <0x0 0x62 0x1 IRQ_TYPE_EDGE_RISING>;
[all …]
Dpmk8350.dtsi13 #define PMK8350_SID 0
21 mode-recovery = <0x01>;
22 mode-bootloader = <0x02>;
31 #size-cells = <0>;
35 reg = <0x1300>, <0x800>;
40 interrupts = <PMK8350_SID 0x13 0x7 IRQ_TYPE_EDGE_BOTH>;
47 interrupts = <PMK8350_SID 0x13 0x6 IRQ_TYPE_EDGE_BOTH>;
54 reg = <0x3100>;
56 #size-cells = <0>;
57 interrupts = <PMK8350_SID 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
[all …]
/linux-6.12.1/arch/arm/mach-omap2/
Dcm2_54xx.h22 #define OMAP54XX_CM_CORE_BASE 0x4a008000
28 #define OMAP54XX_CM_CORE_OCP_SOCKET_INST 0x0000
29 #define OMAP54XX_CM_CORE_CKGEN_INST 0x0100
30 #define OMAP54XX_CM_CORE_COREAON_INST 0x0600
31 #define OMAP54XX_CM_CORE_CORE_INST 0x0700
32 #define OMAP54XX_CM_CORE_IVA_INST 0x1200
33 #define OMAP54XX_CM_CORE_CAM_INST 0x1300
34 #define OMAP54XX_CM_CORE_DSS_INST 0x1400
35 #define OMAP54XX_CM_CORE_GPU_INST 0x1500
36 #define OMAP54XX_CM_CORE_L3INIT_INST 0x1600
[all …]
Dprm54xx.h24 #define OMAP54XX_PRM_BASE 0x4ae06000
31 #define OMAP54XX_PRM_OCP_SOCKET_INST 0x0000
32 #define OMAP54XX_PRM_CKGEN_INST 0x0100
33 #define OMAP54XX_PRM_MPU_INST 0x0300
34 #define OMAP54XX_PRM_DSP_INST 0x0400
35 #define OMAP54XX_PRM_ABE_INST 0x0500
36 #define OMAP54XX_PRM_COREAON_INST 0x0600
37 #define OMAP54XX_PRM_CORE_INST 0x0700
38 #define OMAP54XX_PRM_IVA_INST 0x1200
39 #define OMAP54XX_PRM_CAM_INST 0x1300
[all …]
Dcm2_7xx.h23 #define DRA7XX_CM_CORE_BASE 0x4a008000
29 #define DRA7XX_CM_CORE_OCP_SOCKET_INST 0x0000
30 #define DRA7XX_CM_CORE_CKGEN_INST 0x0104
31 #define DRA7XX_CM_CORE_COREAON_INST 0x0600
32 #define DRA7XX_CM_CORE_CORE_INST 0x0700
33 #define DRA7XX_CM_CORE_IVA_INST 0x0f00
34 #define DRA7XX_CM_CORE_CAM_INST 0x1000
35 #define DRA7XX_CM_CORE_DSS_INST 0x1100
36 #define DRA7XX_CM_CORE_GPU_INST 0x1200
37 #define DRA7XX_CM_CORE_L3INIT_INST 0x1300
[all …]
Dcm2_44xx.h26 #define OMAP4430_CM2_BASE 0x4a008000
32 #define OMAP4430_CM2_OCP_SOCKET_INST 0x0000
33 #define OMAP4430_CM2_CKGEN_INST 0x0100
34 #define OMAP4430_CM2_ALWAYS_ON_INST 0x0600
35 #define OMAP4430_CM2_CORE_INST 0x0700
36 #define OMAP4430_CM2_IVAHD_INST 0x0f00
37 #define OMAP4430_CM2_CAM_INST 0x1000
38 #define OMAP4430_CM2_DSS_INST 0x1100
39 #define OMAP4430_CM2_GFX_INST 0x1200
40 #define OMAP4430_CM2_L3INIT_INST 0x1300
[all …]
Dprm7xx.h26 #define DRA7XX_PRM_BASE 0x4ae06000
33 #define DRA7XX_PRM_OCP_SOCKET_INST 0x0000
34 #define DRA7XX_PRM_CKGEN_INST 0x0100
35 #define DRA7XX_PRM_MPU_INST 0x0300
36 #define DRA7XX_PRM_DSP1_INST 0x0400
37 #define DRA7XX_PRM_IPU_INST 0x0500
38 #define DRA7XX_PRM_COREAON_INST 0x0628
39 #define DRA7XX_PRM_CORE_INST 0x0700
40 #define DRA7XX_PRM_IVA_INST 0x0f00
41 #define DRA7XX_PRM_CAM_INST 0x1000
[all …]
Dprm44xx.h28 #define OMAP4430_PRM_BASE 0x4a306000
35 #define OMAP4430_PRM_OCP_SOCKET_INST 0x0000
36 #define OMAP4430_PRM_CKGEN_INST 0x0100
37 #define OMAP4430_PRM_MPU_INST 0x0300
38 #define OMAP4430_PRM_TESLA_INST 0x0400
39 #define OMAP4430_PRM_ABE_INST 0x0500
40 #define OMAP4430_PRM_ALWAYS_ON_INST 0x0600
41 #define OMAP4430_PRM_CORE_INST 0x0700
42 #define OMAP4430_PRM_IVAHD_INST 0x0f00
43 #define OMAP4430_PRM_CAM_INST 0x1000
[all …]
/linux-6.12.1/drivers/net/wireless/mediatek/mt76/mt7996/
Deeprom.h12 MT_EE_CHIP_ID = 0x000,
13 MT_EE_VERSION = 0x002,
14 MT_EE_MAC_ADDR = 0x004,
15 MT_EE_MAC_ADDR2 = 0x00a,
16 MT_EE_WIFI_CONF = 0x190,
17 MT_EE_MAC_ADDR3 = 0x2c0,
18 MT_EE_RATE_DELTA_2G = 0x1400,
19 MT_EE_RATE_DELTA_5G = 0x147d,
20 MT_EE_RATE_DELTA_6G = 0x154a,
21 MT_EE_TX0_POWER_2G = 0x1300,
[all …]
/linux-6.12.1/drivers/net/ethernet/qualcomm/
Dqca_7k.h21 #define QCA7K_SPI_WRITE (0 << 15)
23 #define QCA7K_SPI_EXTERNAL (0 << 14)
27 #define QCASPI_HW_BUF_LEN 0xC5B
30 #define SPI_REG_BFR_SIZE 0x0100
31 #define SPI_REG_WRBUF_SPC_AVA 0x0200
32 #define SPI_REG_RDBUF_BYTE_AVA 0x0300
33 #define SPI_REG_SPI_CONFIG 0x0400
34 #define SPI_REG_SPI_STATUS 0x0500
35 #define SPI_REG_INTR_CAUSE 0x0C00
36 #define SPI_REG_INTR_ENABLE 0x0D00
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/net/can/
Dmpc5xxx-mscan.txt41 interrupts = <12 0x8>;
43 reg = <0x1300 0x80>;
48 interrupts = <13 0x8>;
50 reg = <0x1380 0x80>;
/linux-6.12.1/Documentation/devicetree/bindings/phy/
Dmediatek,tphy.yaml15 controllers on MediaTek SoCs, includes USB2.0, USB3.0, PCIe and SATA.
22 shared 0x0000 SPLLC
23 0x0100 FMREG
24 u2 port0 0x0800 U2PHY_COM
25 u3 port0 0x0900 U3PHYD
26 0x0a00 U3PHYD_BANK2
27 0x0b00 U3PHYA
28 0x0c00 U3PHYA_DA
29 u2 port1 0x1000 U2PHY_COM
30 u3 port1 0x1100 U3PHYD
[all …]
Dmediatek,xsphy.yaml20 u2 port0 0x0000 MISC
21 0x0100 FMREG
22 0x0300 U2PHY_COM
23 u2 port1 0x1000 MISC
24 0x1100 FMREG
25 0x1300 U2PHY_COM
26 u2 port2 0x2000 MISC
28 u31 common 0x3000 DIG_GLB
29 0x3100 PHYA_GLB
30 u31 port0 0x3400 DIG_LN_TOP
[all …]
/linux-6.12.1/include/linux/soc/samsung/
Dexynos-regs-pmu.h17 #define S5P_CENTRAL_SEQ_CONFIGURATION 0x0200
21 #define S5P_CENTRAL_SEQ_OPTION 0x0208
42 #define EXYNOS_SWRESET 0x0400
44 #define S5P_WAKEUP_STAT 0x0600
46 #define EXYNOS_EINT_WAKEUP_MASK_DISABLED 0xffffffff
47 #define EXYNOS_EINT_WAKEUP_MASK 0x0604
48 #define S5P_WAKEUP_MASK 0x0608
49 #define S5P_WAKEUP_MASK2 0x0614
52 #define EXYNOS4_MIPI_PHY_CONTROL(n) (0x0710 + (n) * 4)
54 #define EXYNOS4_PHY_ENABLE (1 << 0)
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/power/supply/
Dqcom,pm8916-lbc.yaml96 #size-cells = <0>;
100 reg = <0x1000>, <0x1200>, <0x1300>, <0x1600>;
103 interrupts = <0x0 0x10 0 IRQ_TYPE_EDGE_BOTH>,
104 <0x0 0x10 5 IRQ_TYPE_EDGE_BOTH>,
105 <0x0 0x10 6 IRQ_TYPE_EDGE_BOTH>,
106 <0x0 0x10 7 IRQ_TYPE_EDGE_BOTH>,
107 <0x0 0x12 0 IRQ_TYPE_EDGE_BOTH>,
108 <0x0 0x12 1 IRQ_TYPE_EDGE_BOTH>,
109 <0x0 0x13 0 IRQ_TYPE_EDGE_BOTH>,
110 <0x0 0x13 1 IRQ_TYPE_EDGE_BOTH>,
[all …]
/linux-6.12.1/sound/soc/codecs/
Drt1015.h17 #define RT1015_DEVICE_ID_VAL 0x1011
18 #define RT1015_DEVICE_ID_VAL2 0x1015
20 #define RT1015_RESET 0x0000
21 #define RT1015_CLK2 0x0004
22 #define RT1015_CLK3 0x0006
23 #define RT1015_PLL1 0x000a
24 #define RT1015_PLL2 0x000c
25 #define RT1015_DUM_RW1 0x000e
26 #define RT1015_DUM_RW2 0x0010
27 #define RT1015_DUM_RW3 0x0012
[all …]
/linux-6.12.1/drivers/devfreq/event/
Dexynos-ppmu.h13 PPMU_DISABLE = 0,
18 PPMU_PMNCNT0 = 0,
30 PPMU_RO_BUSY_CYCLE_CNT = 0x0,
31 PPMU_WO_BUSY_CYCLE_CNT = 0x1,
32 PPMU_RW_BUSY_CYCLE_CNT = 0x2,
33 PPMU_RO_REQUEST_CNT = 0x3,
34 PPMU_WO_REQUEST_CNT = 0x4,
35 PPMU_RO_DATA_CNT = 0x5,
36 PPMU_WO_DATA_CNT = 0x6,
37 PPMU_RO_LATENCY = 0x12,
[all …]
/linux-6.12.1/include/uapi/linux/
Djoystick.h34 #define JS_VERSION 0x020100
40 #define JS_EVENT_BUTTON 0x01 /* button pressed/released */
41 #define JS_EVENT_AXIS 0x02 /* joystick moved */
42 #define JS_EVENT_INIT 0x80 /* initial state of device */
55 #define JSIOCGVERSION _IOR('j', 0x01, __u32) /* get driver version */
57 #define JSIOCGAXES _IOR('j', 0x11, __u8) /* get number of axes */
58 #define JSIOCGBUTTONS _IOR('j', 0x12, __u8) /* get number of buttons */
59 #define JSIOCGNAME(len) _IOC(_IOC_READ, 'j', 0x13, len) /* get identifier string */
61 #define JSIOCSCORR _IOW('j', 0x21, struct js_corr) /* set correction values */
62 #define JSIOCGCORR _IOR('j', 0x22, struct js_corr) /* get correction values */
[all …]
/linux-6.12.1/sound/soc/mediatek/mt2701/
Dmt2701-reg.h12 #define AUDIO_TOP_CON0 0x0000
13 #define AUDIO_TOP_CON4 0x0010
14 #define AUDIO_TOP_CON5 0x0014
15 #define AFE_DAIBT_CON0 0x001c
16 #define AFE_MRGIF_CON 0x003c
17 #define ASMI_TIMING_CON1 0x0100
18 #define ASMO_TIMING_CON1 0x0104
19 #define PWR1_ASM_CON1 0x0108
20 #define ASYS_TOP_CON 0x0600
21 #define ASYS_I2SIN1_CON 0x0604
[all …]
/linux-6.12.1/sound/soc/kirkwood/
Dkirkwood.h13 #define KIRKWOOD_RECORD_WIN 0
17 #define KIRKWOOD_AUDIO_WIN_BASE_REG(win) (0xA00 + ((win)<<3))
18 #define KIRKWOOD_AUDIO_WIN_CTRL_REG(win) (0xA04 + ((win)<<3))
21 #define KIRKWOOD_RECCTL 0x1000
31 #define KIRKWOOD_RECCTL_MONO_CHAN_LEFT (0<<3)
32 #define KIRKWOOD_RECCTL_SIZE_MASK (7<<0)
33 #define KIRKWOOD_RECCTL_SIZE_16 (7<<0)
34 #define KIRKWOOD_RECCTL_SIZE_16_C (3<<0)
35 #define KIRKWOOD_RECCTL_SIZE_20 (2<<0)
36 #define KIRKWOOD_RECCTL_SIZE_24 (1<<0)
[all …]
/linux-6.12.1/drivers/mfd/
Dsi476x-prop.c25 for (i = 0; i < size; i++) in si476x_core_element_is_in_array()
38 for (i = 0; i < size; i++) in si476x_core_element_is_in_range()
49 0x0000, in si476x_core_is_valid_property_a10()
50 0x0500, 0x0501, in si476x_core_is_valid_property_a10()
51 0x0600, in si476x_core_is_valid_property_a10()
52 0x0709, 0x070C, 0x070D, 0x70E, 0x710, in si476x_core_is_valid_property_a10()
53 0x0718, in si476x_core_is_valid_property_a10()
54 0x1207, 0x1208, in si476x_core_is_valid_property_a10()
55 0x2007, in si476x_core_is_valid_property_a10()
56 0x2300, in si476x_core_is_valid_property_a10()
[all …]

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