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/linux-6.12.1/Documentation/devicetree/bindings/net/
Dmscc,vsc7514-switch.yaml132 reg = <0x1010000 0x10000>,
133 <0x1030000 0x10000>,
134 <0x1080000 0x100>,
135 <0x10e0000 0x10000>,
136 <0x11e0000 0x100>,
137 <0x11f0000 0x100>,
138 <0x1200000 0x100>,
139 <0x1210000 0x100>,
140 <0x1220000 0x100>,
141 <0x1230000 0x100>,
[all …]
/linux-6.12.1/arch/mips/boot/dts/mscc/
Docelot.dtsi11 #size-cells = <0>;
13 cpu@0 {
17 reg = <0>;
26 #address-cells = <0>;
34 #clock-cells = <0>;
40 #clock-cells = <0>;
50 ranges = <0 0x70000000 0x2000000>;
54 cpu_ctrl: syscon@0 {
56 reg = <0x0 0x2c>;
61 reg = <0x70 0x70>;
[all …]
/linux-6.12.1/sound/soc/amd/renoir/
Drn_chip_offset_byte.h12 #define ACP_DMA_CNTL_0 0x1240000
13 #define ACP_DMA_CNTL_1 0x1240004
14 #define ACP_DMA_CNTL_2 0x1240008
15 #define ACP_DMA_CNTL_3 0x124000C
16 #define ACP_DMA_CNTL_4 0x1240010
17 #define ACP_DMA_CNTL_5 0x1240014
18 #define ACP_DMA_CNTL_6 0x1240018
19 #define ACP_DMA_CNTL_7 0x124001C
20 #define ACP_DMA_DSCR_STRT_IDX_0 0x1240020
21 #define ACP_DMA_DSCR_STRT_IDX_1 0x1240024
[all …]
/linux-6.12.1/sound/soc/amd/vangogh/
Dvg_chip_offset_byte.h12 #define ACP_DMA_CNTL_0 0x1240000
13 #define ACP_DMA_CNTL_1 0x1240004
14 #define ACP_DMA_CNTL_2 0x1240008
15 #define ACP_DMA_CNTL_3 0x124000C
16 #define ACP_DMA_CNTL_4 0x1240010
17 #define ACP_DMA_CNTL_5 0x1240014
18 #define ACP_DMA_CNTL_6 0x1240018
19 #define ACP_DMA_CNTL_7 0x124001C
20 #define ACP_DMA_DSCR_STRT_IDX_0 0x1240020
21 #define ACP_DMA_DSCR_STRT_IDX_1 0x1240024
[all …]
/linux-6.12.1/sound/soc/amd/yc/
Dacp6x_chip_offset_byte.h12 #define ACP_DMA_CNTL_0 0x1240000
13 #define ACP_DMA_CNTL_1 0x1240004
14 #define ACP_DMA_CNTL_2 0x1240008
15 #define ACP_DMA_CNTL_3 0x124000C
16 #define ACP_DMA_CNTL_4 0x1240010
17 #define ACP_DMA_CNTL_5 0x1240014
18 #define ACP_DMA_CNTL_6 0x1240018
19 #define ACP_DMA_CNTL_7 0x124001C
20 #define ACP_DMA_DSCR_STRT_IDX_0 0x1240020
21 #define ACP_DMA_DSCR_STRT_IDX_1 0x1240024
[all …]
/linux-6.12.1/sound/soc/amd/raven/
Dchip_offset_byte.h12 #define mmACP_DMA_CNTL_0 0x1240000
13 #define mmACP_DMA_CNTL_1 0x1240004
14 #define mmACP_DMA_CNTL_2 0x1240008
15 #define mmACP_DMA_CNTL_3 0x124000C
16 #define mmACP_DMA_CNTL_4 0x1240010
17 #define mmACP_DMA_CNTL_5 0x1240014
18 #define mmACP_DMA_CNTL_6 0x1240018
19 #define mmACP_DMA_CNTL_7 0x124001C
20 #define mmACP_DMA_DSCR_STRT_IDX_0 0x1240020
21 #define mmACP_DMA_DSCR_STRT_IDX_1 0x1240024
[all …]