Searched +full:0 +full:x12220000 (Results 1 – 5 of 5) sorted by relevance
53 minimum: 062 minimum: 065 minimum: 076 minimum: 079 minimum: 085 - valid value for tx phase shift and rx phase shift is 0 to 7.88 - if CIU clock divider value is 0 (that is divide by 1), both tx and rx89 phase shift clocks should be 0.96 minimum: 099 minimum: 0[all …]
31 #size-cells = <0>;33 cpu0: cpu@0 {36 reg = <0x0>;43 reg = <0x1>;50 reg = <0x2>;57 reg = <0x3>;70 reg = <0x10040000 0x5000>;78 reg = <0x10010000 0x30000>;84 reg = <0x03810000 0x0c>;92 reg = <0x10060000 0x100>;[all …]
178 #size-cells = <0>;194 reg = <0x900>;213 reg = <0x901>;230 bus_leftbus_opp_table: opp-table-0 {249 reg = <0x02020000 0x20000>;252 ranges = <0 0x02020000 0x20000>;254 smp-sram@0 {256 reg = <0x0 0x1000>;261 reg = <0x1f000 0x1000>;267 reg = <0x10023ca0 0x20>;[all …]
47 #size-cells = <0>;60 cpu0: cpu@0 {63 reg = <0>;80 cpu0_opp_table: opp-table-0 {176 reg = <0x02020000 0x30000>;179 ranges = <0 0x02020000 0x30000>;181 smp-sram@0 {183 reg = <0x0 0x1000>;188 reg = <0x2f000 0x1000>;194 reg = <0x10044000 0x20>;[all …]
153 cluster_a15_opp_table: opp-table-0 {270 reg = <0x10d20000 0x1000>;271 ranges = <0x0 0x10d20000 0x6000>;276 reg = <0x4000 0x1000>;281 reg = <0x5000 0x1000>;287 reg = <0x10010000 0x30000>;293 reg = <0x03810000 0x0c>;303 reg = <0x11000000 0x10000>;316 #size-cells = <0>;317 reg = <0x12200000 0x2000>;[all …]