Searched +full:0 +full:x11006000 (Results 1 – 16 of 16) sorted by relevance
82 reg = <0x11006000 0x1000>;
19 #size-cells = <0>;21 cpu@0 {24 reg = <0x0>;29 reg = <0x1>;34 reg = <0x2>;39 reg = <0x3>;47 #clock-cells = <0>;53 #clock-cells = <0>;59 #clock-cells = <0>;65 reg = <0x10008000 0x80>;[all …]
19 #size-cells = <0>;22 cpu@0 {25 reg = <0x0>;30 reg = <0x1>;35 reg = <0x2>;40 reg = <0x3>;54 #clock-cells = <0>;60 #clock-cells = <0>;66 #clock-cells = <0>;78 reg = <0x10008000 0x80>;[all …]
42 #size-cells = <0>;45 cpu0: cpu@0 {48 reg = <0x000>;54 reg = <0x001>;60 reg = <0x100>;66 reg = <0x101>;77 reg = <0 0x80002000 0 0x1000>;90 #clock-cells = <0>;96 #clock-cells = <0>;101 #clock-cells = <0>;[all …]
24 #size-cells = <0>;27 cpu0: cpu@0 {30 reg = <0x0>;38 reg = <0x1>;51 clk20m: oscillator-0 {53 #clock-cells = <0>;60 #clock-cells = <0>;83 reg = <0x10000000 0x1000>;89 reg = <0x10002000 0x1000>;97 reg = <0x10006000 0x1000>;[all …]
73 #size-cells = <0>;76 cpu0: cpu@0 {79 reg = <0x0>;91 reg = <0x1>;103 reg = <0x2>;115 reg = <0x3>;137 #clock-cells = <0>;142 #clock-cells = <0>;147 clk26m: oscillator-0 {149 #clock-cells = <0>;[all …]
92 pinctrl-0: true115 reg = <0x11006000 0x400>;121 pinctrl-0 = <&uart_pin>;
21 cluster0_opp: opp-table-0 {48 #size-cells = <0>;50 cpu0: cpu@0 {53 reg = <0x0>;66 reg = <0x1>;79 reg = <0x2>;92 reg = <0x3>;105 CPU_SLEEP_0_0: cpu-sleep-0-0 {110 arm,psci-suspend-param = <0x0010000>;113 CLUSTER_SLEEP_0: cluster-sleep-0 {[all …]
24 #size-cells = <0>;26 cluster0_opp: opp-table-0 {128 cpu0: cpu@0 {131 reg = <0x0>;135 i-cache-size = <0x8000>;138 d-cache-size = <0x8000>;151 reg = <0x1>;155 i-cache-size = <0x8000>;158 d-cache-size = <0x8000>;171 reg = <0x2>;[all …]
69 #size-cells = <0>;71 cpu0: cpu@0 {74 reg = <0x0 0x0>;89 reg = <0x0 0x1>;111 #clock-cells = <0>;116 #clock-cells = <0>;140 reg = <0 0x43000000 0 0x30000>;150 thermal-sensors = <&thermal 0>;216 reg = <0 0x10000000 0 0x1000>;223 reg = <0 0x10001000 0 0x250>;[all …]
48 #size-cells = <0>;50 cpu0: cpu@0 {54 reg = <0x000>;63 reg = <0x001>;78 reg = <0x002>;93 reg = <0x003>;108 reg = <0x100>;123 reg = <0x101>;138 reg = <0x102>;153 reg = <0x103>;[all …]
22 cluster0_opp: opp-table-0 {66 #size-cells = <0>;85 cpu0: cpu@0 {88 reg = <0x000>;100 reg = <0x001>;113 reg = <0x200>;126 CPU_SLEEP_0: cpu-sleep-0 {132 arm,psci-suspend-param = <0x0010000>;135 CLUSTER_SLEEP_0: cluster-sleep-0 {141 arm,psci-suspend-param = <0x1010000>;[all …]
293 #size-cells = <0>;327 cpu0: cpu@0 {330 reg = <0x000>;353 reg = <0x001>;376 reg = <0x002>;399 reg = <0x003>;422 reg = <0x100>;445 reg = <0x101>;468 reg = <0x102>;491 reg = <0x103>;[all …]
44 #clock-cells = <0>;49 #size-cells = <0>;51 cpu_atlas0: cpu@0 {54 reg = <0x0>;56 i-cache-size = <0xc000>;59 d-cache-size = <0x8000>;68 reg = <0x1>;70 i-cache-size = <0xc000>;73 d-cache-size = <0x8000>;82 reg = <0x2>;[all …]
48 #clock-cells = <0>;53 #size-cells = <0>;91 reg = <0x100>;96 i-cache-size = <0x8000>;99 d-cache-size = <0x8000>;109 reg = <0x101>;112 i-cache-size = <0x8000>;115 d-cache-size = <0x8000>;125 reg = <0x102>;128 i-cache-size = <0x8000>;[all …]
146 0x80000000 | 0xf0000000 | UART0147 0x80004000 | 0xf0004000 | UART1148 0x80008000 | 0xf0008000 | UART2149 0x8000c000 | 0xf000c000 | UART3150 0x80010000 | 0xf0010000 | UART4151 0x80014000 | 0xf0014000 | UART5152 0x80018000 | 0xf0018000 | UART6153 0x8001c000 | 0xf001c000 | UART7154 0x80020000 | 0xf0020000 | UART8155 0x80024000 | 0xf0024000 | UART9[all …]