Searched +full:0 +full:x11003000 (Results 1 – 25 of 26) sorted by relevance
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/linux-6.12.1/Documentation/devicetree/bindings/clock/ |
D | mediatek,mt8195-sys-clock.yaml | 53 reg = <0x10000000 0x1000>; 60 reg = <0x10001000 0x1000>; 67 reg = <0x1000c000 0x1000>; 74 reg = <0x11003000 0x1000>;
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/linux-6.12.1/Documentation/devicetree/bindings/net/bluetooth/ |
D | mediatek,bluetooth.txt | 22 - pinctrl-0: Should contain UART RXD low when the device is powered up to 33 - pinctrl-0: Should contain UART mode pin ctrl 65 reg = <0 0x11003000 0 0x400>; 76 pinctrl-0 = <&uart1_pins_boot>;
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/linux-6.12.1/arch/arm/boot/dts/mediatek/ |
D | mt6582.dtsi | 17 #size-cells = <0>; 19 cpu@0 { 22 reg = <0x0>; 27 reg = <0x1>; 32 reg = <0x2>; 37 reg = <0x3>; 44 #clock-cells = <0>; 50 #clock-cells = <0>; 56 #clock-cells = <0>; 61 reg = <0x10008000 0x80>; [all …]
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D | mt6592.dtsi | 19 #size-cells = <0>; 21 cpu@0 { 24 reg = <0x0>; 29 reg = <0x1>; 34 reg = <0x2>; 39 reg = <0x3>; 44 reg = <0x4>; 49 reg = <0x5>; 54 reg = <0x6>; 59 reg = <0x7>; [all …]
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D | mt8127.dtsi | 19 #size-cells = <0>; 22 cpu@0 { 25 reg = <0x0>; 30 reg = <0x1>; 35 reg = <0x2>; 40 reg = <0x3>; 52 reg = <0 0x80002000 0 0x1000>; 65 #clock-cells = <0>; 71 #clock-cells = <0>; 77 #clock-cells = <0>; [all …]
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D | mt7629.dtsi | 24 #size-cells = <0>; 27 cpu0: cpu@0 { 30 reg = <0x0>; 38 reg = <0x1>; 51 clk20m: oscillator-0 { 53 #clock-cells = <0>; 60 #clock-cells = <0>; 83 reg = <0x10000000 0x1000>; 89 reg = <0x10002000 0x1000>; 97 reg = <0x10006000 0x1000>; [all …]
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D | mt2701.dtsi | 25 #size-cells = <0>; 28 cpu@0 { 31 reg = <0x0>; 36 reg = <0x1>; 41 reg = <0x2>; 46 reg = <0x3>; 57 reg = <0 0x80002000 0 0x1000>; 64 #clock-cells = <0>; 70 #clock-cells = <0>; 73 clk26m: oscillator@0 { [all …]
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D | mt7623.dtsi | 73 #size-cells = <0>; 76 cpu0: cpu@0 { 79 reg = <0x0>; 91 reg = <0x1>; 103 reg = <0x2>; 115 reg = <0x3>; 137 #clock-cells = <0>; 142 #clock-cells = <0>; 147 clk26m: oscillator-0 { 149 #clock-cells = <0>; [all …]
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/linux-6.12.1/arch/arm64/boot/dts/mediatek/ |
D | mt6755.dtsi | 23 #size-cells = <0>; 25 cpu0: cpu@0 { 29 reg = <0x000>; 36 reg = <0x001>; 43 reg = <0x002>; 50 reg = <0x003>; 57 reg = <0x100>; 64 reg = <0x101>; 71 reg = <0x102>; 78 reg = <0x103>; [all …]
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D | mt7988a.dtsi | 15 #size-cells = <0>; 17 cpu@0 { 19 reg = <0x0>; 26 reg = <0x1>; 33 reg = <0x2>; 40 reg = <0x3>; 49 #clock-cells = <0>; 72 reg = <0 0x0c000000 0 0x40000>, /* GICD */ 73 <0 0x0c080000 0 0x200000>, /* GICR */ 74 <0 0x0c400000 0 0x2000>, /* GICC */ [all …]
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D | mt7981b.dtsi | 15 #size-cells = <0>; 17 cpu@0 { 19 reg = <0x0>; 26 reg = <0x1>; 36 #clock-cells = <0>; 52 reg = <0 0x0c000000 0 0x40000>, /* GICD */ 53 <0 0x0c080000 0 0x200000>; /* GICR */ 62 reg = <0 0x10001000 0 0x1000>; 68 reg = <0 0x1001b000 0 0x1000>; 74 reg = <0 0x1001c000 0 0x1000>; [all …]
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D | mt6779.dtsi | 26 #size-cells = <0>; 28 cpu0: cpu@0 { 32 reg = <0x000>; 39 reg = <0x100>; 46 reg = <0x200>; 53 reg = <0x300>; 60 reg = <0x400>; 67 reg = <0x500>; 74 reg = <0x600>; 81 reg = <0x700>; [all …]
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D | mt6797.dtsi | 25 #size-cells = <0>; 27 cpu0: cpu@0 { 31 reg = <0x000>; 38 reg = <0x001>; 45 reg = <0x002>; 52 reg = <0x003>; 59 reg = <0x100>; 66 reg = <0x101>; 73 reg = <0x102>; 80 reg = <0x103>; [all …]
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D | mt8516.dtsi | 21 cluster0_opp: opp-table-0 { 48 #size-cells = <0>; 50 cpu0: cpu@0 { 53 reg = <0x0>; 66 reg = <0x1>; 79 reg = <0x2>; 92 reg = <0x3>; 105 CPU_SLEEP_0_0: cpu-sleep-0-0 { 110 arm,psci-suspend-param = <0x0010000>; 113 CLUSTER_SLEEP_0: cluster-sleep-0 { [all …]
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D | mt7986a.dtsi | 21 #size-cells = <0>; 22 cpu0: cpu@0 { 24 reg = <0x0>; 32 reg = <0x1>; 40 reg = <0x2>; 48 reg = <0x3>; 58 #clock-cells = <0>; 73 reg = <0 0x43000000 0 0x30000>; 79 reg = <0 0x4fc00000 0 0x00100000>; 83 reg = <0 0x4fd00000 0 0x40000>; [all …]
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D | mt8365.dtsi | 24 #size-cells = <0>; 26 cluster0_opp: opp-table-0 { 128 cpu0: cpu@0 { 131 reg = <0x0>; 135 i-cache-size = <0x8000>; 138 d-cache-size = <0x8000>; 151 reg = <0x1>; 155 i-cache-size = <0x8000>; 158 d-cache-size = <0x8000>; 171 reg = <0x2>; [all …]
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D | mt7622.dtsi | 69 #size-cells = <0>; 71 cpu0: cpu@0 { 74 reg = <0x0 0x0>; 89 reg = <0x0 0x1>; 111 #clock-cells = <0>; 116 #clock-cells = <0>; 140 reg = <0 0x43000000 0 0x30000>; 150 thermal-sensors = <&thermal 0>; 216 reg = <0 0x10000000 0 0x1000>; 223 reg = <0 0x10001000 0 0x250>; [all …]
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D | mt6795.dtsi | 48 #size-cells = <0>; 50 cpu0: cpu@0 { 54 reg = <0x000>; 63 reg = <0x001>; 78 reg = <0x002>; 93 reg = <0x003>; 108 reg = <0x100>; 123 reg = <0x101>; 138 reg = <0x102>; 153 reg = <0x103>; [all …]
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D | mt2712e.dtsi | 22 cluster0_opp: opp-table-0 { 66 #size-cells = <0>; 85 cpu0: cpu@0 { 88 reg = <0x000>; 100 reg = <0x001>; 113 reg = <0x200>; 126 CPU_SLEEP_0: cpu-sleep-0 { 132 arm,psci-suspend-param = <0x0010000>; 135 CLUSTER_SLEEP_0: cluster-sleep-0 { 141 arm,psci-suspend-param = <0x1010000>; [all …]
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D | mt8173.dtsi | 53 cluster0_opp: opp-table-0 { 129 #size-cells = <0>; 151 cpu0: cpu@0 { 154 reg = <0x000>; 169 reg = <0x001>; 184 reg = <0x100>; 199 reg = <0x101>; 214 CPU_SLEEP_0: cpu-sleep-0 { 220 arm,psci-suspend-param = <0x0010000>; 242 cpu_suspend = <0x84000001>; [all …]
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D | mt8188.dtsi | 27 #size-cells = <0>; 29 cpu0: cpu@0 { 32 reg = <0x000>; 50 reg = <0x100>; 68 reg = <0x200>; 86 reg = <0x300>; 104 reg = <0x400>; 122 reg = <0x500>; 140 reg = <0x600>; 158 reg = <0x700>; [all …]
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D | mt8192.dtsi | 36 #clock-cells = <0>; 45 #clock-cells = <0>; 52 #clock-cells = <0>; 59 #size-cells = <0>; 61 cpu0: cpu@0 { 64 reg = <0x000>; 75 performance-domains = <&performance 0>; 83 reg = <0x100>; 94 performance-domains = <&performance 0>; 102 reg = <0x200>; [all …]
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D | mt8183.dtsi | 293 #size-cells = <0>; 327 cpu0: cpu@0 { 330 reg = <0x000>; 353 reg = <0x001>; 376 reg = <0x002>; 399 reg = <0x003>; 422 reg = <0x100>; 445 reg = <0x101>; 468 reg = <0x102>; 491 reg = <0x103>; [all …]
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D | mt8186.dtsi | 329 #size-cells = <0>; 367 cpu0: cpu@0 { 370 reg = <0x000>; 394 reg = <0x100>; 418 reg = <0x200>; 442 reg = <0x300>; 466 reg = <0x400>; 490 reg = <0x500>; 514 reg = <0x600>; 538 reg = <0x700>; [all …]
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/linux-6.12.1/arch/arm64/boot/dts/sprd/ |
D | sc9860.dtsi | 16 #size-cells = <0>; 53 reg = <0x0 0x530000>; 61 reg = <0x0 0x530001>; 69 reg = <0x0 0x530002>; 77 reg = <0x0 0x530003>; 85 reg = <0x0 0x530100>; 93 reg = <0x0 0x530101>; 101 reg = <0x0 0x530102>; 109 reg = <0x0 0x530103>; 124 arm,psci-suspend-param = <0x00010002>; [all …]
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