Searched +full:0 +full:x10230000 (Results 1 – 6 of 6) sorted by relevance
67 reg = <0x10230000 0x10000>;
17 #define RTL8712_IOBASE_TXPKT 0x10200000 /*IOBASE_TXPKT*/18 #define RTL8712_IOBASE_RXPKT 0x10210000 /*IOBASE_RXPKT*/19 #define RTL8712_IOBASE_RXCMD 0x10220000 /*IOBASE_RXCMD*/20 #define RTL8712_IOBASE_TXSTATUS 0x10230000 /*IOBASE_TXSTATUS*/21 #define RTL8712_IOBASE_RXSTATUS 0x10240000 /*IOBASE_RXSTATUS*/22 #define RTL8712_IOBASE_IOREG 0x10250000 /*IOBASE_IOREG ADDR*/23 #define RTL8712_IOBASE_SCHEDULER 0x10260000 /*IOBASE_SCHEDULE*/25 #define RTL8712_IOBASE_TRXDMA 0x10270000 /*IOBASE_TRXDMA*/26 #define RTL8712_IOBASE_TXLLT 0x10280000 /*IOBASE_TXLLT*/27 #define RTL8712_IOBASE_WMAC 0x10290000 /*IOBASE_WMAC*/[all …]
29 #size-cells = <0>;34 reg = <0xf00>;43 cpu_opp_table: opp-table-0 {85 #clock-cells = <0>;90 reg = <0x10080000 0x2000>;93 ranges = <0 0x10080000 0x2000>;98 reg = <0x10210000 0x100>;107 pinctrl-0 = <&uart2m0_xfer>;113 reg = <0x10220000 0x100>;122 pinctrl-0 = <&uart1_xfer>;[all …]
20 #size-cells = <0>;22 S7_0: cpu@0 {24 reg = <0>;200 cpu_opp: opp-table-0 {260 #clock-cells = <0>;265 #clock-cells = <0>;271 #clock-cells = <0>;277 #clock-cells = <0>;283 #clock-cells = <0>;289 #clock-cells = <0>;[all …]
146 0x80000000 | 0xf0000000 | UART0147 0x80004000 | 0xf0004000 | UART1148 0x80008000 | 0xf0008000 | UART2149 0x8000c000 | 0xf000c000 | UART3150 0x80010000 | 0xf0010000 | UART4151 0x80014000 | 0xf0014000 | UART5152 0x80018000 | 0xf0018000 | UART6153 0x8001c000 | 0xf001c000 | UART7154 0x80020000 | 0xf0020000 | UART8155 0x80024000 | 0xf0024000 | UART9[all …]
47 #size-cells = <0>;81 cpu0: cpu@0 {84 reg = <0x0>;91 reg = <0x100>;98 reg = <0x200>;105 reg = <0x300>;112 reg = <0x10000>;119 reg = <0x10100>;126 reg = <0x10200>;133 reg = <0x10300>;[all …]