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/linux-6.12.1/drivers/accel/habanalabs/include/gaudi2/asic_reg/
Dpsoc_reset_conf_masks.h24 #define PSOC_RESET_CONF_PSOC_PRSTN_RST_CFG_EN_SHIFT 0
25 #define PSOC_RESET_CONF_PSOC_PRSTN_RST_CFG_EN_MASK 0x1
28 #define PSOC_RESET_CONF_PSOC_SOFT_RST_CFG_EN_SHIFT 0
29 #define PSOC_RESET_CONF_PSOC_SOFT_RST_CFG_EN_MASK 0x1
32 #define PSOC_RESET_CONF_PSOC_FW_RST_CFG_EN_SHIFT 0
33 #define PSOC_RESET_CONF_PSOC_FW_RST_CFG_EN_MASK 0x1
36 #define PSOC_RESET_CONF_PSOC_WD_RST_CFG_EN_SHIFT 0
37 #define PSOC_RESET_CONF_PSOC_WD_RST_CFG_EN_MASK 0x1
40 #define PSOC_RESET_CONF_PSOC_MNL_RST_CFG_EN_SHIFT 0
41 #define PSOC_RESET_CONF_PSOC_MNL_RST_CFG_EN_MASK 0x1
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/crypto/
Dhisilicon,hip07-sec.txt9 Region 0 has registers to control the backend processing engines.
16 Interrupt 0 is for the SEC unit error queue.
29 reg = <0x400 0xd0000000 0x0 0x10000
30 0x400 0xd2000000 0x0 0x10000
31 0x400 0xd2010000 0x0 0x10000
32 0x400 0xd2020000 0x0 0x10000
33 0x400 0xd2030000 0x0 0x10000
34 0x400 0xd2040000 0x0 0x10000
35 0x400 0xd2050000 0x0 0x10000
36 0x400 0xd2060000 0x0 0x10000
[all …]
/linux-6.12.1/drivers/accel/habanalabs/include/gaudi2/
Dgaudi2_special_blocks.h16 { GAUDI2_BLOCK_TYPE_TPC, 0xfc008000, 4, 6, 0, 0x200000, 0x10000, 0x0 }, \
17 { GAUDI2_BLOCK_TYPE_TPC, 0xfc00a000, 4, 6, 0, 0x200000, 0x10000, 0x0 }, \
18 { GAUDI2_BLOCK_TYPE_TPC, 0xfc00b000, 4, 6, 0, 0x200000, 0x10000, 0x0 }, \
19 { GAUDI2_BLOCK_TYPE_TPC, 0xfc00c000, 4, 6, 0, 0x200000, 0x10000, 0x0 }, \
20 { GAUDI2_BLOCK_TYPE_HMMU, 0xfc080000, 4, 4, 0, 0x200000, 0x10000, 0x0 }, \
21 { GAUDI2_BLOCK_TYPE_HMMU, 0xfc081000, 4, 4, 0, 0x200000, 0x10000, 0x0 }, \
22 { GAUDI2_BLOCK_TYPE_HMMU, 0xfc083000, 4, 4, 0, 0x200000, 0x10000, 0x0 }, \
23 { GAUDI2_BLOCK_TYPE_HMMU, 0xfc084000, 4, 4, 0, 0x200000, 0x10000, 0x0 }, \
24 { GAUDI2_BLOCK_TYPE_MME, 0xfc0c8000, 4, 0, 0, 0x200000, 0x0, 0x0 }, \
25 { GAUDI2_BLOCK_TYPE_MME, 0xfc0c9000, 4, 0, 0, 0x200000, 0x0, 0x0 }, \
[all …]
/linux-6.12.1/drivers/of/unittest-data/
Dtests-address.dtsi17 ranges = <0x70000000 0x70000000 0x50000000>,
18 <0x00000000 0xd0000000 0x20000000>;
19 dma-ranges = <0x0 0x20000000 0x40000000>;
22 reg = <0x70000000 0x1000>;
28 ranges = <0x0 0x0 0x80000000 0x0 0x100000>;
29 dma-ranges = <0x1 0x0 0x0 0x20 0x0>;
32 reg = <0x0 0x1000 0x0 0x1000>;
40 reg = <0x90000000 0x1000>;
41 ranges = <0x42000000 0x0 0x40000000 0x40000000 0x0 0x10000000>;
42 dma-ranges = <0x42000000 0x0 0x80000000 0x00000000 0x0 0x10000000>,
[all …]
/linux-6.12.1/arch/arm64/boot/dts/freescale/
Dimx8-ss-lsio.dtsi12 #clock-cells = <0>;
21 ranges = <0x5d000000 0x0 0x5d000000 0x1000000>,
22 <0x08000000 0x0 0x08000000 0x10000000>;
26 reg = <0x5d000000 0x10000>;
39 reg = <0x5d010000 0x10000>;
52 reg = <0x5d020000 0x10000>;
65 reg = <0x5d030000 0x10000>;
77 reg = <0x5d080000 0x10000>;
87 reg = <0x5d090000 0x10000>;
97 reg = <0x5d0a0000 0x10000>;
[all …]
Dfsl-ls1028a.dtsi23 #size-cells = <0>;
25 cpu0: cpu@0 {
28 reg = <0x0>;
30 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
31 i-cache-size = <0xc000>;
34 d-cache-size = <0x8000>;
45 reg = <0x1>;
47 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
48 i-cache-size = <0xc000>;
51 d-cache-size = <0x8000>;
[all …]
Dimx8mn.dtsi46 #size-cells = <0>;
53 arm,psci-suspend-param = <0x0010033>;
61 A53_0: cpu@0 {
64 reg = <0x0>;
68 i-cache-size = <0x8000>;
71 d-cache-size = <0x8000>;
85 reg = <0x1>;
89 i-cache-size = <0x8000>;
92 d-cache-size = <0x8000>;
104 reg = <0x2>;
[all …]
Dfsl-ls1012a.dtsi32 #size-cells = <0>;
34 cpu0: cpu@0 {
37 reg = <0x0>;
38 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
54 arm,psci-suspend-param = <0x0>;
63 #clock-cells = <0>;
70 #clock-cells = <0>;
92 reg = <0x0 0x1401000 0 0x1000>, /* GICD */
93 <0x0 0x1402000 0 0x2000>, /* GICC */
94 <0x0 0x1404000 0 0x2000>, /* GICH */
[all …]
Dimx8-ss-audio.dtsi14 #clock-cells = <0>;
21 #clock-cells = <0>;
22 clock-frequency = <0>;
28 #clock-cells = <0>;
29 clock-frequency = <0>;
35 #clock-cells = <0>;
36 clock-frequency = <0>;
42 #clock-cells = <0>;
43 clock-frequency = <0>;
49 #clock-cells = <0>;
[all …]
Dimx8-ss-dma.dtsi13 #clock-cells = <0>;
22 ranges = <0x5a000000 0x0 0x5a000000 0x1000000>;
26 reg = <0x5a000000 0x10000>;
28 #size-cells = <0>;
37 dmas = <&edma2 1 0 0>, <&edma2 0 0 FSL_EDMA_RX>;
44 reg = <0x5a010000 0x10000>;
46 #size-cells = <0>;
55 dmas = <&edma2 3 0 0>, <&edma2 2 0 FSL_EDMA_RX>;
62 reg = <0x5a020000 0x10000>;
64 #size-cells = <0>;
[all …]
Dfsl-ls1046a.dtsi38 #size-cells = <0>;
40 cpu0: cpu@0 {
43 reg = <0x0>;
44 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
53 reg = <0x1>;
54 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
63 reg = <0x2>;
64 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
73 reg = <0x3>;
74 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
[all …]
Dimx8ulp.dtsi35 #size-cells = <0>;
37 A35_0: cpu@0 {
40 reg = <0x0 0x0>;
49 reg = <0x0 0x1>;
66 arm,psci-suspend-param = <0x0>;
77 reg = <0x0 0x2d400000 0 0x10000>, /* GIC Dist */
78 <0x0 0x2d440000 0 0xc0000>; /* GICR (RD_base + SGI_base) */
101 thermal-sensors = <&scmi_sensor 0>;
131 #clock-cells = <0>;
138 #clock-cells = <0>;
[all …]
Dimx93.dtsi49 #size-cells = <0>;
56 arm,psci-suspend-param = <0x0010033>;
65 A55_0: cpu@0 {
68 reg = <0x0>;
84 reg = <0x100>;
129 #clock-cells = <0>;
136 #clock-cells = <0>;
143 #clock-cells = <0>;
171 reg = <0 0x48000000 0 0x10000>,
172 <0 0x48040000 0 0xc0000>;
[all …]
Dimx8-ss-conn.dtsi12 #clock-cells = <0>;
19 #clock-cells = <0>;
26 #clock-cells = <0>;
33 #clock-cells = <0>;
42 ranges = <0x5b000000 0x0 0x5b000000 0x1000000>;
46 reg = <0x5b0d0000 0x200>;
50 fsl,usbmisc = <&usbmisc1 0>;
52 ahb-burst-config = <0x0>;
53 tx-burst-size-dword = <0x10>;
54 rx-burst-size-dword = <0x10>;
[all …]
Dfsl-ls1043a.dtsi37 #size-cells = <0>;
45 cpu0: cpu@0 {
48 reg = <0x0>;
49 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
58 reg = <0x1>;
59 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
68 reg = <0x2>;
69 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
78 reg = <0x3>;
79 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
[all …]
Dimx8mm.dtsi46 #size-cells = <0>;
53 arm,psci-suspend-param = <0x0010033>;
61 A53_0: cpu@0 {
64 reg = <0x0>;
68 i-cache-size = <0x8000>;
71 d-cache-size = <0x8000>;
85 reg = <0x1>;
89 i-cache-size = <0x8000>;
92 d-cache-size = <0x8000>;
104 reg = <0x2>;
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/display/ti/
Dti,j721e-dss.yaml27 - description: common_s0 DSS Shared common 0
91 - description: common_s0 DSS Shared common 0
113 port@0:
159 reg = <0x04a00000 0x10000>, /* common_m */
160 <0x04a10000 0x10000>, /* common_s0*/
161 <0x04b00000 0x10000>, /* common_s1*/
162 <0x04b10000 0x10000>, /* common_s2*/
163 <0x04a20000 0x10000>, /* vidl1 */
164 <0x04a30000 0x10000>, /* vidl2 */
165 <0x04a50000 0x10000>, /* vid1 */
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/net/
Dmscc,vsc7514-switch.yaml132 reg = <0x1010000 0x10000>,
133 <0x1030000 0x10000>,
134 <0x1080000 0x100>,
135 <0x10e0000 0x10000>,
136 <0x11e0000 0x100>,
137 <0x11f0000 0x100>,
138 <0x1200000 0x100>,
139 <0x1210000 0x100>,
140 <0x1220000 0x100>,
141 <0x1230000 0x100>,
[all …]
/linux-6.12.1/arch/arm/boot/dts/nxp/imx/
Dimx7s.dtsi56 #size-cells = <0>;
63 arm,psci-suspend-param = <0x0010000>;
71 cpu0: cpu@0 {
74 reg = <0>;
94 opp-supported-hw = <0xf>, <0xf>;
100 #clock-cells = <0>;
107 #clock-cells = <0>;
116 #phy-cells = <0>;
124 #phy-cells = <0>;
143 #size-cells = <0>;
[all …]
/linux-6.12.1/drivers/mtd/chips/
Djedec_probe.c27 #define AM29DL800BB 0x22CB
28 #define AM29DL800BT 0x224A
30 #define AM29F800BB 0x2258
31 #define AM29F800BT 0x22D6
32 #define AM29LV400BB 0x22BA
33 #define AM29LV400BT 0x22B9
34 #define AM29LV800BB 0x225B
35 #define AM29LV800BT 0x22DA
36 #define AM29LV160DT 0x22C4
37 #define AM29LV160DB 0x2249
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/remoteproc/
Dxlnx,zynqmp-r5fss.yaml39 enum: [0, 1, 2]
44 clock-for-clock) or Single CPU mode (RPU core 0 is held in reset while
47 If set to 1 then lockstep mode and if 0 then split mode.
50 0: split mode
56 enum: [0, 1]
59 0: split mode
63 "^r(.*)@[0-9a-f]+$":
162 "^r52f@[0-9a-f]+$":
206 "^r5f@[0-9a-f]+$":
241 enum: [0]
[all …]
/linux-6.12.1/arch/arm/boot/dts/nxp/ls/
Dls1021a.dtsi31 #size-cells = <0>;
36 reg = <0xf00>;
37 clocks = <&clockgen 1 0>;
44 reg = <0xf01>;
45 clocks = <&clockgen 1 0>;
50 memory@0 {
52 reg = <0x0 0x0 0x0 0x0>;
57 #clock-cells = <0>;
80 offset = <0xb0>;
81 mask = <0x02>;
[all …]
/linux-6.12.1/arch/arm64/boot/dts/hisilicon/
Dhip07.dtsi23 #size-cells = <0>;
270 reg = <0x10000>;
273 numa-node-id = <0>;
279 reg = <0x10001>;
282 numa-node-id = <0>;
288 reg = <0x10002>;
291 numa-node-id = <0>;
297 reg = <0x10003>;
300 numa-node-id = <0>;
306 reg = <0x10100>;
[all …]
/linux-6.12.1/arch/riscv/boot/dts/starfive/
Djh7110.dtsi20 #size-cells = <0>;
22 S7_0: cpu@0 {
24 reg = <0>;
200 cpu_opp: opp-table-0 {
260 #clock-cells = <0>;
265 #clock-cells = <0>;
271 #clock-cells = <0>;
277 #clock-cells = <0>;
283 #clock-cells = <0>;
289 #clock-cells = <0>;
[all …]
Djh7100.dtsi18 #size-cells = <0>;
20 U74_0: cpu@0 {
22 reg = <0>;
118 #clock-cells = <0>;
121 clock-frequency = <0>;
126 #clock-cells = <0>;
129 clock-frequency = <0>;
134 #clock-cells = <0>;
137 clock-frequency = <0>;
142 #clock-cells = <0>;
[all …]

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