Searched +full:0 +full:x0aaf0000 (Results 1 – 6 of 6) sorted by relevance
71 reg = <0x0aaf0000 0x10000>;
17 #define VID_CTL 0x0018 #define VID_ALP 0x0419 #define VID_CLF 0x0820 #define VID_VPO 0x0C21 #define VID_VPS 0x1022 #define VID_KEY1 0x2823 #define VID_KEY2 0x2C24 #define VID_MPR0 0x3025 #define VID_MPR1 0x3426 #define VID_MPR2 0x38[all …]
38 #clock-cells = <0>;43 #clock-cells = <0>;47 #clock-cells = <0>;55 #clock-cells = <0>;65 #size-cells = <0>;67 CPU0: cpu@0 {70 reg = <0 0>;71 clocks = <&cpufreq_hw 0>;76 qcom,freq-domain = <&cpufreq_hw 0>;96 reg = <0 0x100>;[all …]
39 #clock-cells = <0>;45 #clock-cells = <0>;52 #size-cells = <0>;54 CPU0: cpu@0 {57 reg = <0x0 0x0>;62 qcom,freq-domain = <&cpufreq_hw 0>;64 clocks = <&cpufreq_hw 0>;81 reg = <0x0 0x100>;86 qcom,freq-domain = <&cpufreq_hw 0>;88 clocks = <&cpufreq_hw 0>;[all …]
40 #clock-cells = <0>;45 #clock-cells = <0>;50 #clock-cells = <0>;59 #clock-cells = <0>;69 #size-cells = <0>;71 CPU0: cpu@0 {74 reg = <0 0>;76 clocks = <&cpufreq_hw 0>;86 qcom,freq-domain = <&cpufreq_hw 0>;107 reg = <0 0x100>;[all …]
81 #clock-cells = <0>;87 #clock-cells = <0>;98 reg = <0x0 0x004cd000 0x0 0x1000>;102 reg = <0x0 0x80000000 0x0 0x600000>;107 reg = <0x0 0x80600000 0x0 0x200000>;112 reg = <0x0 0x80800000 0x0 0x60000>;117 reg = <0x0 0x80860000 0x0 0x20000>;123 reg = <0x0 0x80884000 0x0 0x10000>;128 reg = <0x0 0x808ff000 0x0 0x1000>;133 reg = <0x0 0x80900000 0x0 0x200000>;[all …]