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/linux-6.12.1/Documentation/devicetree/bindings/pinctrl/
Dqcom,sm8550-lpass-lpi-pinctrl.yaml64 pattern: "^gpio([0-9]|1[0-9]|2[0-2])$"
96 reg = <0x06e80000 0x20000>,
97 <0x0725a000 0x10000>;
105 gpio-ranges = <&lpass_tlmm 0 0 23>;
Dqcom,sm8650-lpass-lpi-pinctrl.yaml59 pattern: "^gpio([0-9]|1[0-9]|2[0-2])$"
91 reg = <0x06e80000 0x20000>;
99 gpio-ranges = <&lpass_tlmm 0 0 23>;
/linux-6.12.1/arch/arm64/boot/dts/qcom/
Dmsm8994-msft-lumia-octagon.dtsi52 #clock-cells = <0>;
58 pinctrl-0 = <&divclk4_pin_a>;
98 pinctrl-0 = <&hall_front_default &hall_back_default>;
129 reg = <0 0x00200000 0 0x100000>;
134 reg = <0 0x00300000 0 0x80000>;
139 reg = <0 0x00380000 0 0x1000>;
144 reg = <0 0x00381000 0 0x4000>;
149 reg = <0 0x00385000 0 0x1000>;
154 reg = <0 0x00386000 0 0x3000>;
159 reg = <0 0x00389000 0 0x1000>;
[all …]
Dsm8550.dtsi38 #clock-cells = <0>;
43 #clock-cells = <0>;
47 #clock-cells = <0>;
55 #clock-cells = <0>;
65 #size-cells = <0>;
67 CPU0: cpu@0 {
70 reg = <0 0>;
71 clocks = <&cpufreq_hw 0>;
76 qcom,freq-domain = <&cpufreq_hw 0>;
96 reg = <0 0x100>;
[all …]
Dsm8650.dtsi40 #clock-cells = <0>;
45 #clock-cells = <0>;
50 #clock-cells = <0>;
59 #clock-cells = <0>;
69 #size-cells = <0>;
71 CPU0: cpu@0 {
74 reg = <0 0>;
76 clocks = <&cpufreq_hw 0>;
86 qcom,freq-domain = <&cpufreq_hw 0>;
107 reg = <0 0x100>;
[all …]
Dx1e80100.dtsi36 #clock-cells = <0>;
42 #clock-cells = <0>;
47 #clock-cells = <0>;
56 #clock-cells = <0>;
66 #size-cells = <0>;
68 CPU0: cpu@0 {
71 reg = <0x0 0x0>;
88 reg = <0x0 0x100>;
99 reg = <0x0 0x200>;
110 reg = <0x0 0x300>;
[all …]