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/linux-6.12.1/arch/arm64/boot/dts/freescale/
Dimx8dxl-evk.dts31 mboxes = <&lsio_mu5 0 1 &lsio_mu5 1 1 &lsio_mu5 3 1>;
36 fsl,entry-address = <0x34fe0000>;
42 reg = <0x00000000 0x80000000 0 0x40000000>;
54 * reg = <0 0x96000000 0 0x2000000>;
63 size = <0 0x14000000>;
64 alloc-ranges = <0 0x98000000 0 0x14000000>;
69 reg = <0 0x90000000 0 0x8000>;
74 reg = <0 0x90008000 0 0x8000>;
79 reg = <0 0x90010000 0 0x8000>;
84 reg = <0 0x90018000 0 0x8000>;
[all …]
Dimx8qxp-mek.dts21 reg = <0x00000000 0x80000000 0 0x40000000>;
36 pinctrl-0 = <&pinctrl_typec_mux>;
53 hp-det-gpio = <&lsio_gpio1 0 GPIO_ACTIVE_HIGH>;
76 pinctrl-0 = <&pinctrl_fec1>;
84 #size-cells = <0>;
86 ethphy0: ethernet-phy@0 {
88 reg = <0>;
95 #size-cells = <0>;
98 pinctrl-0 = <&pinctrl_lpi2c1 &pinctrl_ioexp_rst>;
104 #size-cells = <0>;
[all …]
Dimx8qm-mek.dts32 reg = <0x00000000 0x80000000 0 0x40000000>;
41 reg = <0 0x90000000 0 0x8000>;
46 reg = <0 0x90008000 0 0x8000>;
51 reg = <0 0x90010000 0 0x8000>;
56 reg = <0 0x90018000 0 0x8000>;
61 reg = <0 0x900ff000 0 0x1000>;
66 reg = <0 0x90100000 0 0x8000>;
71 reg = <0 0x90108000 0 0x8000>;
76 reg = <0 0x90110000 0 0x8000>;
81 reg = <0 0x90118000 0 0x8000>;
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/clock/
Dallwinner,sun9i-a80-ahb-clk.yaml17 const: 0
45 #clock-cells = <0>;
47 reg = <0x06000060 0x4>;