Searched +full:0 +full:x02184400 (Results 1 – 4 of 4) sorted by relevance
103 pins after a J-to-K or K-to-J transition. The range is from 0x0 to104 0x3, the default value is 0x1. Details can refer to TXPREEMPAMPTUNE0107 minimum: 0x0108 maximum: 0x3113 level voltage. The range is from 0x0 to 0xf, the default value is114 0x3. Details can refer to TXVREFTUNE0 bits of USBNC_n_PHY_CFG1.116 minimum: 0x0117 maximum: 0xf124 to design default time. (0:-10%; 1:design default; 2:+15%; 3:+20%)127 minimum: 0[all …]
51 #size-cells = <0>;53 cpu0: cpu@0 {56 reg = <0x0>;86 #clock-cells = <0>;92 #clock-cells = <0>;100 interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;105 #phy-cells = <0>;117 reg = <0x00900000 0x20000>;118 ranges = <0 0x00900000 0x20000>;128 reg = <0x00a01000 0x1000>,[all …]
59 #clock-cells = <0>;65 #clock-cells = <0>;66 clock-frequency = <0>;71 #clock-cells = <0>;78 #size-cells = <0>;83 lvds-channel@0 {85 #size-cells = <0>;86 reg = <0>;89 port@0 {90 reg = <0>;[all …]
61 #size-cells = <0>;63 cpu0: cpu@0 {66 reg = <0>;100 #clock-cells = <0>;107 #clock-cells = <0>;114 #clock-cells = <0>;115 clock-frequency = <0>;121 #clock-cells = <0>;122 clock-frequency = <0>;128 #clock-cells = <0>;[all …]