Searched +full:0 +full:x01c0c000 (Results 1 – 12 of 12) sorted by relevance
19 const: 0122 port@0:134 "^endpoint(@[0-9])$":154 - port@0382 reg = <0x01c0c000 0x1000>;393 #clock-cells = <0>;398 #size-cells = <0>;400 port@0 {402 #size-cells = <0>;403 reg = <0>;[all …]
72 #size-cells = <0>;74 cpu@0 {77 reg = <0>;102 #clock-cells = <0>;110 #clock-cells = <0>;126 reg = <0x01000000 0x10000>;138 reg = <0x01100000 0x100000>;139 clocks = <&display_clocks 0>,143 resets = <&display_clocks 0>;147 #size-cells = <0>;[all …]
56 #size-cells = <0>;58 cpu0: cpu@0 {61 reg = <0x0>;97 #clock-cells = <0>;104 #clock-cells = <0>;119 size = <0x6000000>;120 alloc-ranges = <0x40000000 0x10000000>;135 reg = <0x01c00000 0x30>;140 sram_a: sram@0 {142 reg = <0x00000000 0xc000>;[all …]
91 #size-cells = <0>;93 cpu0: cpu@0 {96 reg = <0>;112 #clock-cells = <0>;120 #clock-cells = <0>;136 reg = <0x01c00000 0x30>;143 reg = <0x01d00000 0x80000>;146 ranges = <0 0x01d00000 0x80000>;148 ve_sram: sram-section@0 {151 reg = <0x000000 0x80000>;[all …]
87 #clock-cells = <0>;95 #clock-cells = <0>;118 reg = <0x01000000 0x10000>;129 compatible = "allwinner,sun8i-h3-de2-mixer-0";130 reg = <0x01100000 0x100000>;139 #size-cells = <0>;153 reg = <0x01c02000 0x1000>;163 reg = <0x01c0c000 0x1000>;172 #size-cells = <0>;174 tcon0_in: port@0 {[all …]
111 #size-cells = <0>;112 cpu0: cpu@0 {115 reg = <0x0>;166 #clock-cells = <0>;173 #clock-cells = <0>;199 size = <0x6000000>;200 alloc-ranges = <0x40000000 0x10000000>;214 reg = <0x01c00000 0x30>;219 sram_a: sram@0 {221 reg = <0x00000000 0xc000>;[all …]
62 #size-cells = <0>;64 cpu0: cpu@0 {71 reg = <0>;115 reg = <0x100>;126 reg = <0x101>;137 reg = <0x102>;148 reg = <0x103>;168 #clock-cells = <0>;181 #clock-cells = <0>;188 #clock-cells = <0>;[all …]
101 #size-cells = <0>;103 cpu0: cpu@0 {106 reg = <0>;213 #clock-cells = <0>;221 #clock-cells = <0>;238 #clock-cells = <0>;245 #clock-cells = <0>;252 #clock-cells = <0>;254 reg = <0x01c200d0 0x4>;274 reg = <0x01c02000 0x1000>;[all …]
101 #size-cells = <0>;103 cpu0: cpu@0 {106 reg = <0>;181 size = <0x6000000>;182 alloc-ranges = <0x40000000 0x10000000>;208 #clock-cells = <0>;215 #clock-cells = <0>;231 #clock-cells = <0>;238 #clock-cells = <0>;245 #clock-cells = <0>;[all …]
47 #size-cells = <0>;49 cpu0: cpu@0 {52 reg = <0>;57 i-cache-size = <0x8000>;60 d-cache-size = <0x8000>;74 i-cache-size = <0x8000>;77 d-cache-size = <0x8000>;91 i-cache-size = <0x8000>;94 d-cache-size = <0x8000>;108 i-cache-size = <0x8000>;[all …]
29 #clock-cells = <0>;35 #clock-cells = <0>;43 #size-cells = <0>;45 CPU0: cpu@0 {48 reg = <0x0 0x0>;52 qcom,freq-domain = <&cpufreq_hw 0>;59 clocks = <&cpufreq_hw 0>;77 reg = <0x0 0x100>;81 qcom,freq-domain = <&cpufreq_hw 0>;88 clocks = <&cpufreq_hw 0>;[all …]
78 #clock-cells = <0>;85 #clock-cells = <0>;92 #size-cells = <0>;94 CPU0: cpu@0 {97 reg = <0x0 0x0>;98 clocks = <&cpufreq_hw 0>;102 qcom,freq-domain = <&cpufreq_hw 0>;126 reg = <0x0 0x100>;127 clocks = <&cpufreq_hw 0>;131 qcom,freq-domain = <&cpufreq_hw 0>;[all …]