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/linux-6.12.1/drivers/gpu/drm/etnaviv/
Dcommon.xml.h7 http://0x04.net/cgit/index.cgi/rules-ng-ng
8 git clone git://0x04.net/rules-ng-ng
43 #define PIPE_ID_PIPE_3D 0x00000000
44 #define PIPE_ID_PIPE_2D 0x00000001
45 #define SYNC_RECIPIENT_FE 0x00000001
46 #define SYNC_RECIPIENT_RA 0x00000005
47 #define SYNC_RECIPIENT_PE 0x00000007
48 #define SYNC_RECIPIENT_DE 0x0000000b
49 #define SYNC_RECIPIENT_BLT 0x00000010
50 #define ENDIAN_MODE_NO_SWAP 0x00000000
[all …]
/linux-6.12.1/drivers/mfd/
Dcs42l43.c42 #define CS42L43_MCU_UPDATE_OFFSET 0x100000
46 #define CS42L43_MCU_ROM_REV 0x2001
47 #define CS42L43_MCU_ROM_BIOS_REV 0x0000
49 #define CS42L43_MCU_SUPPORTED_REV 0x2105
50 #define CS42L43_MCU_SHADOW_REGS_REQUIRED_REV 0x2200
51 #define CS42L43_MCU_SUPPORTED_BIOS_REV 0x0001
75 { 0x4000, 0x00000055 },
76 { 0x4000, 0x000000AA },
77 { 0x10084, 0x00000000 },
78 { 0x1741C, 0x00CD2000 },
[all …]
/linux-6.12.1/arch/sh/kernel/cpu/sh2a/
Dfpu.c21 #define FPSCR_RCHG 0x00000000
32 asm volatile("sts.l fpul, @-%0\n\t" in save_fpu()
33 "sts.l fpscr, @-%0\n\t" in save_fpu()
34 "fmov.s fr15, @-%0\n\t" in save_fpu()
35 "fmov.s fr14, @-%0\n\t" in save_fpu()
36 "fmov.s fr13, @-%0\n\t" in save_fpu()
37 "fmov.s fr12, @-%0\n\t" in save_fpu()
38 "fmov.s fr11, @-%0\n\t" in save_fpu()
39 "fmov.s fr10, @-%0\n\t" in save_fpu()
40 "fmov.s fr9, @-%0\n\t" in save_fpu()
[all …]
/linux-6.12.1/arch/powerpc/boot/dts/
Duc101.dts75 phy0: ethernet-phy@0 {
77 reg = <0>;
91 reg = <0x2c>;
95 reg = <0x51>;
105 ranges = <0 0 0xff800000 0x00800000
106 1 0 0x80000000 0x00800000
107 3 0 0x80000000 0x00800000>;
109 flash@0,0 {
111 reg = <0 0 0x00800000>;
117 partition@0 {
[all …]
Dmucmc52.dts78 phy0: ethernet-phy@0 {
80 reg = <0>;
91 reg = <0x2c>;
95 reg = <0x51>;
101 interrupt-map-mask = <0xf800 0 0 7>;
103 /* IDSEL 0x10 */
104 0x8000 0 0 1 &mpc5200_pic 0 3 3
105 0x8000 0 0 2 &mpc5200_pic 0 3 3
106 0x8000 0 0 3 &mpc5200_pic 0 2 3
107 0x8000 0 0 4 &mpc5200_pic 0 1 3
[all …]
Dmpc8315erdb.dts27 #size-cells = <0>;
29 PowerPC,8315@0 {
31 reg = <0x0>;
36 timebase-frequency = <0>; // from bootloader
37 bus-frequency = <0>; // from bootloader
38 clock-frequency = <0>; // from bootloader
44 reg = <0x00000000 0x08000000>; // 128MB at 0
51 reg = <0xe0005000 0x1000>;
52 interrupts = <77 0x8>;
58 ranges = <0x0 0x0 0xfe000000 0x00800000
[all …]
Dmpc8377_rdb.dts27 #size-cells = <0>;
29 PowerPC,8377@0 {
31 reg = <0x0>;
36 timebase-frequency = <0>;
37 bus-frequency = <0>;
38 clock-frequency = <0>;
44 reg = <0x00000000 0x10000000>; // 256MB at 0
51 reg = <0xe0005000 0x1000>;
52 interrupts = <77 0x8>;
58 ranges = <0x0 0x0 0xfe000000 0x00800000
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/bus/
Dqcom,ebi2.yaml31 CS0 GPIO134 0x1a800000-0x1b000000 (8MB)
32 CS1 GPIO39 (A) / GPIO123 (B) 0x1b000000-0x1b800000 (8MB)
33 CS2 GPIO40 (A) / GPIO124 (B) 0x1b800000-0x1c000000 (8MB)
34 CS3 GPIO133 0x1d000000-0x25000000 (128 MB)
35 CS4 GPIO132 0x1c800000-0x1d000000 (8MB)
36 CS5 GPIO131 0x1c000000-0x1c800000 (8MB)
105 "^.*@[0-5],[0-9a-f]+$":
120 actually 1, so a value of 0 will still yield 1 recovery cycle.
121 minimum: 0
129 asserted. With a hold of 1 (value = 0), the CS stays active
[all …]
/linux-6.12.1/arch/arm64/boot/dts/ti/
Dk3-j721e.dtsi25 #size-cells = <0>;
39 cpu0: cpu@0 {
41 reg = <0x000>;
44 i-cache-size = <0xC000>;
47 d-cache-size = <0x8000>;
55 reg = <0x001>;
58 i-cache-size = <0xC000>;
61 d-cache-size = <0x8000>;
72 cache-size = <0x100000>;
114 ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
[all …]
Dk3-j784s4-evm-pcie0-pcie1-ep.dtso38 reg = <0x00 0x02900000 0x00 0x1000>,
39 <0x00 0x02907000 0x00 0x400>,
40 <0x00 0x0d000000 0x00 0x00800000>,
41 <0x00 0x10000000 0x00 0x08000000>;
45 ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x0>;
49 clocks = <&k3_clks 332 0>;
52 max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
60 reg = <0x00 0x02910000 0x00 0x1000>,
61 <0x00 0x02917000 0x00 0x400>,
62 <0x00 0x0d800000 0x00 0x00800000>,
[all …]
/linux-6.12.1/arch/powerpc/include/uapi/asm/
Dcputable.h6 #define PPC_FEATURE_32 0x80000000
7 #define PPC_FEATURE_64 0x40000000
8 #define PPC_FEATURE_601_INSTR 0x20000000
9 #define PPC_FEATURE_HAS_ALTIVEC 0x10000000
10 #define PPC_FEATURE_HAS_FPU 0x08000000
11 #define PPC_FEATURE_HAS_MMU 0x04000000
12 #define PPC_FEATURE_HAS_4xxMAC 0x02000000
13 #define PPC_FEATURE_UNIFIED_CACHE 0x01000000
14 #define PPC_FEATURE_HAS_SPE 0x00800000
15 #define PPC_FEATURE_HAS_EFP_SINGLE 0x00400000
[all …]
/linux-6.12.1/arch/sh/kernel/cpu/sh4/
Dfpu.c22 #define FPSCR_RCHG 0x00000000
46 asm volatile ("sts.l fpul, @-%0\n\t" in save_fpu()
47 "sts.l fpscr, @-%0\n\t" in save_fpu()
50 "fmov.s fr15, @-%0\n\t" in save_fpu()
51 "fmov.s fr14, @-%0\n\t" in save_fpu()
52 "fmov.s fr13, @-%0\n\t" in save_fpu()
53 "fmov.s fr12, @-%0\n\t" in save_fpu()
54 "fmov.s fr11, @-%0\n\t" in save_fpu()
55 "fmov.s fr10, @-%0\n\t" in save_fpu()
56 "fmov.s fr9, @-%0\n\t" in save_fpu()
[all …]
/linux-6.12.1/arch/arm/
DKconfig-nommu15 default 0x00800000
19 default 0x00800000
24 default 0x00400000
29 default 0x00400000
33 default 0x00007700
44 placed at address 0x00000000. However, this region may be
/linux-6.12.1/sound/drivers/vx/
Dvx_cmd.h86 #define CODE_OP_PIPE_TIME 0x004e0000
87 #define CODE_OP_START_STREAM 0x00800000
88 #define CODE_OP_PAUSE_STREAM 0x00810000
89 #define CODE_OP_OUT_STREAM_LEVEL 0x00820000
90 #define CODE_OP_UPDATE_R_BUFFERS 0x00840000
91 #define CODE_OP_OUT_STREAM1_LEVEL_CURVE 0x00850000
92 #define CODE_OP_OUT_STREAM2_LEVEL_CURVE 0x00930000
93 #define CODE_OP_OUT_STREAM_FORMAT 0x00860000
94 #define CODE_OP_STREAM_TIME 0x008f0000
95 #define CODE_OP_OUT_STREAM_EXTRAPARAMETER 0x00910000
[all …]
/linux-6.12.1/drivers/net/wireless/ath/ath9k/
Dar9340_initvals.h37 {0x000160ac, 0xa4646800, 0xa4646800, 0xa4646800, 0xa4646800},
38 {0x0001610c, 0x08000000, 0x00000000, 0x00000000, 0x00000000},
39 {0x00016140, 0x10804000, 0x10804000, 0x50804000, 0x50804000},
40 {0x0001650c, 0x08000000, 0x00000000, 0x00000000, 0x00000000},
41 {0x00016540, 0x10804000, 0x10804000, 0x50804000, 0x50804000},
46 {0x0000a410, 0x000050d9, 0x000050d9, 0x000050d9, 0x000050d9},
47 {0x0000a500, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
48 {0x0000a504, 0x06000003, 0x06000003, 0x04000002, 0x04000002},
49 {0x0000a508, 0x0a000020, 0x0a000020, 0x08000004, 0x08000004},
50 {0x0000a50c, 0x10000023, 0x10000023, 0x0b000200, 0x0b000200},
[all …]
/linux-6.12.1/arch/mips/include/asm/txx9/
Dtx4938.h19 #define TX4938_REG_BASE 0xffffffffff1f0000UL /* == TX4937_REG_BASE */
21 #define TX4938_REG_BASE 0xff1f0000UL /* == TX4937_REG_BASE */
23 #define TX4938_REG_SIZE 0x00010000 /* == TX4937_REG_SIZE */
26 #define TX4938_NDFMC_REG (TX4938_REG_BASE + 0x5000)
27 #define TX4938_SRAMC_REG (TX4938_REG_BASE + 0x6000)
28 #define TX4938_PCIC1_REG (TX4938_REG_BASE + 0x7000)
29 #define TX4938_SDRAMC_REG (TX4938_REG_BASE + 0x8000)
30 #define TX4938_EBUSC_REG (TX4938_REG_BASE + 0x9000)
31 #define TX4938_DMA_REG(ch) (TX4938_REG_BASE + 0xb000 + (ch) * 0x800)
32 #define TX4938_PCIC_REG (TX4938_REG_BASE + 0xd000)
[all …]
/linux-6.12.1/include/soc/fsl/qe/
Ducc_slow.h22 #define T_R 0x80000000 /* ready bit */
23 #define T_PAD 0x40000000 /* add pads to short frames */
24 #define T_W 0x20000000 /* wrap bit */
25 #define T_I 0x10000000 /* interrupt on completion */
26 #define T_L 0x08000000 /* last */
28 #define T_A 0x04000000 /* Address - the data transmitted as address
30 #define T_TC 0x04000000 /* transmit CRC */
31 #define T_CM 0x02000000 /* continuous mode */
32 #define T_DEF 0x02000000 /* collision on previous attempt to transmit */
33 #define T_P 0x01000000 /* Preamble - send Preamble sequence before
[all …]
/linux-6.12.1/drivers/net/wireless/ath/ath5k/
Ddesc.h25 * @rx_control_0: RX control word 0
34 #define AR5K_DESC_RX_CTL1_BUF_LEN 0x00000fff /* data buffer length */
35 #define AR5K_DESC_RX_CTL1_INTREQ 0x00002000 /* RX interrupt request */
39 * @rx_status_0: RX status word 0
50 /* RX status word 0 fields/flags */
51 #define AR5K_5210_RX_DESC_STATUS0_DATA_LEN 0x00000fff /* RX data length */
52 #define AR5K_5210_RX_DESC_STATUS0_MORE 0x00001000 /* more desc for this frame */
53 #define AR5K_5210_RX_DESC_STATUS0_RECEIVE_ANT_5210 0x00004000 /* [5210] receive on ant 1 */
54 #define AR5K_5210_RX_DESC_STATUS0_RECEIVE_RATE 0x00078000 /* reception rate */
56 #define AR5K_5210_RX_DESC_STATUS0_RECEIVE_SIGNAL 0x07f80000 /* rssi */
[all …]
/linux-6.12.1/arch/sh/drivers/pci/
Dpci-sh7751.h13 #define SH7751_VENDOR_ID 0x1054
14 #define SH7751_DEVICE_ID 0x3505
15 #define SH7751R_DEVICE_ID 0x350e
18 #define SH7751_PCI_CONFIG_BASE 0xFD000000 /* Config space base addr */
19 #define SH7751_PCI_CONFIG_SIZE 0x1000000 /* Config space size */
20 #define SH7751_PCI_MEMORY_BASE 0xFD000000 /* Memory space base addr */
21 #define SH7751_PCI_MEM_SIZE 0x01000000 /* Size of Memory window */
22 #define SH7751_PCI_IO_BASE 0xFE240000 /* IO space base address */
23 #define SH7751_PCI_IO_SIZE 0x40000 /* Size of IO window */
25 #define SH7751_PCIREG_BASE 0xFE200000 /* PCI regs base address */
[all …]
/linux-6.12.1/arch/powerpc/include/asm/
Dreg_booke.h23 #define MSR_CM_LG 31 /* Computation Mode (0=32-bit, 1=64-bit) */
48 #define SPRN_DECAR 0x036 /* Decrementer Auto Reload Register */
49 #define SPRN_IVPR 0x03F /* Interrupt Vector Prefix Register */
50 #define SPRN_USPRG0 0x100 /* User Special Purpose Register General 0 */
51 #define SPRN_SPRG3R 0x103 /* Special Purpose Register General 3 Read */
52 #define SPRN_SPRG4R 0x104 /* Special Purpose Register General 4 Read */
53 #define SPRN_SPRG5R 0x105 /* Special Purpose Register General 5 Read */
54 #define SPRN_SPRG6R 0x106 /* Special Purpose Register General 6 Read */
55 #define SPRN_SPRG7R 0x107 /* Special Purpose Register General 7 Read */
56 #define SPRN_SPRG4W 0x114 /* Special Purpose Register General 4 Write */
[all …]
/linux-6.12.1/arch/arm/boot/bootp/
DMakefile10 add_hex = $(shell printf 0x%x $$(( $(1) + $(2) )) )
19 PARAMS_PHYS := $(call add_hex, $(PHYS_OFFSET), 0x100)
22 initrd_offset-$(CONFIG_ARCH_FOOTBRIDGE) += 0x00800000
23 initrd_offset-$(CONFIG_ARCH_SA1100) += 0x00800000
24 initrd_offset-$(CONFIG_ARCH_RPC) += 0x08000000
/linux-6.12.1/arch/mips/math-emu/
Dsp_sqrt.c34 /* sqrt(0) = 0 */ in ieee754sp_sqrt()
60 if (m == 0) { /* subnormal x */ in ieee754sp_sqrt()
61 for (i = 0; (ix & 0x00800000) == 0; i++) in ieee754sp_sqrt()
66 ix = (ix & 0x007fffff) | 0x00800000; in ieee754sp_sqrt()
73 s = 0; in ieee754sp_sqrt()
74 q = 0; /* q = sqrt(x) */ in ieee754sp_sqrt()
75 r = 0x01000000; /* r = moving bit from right to left */ in ieee754sp_sqrt()
77 while (r != 0) { in ieee754sp_sqrt()
88 if (ix != 0) { in ieee754sp_sqrt()
99 ix = (q >> 1) + 0x3f000000; in ieee754sp_sqrt()
/linux-6.12.1/Documentation/devicetree/bindings/remoteproc/
Dti,k3-dsp-rproc.yaml161 mailbox0_cluster3: mailbox-0 {
173 ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
174 <0x00 0x64800000 0x00 0x64800000 0x00 0x00800000>, /* C71_0 */
175 <0x4d 0x80800000 0x4d 0x80800000 0x00 0x00800000>, /* C66_0 */
176 <0x4d 0x81800000 0x4d 0x81800000 0x00 0x00800000>; /* C66_1 */
181 reg = <0x4d 0x80800000 0x00 0x00048000>,
182 <0x4d 0x80e00000 0x00 0x00008000>,
183 <0x4d 0x80f00000 0x00 0x00008000>;
187 ti,sci-proc-ids = <0x03 0xFF>;
198 reg = <0x00 0x64800000 0x00 0x00080000>,
[all …]
/linux-6.12.1/drivers/net/ethernet/sis/
Dsis900.h19 #define SIS900_TOTAL_SIZE 0x100
23 cr=0x0, //Command Register
24 cfg=0x4, //Configuration Register
25 mear=0x8, //EEPROM Access Register
26 ptscr=0xc, //PCI Test Control Register
27 isr=0x10, //Interrupt Status Register
28 imr=0x14, //Interrupt Mask Register
29 ier=0x18, //Interrupt Enable Register
30 epar=0x18, //Enhanced PHY Access Register
31 txdp=0x20, //Transmit Descriptor Pointer Register
[all …]
/linux-6.12.1/arch/arm/boot/dts/qcom/
Dqcom-msm8660.dtsi18 #size-cells = <0>;
20 cpu@0 {
24 reg = <0>;
45 reg = <0x0 0x0>;
56 #clock-cells = <0>;
63 #clock-cells = <0>;
70 #clock-cells = <0>;
86 reg = < 0x02080000 0x1000 >,
87 < 0x02081000 0x1000 >;
92 interrupts = <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>,
[all …]

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