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/linux-6.12.1/drivers/pinctrl/mediatek/
Dpinctrl-mt6765.c14 * iocfg[0]:0x10005000, iocfg[1]:0x10002C00, iocfg[2]:0x10002800,
15 * iocfg[3]:0x10002A00, iocfg[4]:0x10002000, iocfg[5]:0x10002200,
16 * iocfg[6]:0x10002500, iocfg[7]:0x10002600.
22 _x_bits, 32, 0)
29 PIN_FIELD(0, 202, 0x300, 0x10, 0, 4),
33 PIN_FIELD(0, 202, 0x0, 0x10, 0, 1),
37 PIN_FIELD(0, 202, 0x200, 0x10, 0, 1),
41 PIN_FIELD(0, 202, 0x100, 0x10, 0, 1),
45 PINS_FIELD_BASE(0, 3, 2, 0x00b0, 0x10, 4, 1),
46 PINS_FIELD_BASE(4, 7, 2, 0x00b0, 0x10, 5, 1),
[all …]
Dpinctrl-mt8186.c13 * iocfg[0]:0x10005000, iocfg[1]:0x10002000, iocfg[2]:0x10002200,
14 * iocfg[3]:0x10002400, iocfg[4]:0x10002600, iocfg[5]:0x10002800,
15 * iocfg[6]:0x10002C00.
20 PIN_FIELD_CALC(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits, 32, 0)
26 PIN_FIELD(0, 184, 0x300, 0x10, 0, 4),
30 PIN_FIELD(0, 184, 0x0, 0x10, 0, 1),
34 PIN_FIELD(0, 184, 0x200, 0x10, 0, 1),
38 PIN_FIELD(0, 184, 0x100, 0x10, 0, 1),
42 PIN_FIELD_BASE(0, 0, 6, 0x0030, 0x10, 13, 1),
43 PIN_FIELD_BASE(1, 1, 6, 0x0030, 0x10, 14, 1),
[all …]
Dpinctrl-mt6779.c13 * gpio:0x10005000, iocfg_rm:0x11C20000, iocfg_br:0x11D10000,
14 * iocfg_lm:0x11E20000, iocfg_lb:0x11E70000, iocfg_rt:0x11EA0000,
15 * iocfg_lt:0x11F20000, iocfg_tl:0x11F30000
21 32, 0)
28 PIN_FIELD_BASE(0, 7, 0, 0x0300, 0x10, 0, 4),
29 PIN_FIELD_BASE(8, 15, 0, 0x0310, 0x10, 0, 4),
30 PIN_FIELD_BASE(16, 23, 0, 0x0320, 0x10, 0, 4),
31 PIN_FIELD_BASE(24, 31, 0, 0x0330, 0x10, 0, 4),
32 PIN_FIELD_BASE(32, 39, 0, 0x0340, 0x10, 0, 4),
33 PIN_FIELD_BASE(40, 47, 0, 0x0350, 0x10, 0, 4),
[all …]
Dpinctrl-mt8192.c13 * iocfg0:0x10005000, iocfg_rm:0x11C20000, iocfg_bm:0x11D10000,
14 * iocfg_bl:0x11D30000, iocfg_br:0x11D40000, iocfg_lm:0x11E20000,
15 * iocfg_lb:0x11E70000, iocfg_rt:0x11EA0000, iocfg_lt:0x11F20000,
16 * iocfg_tl:0x11F30000
22 32, 0)
29 PIN_FIELD(0, 228, 0x300, 0x10, 0, 4),
33 PIN_FIELD(0, 228, 0x0, 0x10, 0, 1),
37 PIN_FIELD(0, 228, 0x200, 0x10, 0, 1),
41 PIN_FIELD(0, 228, 0x100, 0x10, 0, 1),
45 PIN_FIELD_BASE(0, 0, 4, 0x00f0, 0x10, 8, 1),
[all …]
/linux-6.12.1/drivers/gpu/drm/radeon/
Dradeon_ucode.h75 #define RV770_SMC_UCODE_START 0x0100
76 #define RV770_SMC_UCODE_SIZE 0x410d
77 #define RV770_SMC_INT_VECTOR_START 0xffc0
78 #define RV770_SMC_INT_VECTOR_SIZE 0x0040
80 #define RV730_SMC_UCODE_START 0x0100
81 #define RV730_SMC_UCODE_SIZE 0x412c
82 #define RV730_SMC_INT_VECTOR_START 0xffc0
83 #define RV730_SMC_INT_VECTOR_SIZE 0x0040
85 #define RV710_SMC_UCODE_START 0x0100
86 #define RV710_SMC_UCODE_SIZE 0x3f1f
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/dma/
Dcirrus,ep9301-dma-m2p.yaml86 0: I2S channel 1
116 reg = <0x80000000 0x0040>,
117 <0x80000040 0x0040>,
118 <0x80000080 0x0040>,
119 <0x800000c0 0x0040>,
120 <0x80000240 0x0040>,
121 <0x80000200 0x0040>,
122 <0x800002c0 0x0040>,
123 <0x80000280 0x0040>,
124 <0x80000340 0x0040>,
[all …]
/linux-6.12.1/drivers/net/ethernet/cirrus/
Dcs89x0.h18 #define PP_ChipID 0x0000 /* offset 0h -> Corp -ID */
22 #define PP_ISAIOB 0x0020 /* IO base address */
23 #define PP_CS8900_ISAINT 0x0022 /* ISA interrupt select */
24 #define PP_CS8920_ISAINT 0x0370 /* ISA interrupt select */
25 #define PP_CS8900_ISADMA 0x0024 /* ISA Rec DMA channel */
26 #define PP_CS8920_ISADMA 0x0374 /* ISA Rec DMA channel */
27 #define PP_ISASOF 0x0026 /* ISA DMA offset */
28 #define PP_DmaFrameCnt 0x0028 /* ISA DMA Frame count */
29 #define PP_DmaByteCnt 0x002A /* ISA DMA Byte count */
30 #define PP_CS8900_ISAMemB 0x002C /* Memory base */
[all …]
/linux-6.12.1/sound/soc/codecs/
Dwm9090.h16 #define WM9090_SOFTWARE_RESET 0x00
17 #define WM9090_POWER_MANAGEMENT_1 0x01
18 #define WM9090_POWER_MANAGEMENT_2 0x02
19 #define WM9090_POWER_MANAGEMENT_3 0x03
20 #define WM9090_CLOCKING_1 0x06
21 #define WM9090_IN1_LINE_CONTROL 0x16
22 #define WM9090_IN2_LINE_CONTROL 0x17
23 #define WM9090_IN1_LINE_INPUT_A_VOLUME 0x18
24 #define WM9090_IN1_LINE_INPUT_B_VOLUME 0x19
25 #define WM9090_IN2_LINE_INPUT_A_VOLUME 0x1A
[all …]
Dwm8985.h13 #define WM8985_SOFTWARE_RESET 0x00
14 #define WM8985_POWER_MANAGEMENT_1 0x01
15 #define WM8985_POWER_MANAGEMENT_2 0x02
16 #define WM8985_POWER_MANAGEMENT_3 0x03
17 #define WM8985_AUDIO_INTERFACE 0x04
18 #define WM8985_COMPANDING_CONTROL 0x05
19 #define WM8985_CLOCK_GEN_CONTROL 0x06
20 #define WM8985_ADDITIONAL_CONTROL 0x07
21 #define WM8985_GPIO_CONTROL 0x08
22 #define WM8985_JACK_DETECT_CONTROL_1 0x09
[all …]
Dwm8990.h16 #define WM8990_RESET 0x00
17 #define WM8990_POWER_MANAGEMENT_1 0x01
18 #define WM8990_POWER_MANAGEMENT_2 0x02
19 #define WM8990_POWER_MANAGEMENT_3 0x03
20 #define WM8990_AUDIO_INTERFACE_1 0x04
21 #define WM8990_AUDIO_INTERFACE_2 0x05
22 #define WM8990_CLOCKING_1 0x06
23 #define WM8990_CLOCKING_2 0x07
24 #define WM8990_AUDIO_INTERFACE_3 0x08
25 #define WM8990_AUDIO_INTERFACE_4 0x09
[all …]
Dwm8991.h16 #define WM8991_RESET 0x00
17 #define WM8991_POWER_MANAGEMENT_1 0x01
18 #define WM8991_POWER_MANAGEMENT_2 0x02
19 #define WM8991_POWER_MANAGEMENT_3 0x03
20 #define WM8991_AUDIO_INTERFACE_1 0x04
21 #define WM8991_AUDIO_INTERFACE_2 0x05
22 #define WM8991_CLOCKING_1 0x06
23 #define WM8991_CLOCKING_2 0x07
24 #define WM8991_AUDIO_INTERFACE_3 0x08
25 #define WM8991_AUDIO_INTERFACE_4 0x09
[all …]
Dwm8993.h15 #define WM8993_SOFTWARE_RESET 0x00
16 #define WM8993_POWER_MANAGEMENT_1 0x01
17 #define WM8993_POWER_MANAGEMENT_2 0x02
18 #define WM8993_POWER_MANAGEMENT_3 0x03
19 #define WM8993_AUDIO_INTERFACE_1 0x04
20 #define WM8993_AUDIO_INTERFACE_2 0x05
21 #define WM8993_CLOCKING_1 0x06
22 #define WM8993_CLOCKING_2 0x07
23 #define WM8993_AUDIO_INTERFACE_3 0x08
24 #define WM8993_AUDIO_INTERFACE_4 0x09
[all …]
Dwm8983.h16 #define WM8983_SOFTWARE_RESET 0x00
17 #define WM8983_POWER_MANAGEMENT_1 0x01
18 #define WM8983_POWER_MANAGEMENT_2 0x02
19 #define WM8983_POWER_MANAGEMENT_3 0x03
20 #define WM8983_AUDIO_INTERFACE 0x04
21 #define WM8983_COMPANDING_CONTROL 0x05
22 #define WM8983_CLOCK_GEN_CONTROL 0x06
23 #define WM8983_ADDITIONAL_CONTROL 0x07
24 #define WM8983_GPIO_CONTROL 0x08
25 #define WM8983_JACK_DETECT_CONTROL_1 0x09
[all …]
Dwm8955.h18 #define WM8955_LOUT1_VOLUME 0x02
19 #define WM8955_ROUT1_VOLUME 0x03
20 #define WM8955_DAC_CONTROL 0x05
21 #define WM8955_AUDIO_INTERFACE 0x07
22 #define WM8955_SAMPLE_RATE 0x08
23 #define WM8955_LEFT_DAC_VOLUME 0x0A
24 #define WM8955_RIGHT_DAC_VOLUME 0x0B
25 #define WM8955_BASS_CONTROL 0x0C
26 #define WM8955_TREBLE_CONTROL 0x0D
27 #define WM8955_RESET 0x0F
[all …]
/linux-6.12.1/arch/arm/boot/dts/cirrus/
Dep93xx.dtsi18 reg = <0x80930000 0x1000>;
101 reg = <0x80900000 0x28>;
110 * windows in the 256MB space from 0x50000000 to 0x5fffffff.
116 reg = <0x80080000 0x20>;
125 reg = <0x80000000 0x0040>,
126 <0x80000040 0x0040>,
127 <0x80000080 0x0040>,
128 <0x800000c0 0x0040>,
129 <0x80000240 0x0040>,
130 <0x80000200 0x0040>,
[all …]
/linux-6.12.1/include/sound/
Dwm8903.h15 #define WM8903_GPIO_CONFIG_ZERO 0x8000
18 * R6 (0x06) - Mic Bias Control 0
20 #define WM8903_MICDET_THR_MASK 0x0030 /* MICDET_THR - [5:4] */
23 #define WM8903_MICSHORT_THR_MASK 0x000C /* MICSHORT_THR - [3:2] */
26 #define WM8903_MICDET_ENA 0x0002 /* MICDET_ENA */
27 #define WM8903_MICDET_ENA_MASK 0x0002 /* MICDET_ENA */
30 #define WM8903_MICBIAS_ENA 0x0001 /* MICBIAS_ENA */
31 #define WM8903_MICBIAS_ENA_MASK 0x0001 /* MICBIAS_ENA */
32 #define WM8903_MICBIAS_ENA_SHIFT 0 /* MICBIAS_ENA */
40 #define WM8903_GPn_FN_GPIO_OUTPUT 0
[all …]
/linux-6.12.1/include/linux/mfd/wm8350/
Dcore.h27 #define WM8350_RESET_ID 0x00
28 #define WM8350_ID 0x01
29 #define WM8350_REVISION 0x02
30 #define WM8350_SYSTEM_CONTROL_1 0x03
31 #define WM8350_SYSTEM_CONTROL_2 0x04
32 #define WM8350_SYSTEM_HIBERNATE 0x05
33 #define WM8350_INTERFACE_CONTROL 0x06
34 #define WM8350_POWER_MGMT_1 0x08
35 #define WM8350_POWER_MGMT_2 0x09
36 #define WM8350_POWER_MGMT_3 0x0A
[all …]
Dgpio.h16 #define WM8350_GPIO_DEBOUNCE 0x80
17 #define WM8350_GPIO_PIN_PULL_UP_CONTROL 0x81
18 #define WM8350_GPIO_PULL_DOWN_CONTROL 0x82
19 #define WM8350_GPIO_INT_MODE 0x83
20 #define WM8350_GPIO_CONTROL 0x85
21 #define WM8350_GPIO_CONFIGURATION_I_O 0x86
22 #define WM8350_GPIO_PIN_POLARITY_TYPE 0x87
23 #define WM8350_GPIO_FUNCTION_SELECT_1 0x8C
24 #define WM8350_GPIO_FUNCTION_SELECT_2 0x8D
25 #define WM8350_GPIO_FUNCTION_SELECT_3 0x8E
[all …]
/linux-6.12.1/arch/arm/boot/dts/nxp/vf/
Dvf500-colibri.dtsi15 reg = <0x80000000 0x8000000>;
20 io-channels = <&adc1 0>,<&adc0 0>,
29 pinctrl-0 = <&pinctrl_touchctrl_idle>;
46 VF610_PAD_PTA18__GPIO_8 0x006d
47 VF610_PAD_PTA19__GPIO_9 0x006c
53 VF610_PAD_PTA18__ADC0_SE0 0x0040
54 VF610_PAD_PTA19__ADC0_SE1 0x0040
55 VF610_PAD_PTA16__ADC1_SE0 0x0040
56 VF610_PAD_PTB2__ADC1_SE2 0x0040
62 VF610_PAD_PTA23__GPIO_13 0x22e9
[all …]
/linux-6.12.1/include/linux/mfd/madera/
Dregisters.h14 #define MADERA_SOFTWARE_RESET 0x00
15 #define MADERA_HARDWARE_REVISION 0x01
16 #define MADERA_CTRL_IF_CFG_1 0x08
17 #define MADERA_CTRL_IF_CFG_2 0x09
18 #define MADERA_CTRL_IF_CFG_3 0x0A
19 #define MADERA_WRITE_SEQUENCER_CTRL_0 0x16
20 #define MADERA_WRITE_SEQUENCER_CTRL_1 0x17
21 #define MADERA_WRITE_SEQUENCER_CTRL_2 0x18
22 #define MADERA_TONE_GENERATOR_1 0x20
23 #define MADERA_TONE_GENERATOR_2 0x21
[all …]
/linux-6.12.1/include/linux/mfd/
Dwm8400-audio.h14 * R2 (0x02) - Power Management (1)
16 #define WM8400_CODEC_ENA 0x8000 /* CODEC_ENA */
17 #define WM8400_CODEC_ENA_MASK 0x8000 /* CODEC_ENA */
20 #define WM8400_SYSCLK_ENA 0x4000 /* SYSCLK_ENA */
21 #define WM8400_SYSCLK_ENA_MASK 0x4000 /* SYSCLK_ENA */
24 #define WM8400_SPK_MIX_ENA 0x2000 /* SPK_MIX_ENA */
25 #define WM8400_SPK_MIX_ENA_MASK 0x2000 /* SPK_MIX_ENA */
28 #define WM8400_SPK_ENA 0x1000 /* SPK_ENA */
29 #define WM8400_SPK_ENA_MASK 0x1000 /* SPK_ENA */
32 #define WM8400_OUT3_ENA 0x0800 /* OUT3_ENA */
[all …]
/linux-6.12.1/include/linux/mfd/wm831x/
Dirq.h14 #define WM831X_IRQ_TEMP_THW 0
75 * R16400 (0x4010) - System Interrupts
77 #define WM831X_PS_INT 0x8000 /* PS_INT */
78 #define WM831X_PS_INT_MASK 0x8000 /* PS_INT */
81 #define WM831X_TEMP_INT 0x4000 /* TEMP_INT */
82 #define WM831X_TEMP_INT_MASK 0x4000 /* TEMP_INT */
85 #define WM831X_GP_INT 0x2000 /* GP_INT */
86 #define WM831X_GP_INT_MASK 0x2000 /* GP_INT */
89 #define WM831X_ON_PIN_INT 0x1000 /* ON_PIN_INT */
90 #define WM831X_ON_PIN_INT_MASK 0x1000 /* ON_PIN_INT */
[all …]
Dregulator.h14 * R16462 (0x404E) - Current Sink 1
16 #define WM831X_CS1_ENA 0x8000 /* CS1_ENA */
17 #define WM831X_CS1_ENA_MASK 0x8000 /* CS1_ENA */
20 #define WM831X_CS1_DRIVE 0x4000 /* CS1_DRIVE */
21 #define WM831X_CS1_DRIVE_MASK 0x4000 /* CS1_DRIVE */
24 #define WM831X_CS1_SLPENA 0x1000 /* CS1_SLPENA */
25 #define WM831X_CS1_SLPENA_MASK 0x1000 /* CS1_SLPENA */
28 #define WM831X_CS1_OFF_RAMP_MASK 0x0C00 /* CS1_OFF_RAMP - [11:10] */
31 #define WM831X_CS1_ON_RAMP_MASK 0x0300 /* CS1_ON_RAMP - [9:8] */
34 #define WM831X_CS1_ISEL_MASK 0x003F /* CS1_ISEL - [5:0] */
[all …]
/linux-6.12.1/drivers/net/ethernet/seeq/
Dether3.h13 /* use 0 for production, 1 for verification, >2 for debug. debug flags: */
19 #define NET_DEBUG 0
25 #define REG_COMMAND (priv(dev)->seeq + 0x0000)
26 #define CMD_ENINTDMA 0x0001
27 #define CMD_ENINTRX 0x0002
28 #define CMD_ENINTTX 0x0004
29 #define CMD_ENINTBUFWIN 0x0008
30 #define CMD_ACKINTDMA 0x0010
31 #define CMD_ACKINTRX 0x0020
32 #define CMD_ACKINTTX 0x0040
[all …]
/linux-6.12.1/include/linux/usb/
Dr8a66597.h13 #define R8A66597_PLATDATA_XTAL_12MHZ 0x01
14 #define R8A66597_PLATDATA_XTAL_24MHZ 0x02
15 #define R8A66597_PLATDATA_XTAL_48MHZ 0x03
44 #define SYSCFG0 0x00
45 #define SYSCFG1 0x02
46 #define SYSSTS0 0x04
47 #define SYSSTS1 0x06
48 #define DVSTCTR0 0x08
49 #define DVSTCTR1 0x0A
50 #define TESTMODE 0x0C
[all …]

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