/linux-6.12.1/arch/arm/boot/dts/nvidia/ |
D | tegra20-acer-a500-picasso.dts | 37 memory@0 { 38 reg = <0x00000000 0x40000000>; 48 reg = <0x2ffe0000 0x10000>; /* 64kB */ 49 console-size = <0x8000>; /* 32kB */ 50 record-size = <0x400>; /* 1kB */ 56 alloc-ranges = <0x30000000 0x10000000>; 57 size = <0x10000000>; /* 256MiB */ 92 pinctrl-0 = <&state_default>; 425 shutdown-gpios = <&gpio TEGRA_GPIO(U, 0) GPIO_ACTIVE_HIGH>; 443 reg = <0x1a>; [all …]
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D | tegra124-apalis-emc.dtsi | 108 0x40040001 0x8000000a 109 0x00000001 0x00000001 110 0x00000002 0x00000000 111 0x00000002 0x00000001 112 0x00000003 0x00000008 113 0x00000003 0x00000002 114 0x00000003 0x00000006 115 0x06030203 0x000a0502 116 0x77e30303 0x70000f03 117 0x001f0000 [all …]
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D | tegra124-jetson-tk1-emc.dtsi | 104 0x40040001 105 0x8000000a 106 0x00000001 107 0x00000001 108 0x00000002 109 0x00000000 110 0x00000002 111 0x00000001 112 0x00000003 113 0x00000008 [all …]
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D | tegra30-asus-tf300t.dts | 75 reg = <0x10>; 94 mount-matrix = "0", "-1", "0", 95 "-1", "0", "0", 96 "0", "0", "-1"; 100 mount-matrix = "-1", "0", "0", 101 "0", "1", "0", 102 "0", "0", "-1"; 107 mount-matrix = "0", "-1", "0", 108 "-1", "0", "0", 109 "0", "0", "1"; [all …]
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D | tegra124-nyan-blaze-emc.dtsi | 92 0x40040001 93 0x8000000a 94 0x00000001 95 0x00000001 96 0x00000002 97 0x00000000 98 0x00000002 99 0x00000001 100 0x00000002 101 0x00000008 [all …]
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D | tegra30-asus-tf700t.dts | 92 reg = <0x10>; 111 mount-matrix = "1", "0", "0", 112 "0", "-1", "0", 113 "0", "0", "-1"; 117 mount-matrix = "0", "1", "0", 118 "1", "0", "0", 119 "0", "0", "-1"; 124 mount-matrix = "0", "-1", "0", 125 "-1", "0", "0", 126 "0", "0", "1"; [all …]
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D | tegra30-asus-tf300tg.dts | 22 <TEGRA_GPIO(X, 0) GPIO_ACTIVE_HIGH>, 171 reg = <0x10>; 190 mount-matrix = "1", "0", "0", 191 "0", "-1", "0", 192 "0", "0", "-1"; 196 mount-matrix = "-1", "0", "0", 197 "0", "1", "0", 198 "0", "0", "-1"; 203 mount-matrix = "0", "-1", "0", 204 "-1", "0", "0", [all …]
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D | tegra30-asus-tf201.dts | 67 reg = <0x4d>; 82 mount-matrix = "-1", "0", "0", 83 "0", "-1", "0", 84 "0", "0", "-1"; 88 mount-matrix = "0", "-1", "0", 89 "-1", "0", "0", 90 "0", "0", "-1"; 95 mount-matrix = "1", "0", "0", 96 "0", "-1", "0", 97 "0", "0", "1"; [all …]
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D | tegra124-nyan-big-emc.dtsi | 263 0x40040001 /* MC_EMEM_ARB_CFG */ 264 0x8000000a /* MC_EMEM_ARB_OUTSTANDING_REQ */ 265 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ 266 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ 267 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ 268 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ 269 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ 270 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ 271 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ 272 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ [all …]
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D | tegra30-asus-nexus7-grouper-memory-timings.dtsi | 5 emc-timings-0 { 6 nvidia,ram-code = <0>; /* Elpida EDJ2108EDBG-DJL-F */ 12 0x00020001 /* MC_EMEM_ARB_CFG */ 13 0xc0000020 /* MC_EMEM_ARB_OUTSTANDING_REQ */ 14 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ 15 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ 16 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ 17 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ 18 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */ 19 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ [all …]
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D | tegra30-lg-p880.dts | 17 pinctrl-0 = <&state_default>; 120 emc-timings-0 { 122 nvidia,ram-code = <0>; 127 nvidia,emem-configuration = < 0x00050001 0xc0000010 128 0x00000001 0x00000001 0x00000002 0x00000000 129 0x00000003 0x00000001 0x00000002 0x00000004 130 0x00000001 0x00000000 0x00000002 0x00000002 131 0x02020001 0x00060402 0x77230303 0x001f0000 >; 137 nvidia,emem-configuration = < 0x00020001 0xc0000010 138 0x00000001 0x00000001 0x00000002 0x00000000 [all …]
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D | tegra30-lg-p895.dts | 12 pinctrl-0 = <&state_default>; 123 nvidia,emem-configuration = < 0x00020001 0xc0000010 124 0x00000001 0x00000001 0x00000002 0x00000000 125 0x00000003 0x00000001 0x00000002 0x00000004 126 0x00000001 0x00000000 0x00000002 0x00000002 127 0x02020001 0x00060402 0x77230303 0x001f0000 >; 133 nvidia,emem-configuration = < 0x00030003 0xc0000010 134 0x00000001 0x00000001 0x00000002 0x00000000 135 0x00000003 0x00000001 0x00000002 0x00000004 136 0x00000001 0x00000000 0x00000002 0x00000002 [all …]
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D | tegra20-paz00.dts | 28 memory@0 { 29 reg = <0x00000000 0x20000000>; 55 pinctrl-0 = <&state_default>; 303 reg = <0x1e>; 335 reg = <0x34>; 471 reg = <0x4c>; 484 nvidia,cpu-pwr-off-time = <0>; 486 nvidia,core-pwr-off-time = <0>; 494 emc-tables@0 { 495 nvidia,ram-code = <0x0>; [all …]
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/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/uvd/ |
D | uvd_4_0_sh_mask.h | 26 #define UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN_MASK 0x00000001L 27 #define UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN__SHIFT 0x00000000 28 #define UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN_MASK 0x00000002L 29 #define UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN__SHIFT 0x00000001 30 #define UVD_CGC_CTRL2__GATER_DIV_ID_MASK 0x0000001cL 31 #define UVD_CGC_CTRL2__GATER_DIV_ID__SHIFT 0x00000002 32 #define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK 0x0000003cL 33 #define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT 0x00000002 34 #define UVD_CGC_CTRL__CLK_OFF_DELAY_MASK 0x000007c0L 35 #define UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT 0x00000006 [all …]
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/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/bif/ |
D | bif_3_0_sh_mask.h | 26 #define BACO_CNTL__BACO_ANA_ISO_DIS_MASK 0x00000080L 27 #define BACO_CNTL__BACO_ANA_ISO_DIS__SHIFT 0x00000007 28 #define BACO_CNTL__BACO_BCLK_OFF_MASK 0x00000002L 29 #define BACO_CNTL__BACO_BCLK_OFF__SHIFT 0x00000001 30 #define BACO_CNTL__BACO_EN_MASK 0x00000001L 31 #define BACO_CNTL__BACO_EN__SHIFT 0x00000000 32 #define BACO_CNTL__BACO_HANG_PROTECTION_EN_MASK 0x00000020L 33 #define BACO_CNTL__BACO_HANG_PROTECTION_EN__SHIFT 0x00000005 34 #define BACO_CNTL__BACO_ISO_DIS_MASK 0x00000004L 35 #define BACO_CNTL__BACO_ISO_DIS__SHIFT 0x00000002 [all …]
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/linux-6.12.1/arch/arm64/boot/dts/freescale/ |
D | imx8mm-tqma8mqml-mba8mx.dts | 30 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; 45 pinctrl-0 = <&pinctrl_usb1_connector>; 50 #size-cells = <0>; 52 port@0 { 53 reg = <0>; 65 reg = <0x27>; 70 pinctrl-0 = <&pinctrl_expander>; 126 pinctrl-0 = <&pinctrl_usbotg1>; 152 fsl,pins = <MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x00000006>, 153 <MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x00000006>, [all …]
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/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/gca/ |
D | gfx_6_0_sh_mask.h | 26 #define BCI_DEBUG_READ__DATA_MASK 0x00ffffffL 27 #define BCI_DEBUG_READ__DATA__SHIFT 0x00000000 28 #define CB_BLEND0_CONTROL__ALPHA_COMB_FCN_MASK 0x00e00000L 29 #define CB_BLEND0_CONTROL__ALPHA_COMB_FCN__SHIFT 0x00000015 30 #define CB_BLEND0_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000L 31 #define CB_BLEND0_CONTROL__ALPHA_DESTBLEND__SHIFT 0x00000018 32 #define CB_BLEND0_CONTROL__ALPHA_SRCBLEND_MASK 0x001f0000L 33 #define CB_BLEND0_CONTROL__ALPHA_SRCBLEND__SHIFT 0x00000010 34 #define CB_BLEND0_CONTROL__COLOR_COMB_FCN_MASK 0x000000e0L 35 #define CB_BLEND0_CONTROL__COLOR_COMB_FCN__SHIFT 0x00000005 [all …]
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/linux-6.12.1/drivers/gpu/drm/amd/include/ |
D | vega10_enum.h | 51 GDS_PERF_SEL_DS_ADDR_CONFL = 0, 184 NO_FORCE_REQUEST = 0x00000000, 185 FORCE_LIGHT_SLEEP_REQUEST = 0x00000001, 186 FORCE_DEEP_SLEEP_REQUEST = 0x00000002, 187 FORCE_SHUT_DOWN_REQUEST = 0x00000003, 195 NO_FORCE_REQ = 0x00000000, 196 FORCE_LIGHT_SLEEP_REQ = 0x00000001, 204 ENABLE_MEM_PWR_CTRL = 0x00000000, 205 DISABLE_MEM_PWR_CTRL = 0x00000001, 213 DYNAMIC_SHUT_DOWN_ENABLE = 0x00000000, [all …]
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D | navi10_enum.h | 51 GDS_PERF_SEL_DS_ADDR_CONFL = 0, 184 GATCL1_TYPE_NORMAL = 0x00000000, 185 GATCL1_TYPE_SHOOTDOWN = 0x00000001, 186 GATCL1_TYPE_BYPASS = 0x00000002, 194 UTCL1_TYPE_NORMAL = 0x00000000, 195 UTCL1_TYPE_SHOOTDOWN = 0x00000001, 196 UTCL1_TYPE_BYPASS = 0x00000002, 204 UTCL1_XNACK_SUCCESS = 0x00000000, 205 UTCL1_XNACK_RETRY = 0x00000001, 206 UTCL1_XNACK_PRT = 0x00000002, [all …]
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D | soc24_enum.h | 52 CP_PERFMON_ENABLE_MODE_ALWAYS_COUNT = 0x00000000, 53 CP_PERFMON_ENABLE_MODE_RESERVED_1 = 0x00000001, 54 CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_TRUE = 0x00000002, 55 CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_FALSE = 0x00000003, 63 CP_PERFMON_STATE_DISABLE_AND_RESET = 0x00000000, 64 CP_PERFMON_STATE_START_COUNTING = 0x00000001, 65 CP_PERFMON_STATE_STOP_COUNTING = 0x00000002, 66 CP_PERFMON_STATE_RESERVED_3 = 0x00000003, 67 CP_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM = 0x00000004, 68 CP_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM = 0x00000005, [all …]
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D | soc21_enum.h | 55 DSM_DATA_SEL_DISABLE = 0x00000000, 56 DSM_DATA_SEL_0 = 0x00000001, 57 DSM_DATA_SEL_1 = 0x00000002, 58 DSM_DATA_SEL_BOTH = 0x00000003, 66 DSM_ENABLE_ERROR_INJECT_FED_IN = 0x00000000, 67 DSM_ENABLE_ERROR_INJECT_SINGLE = 0x00000001, 68 DSM_ENABLE_ERROR_INJECT_UNCORRECTABLE = 0x00000002, 69 DSM_ENABLE_ERROR_INJECT_UNCORRECTABLE_LIMITED = 0x00000003, 77 DSM_SELECT_INJECT_DELAY_NO_DELAY = 0x00000000, 78 DSM_SELECT_INJECT_DELAY_DELAY_ERROR = 0x00000001, [all …]
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/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/gmc/ |
D | gmc_6_0_sh_mask.h | 26 #define ATC_ATS_CNTL__CREDITS_ATS_RPB_MASK 0x00003f00L 27 #define ATC_ATS_CNTL__CREDITS_ATS_RPB__SHIFT 0x00000008 28 #define ATC_ATS_CNTL__DEBUG_ECO_MASK 0x000f0000L 29 #define ATC_ATS_CNTL__DEBUG_ECO__SHIFT 0x00000010 30 #define ATC_ATS_CNTL__DISABLE_ATC_MASK 0x00000001L 31 #define ATC_ATS_CNTL__DISABLE_ATC__SHIFT 0x00000000 32 #define ATC_ATS_CNTL__DISABLE_PASID_MASK 0x00000004L 33 #define ATC_ATS_CNTL__DISABLE_PASID__SHIFT 0x00000002 34 #define ATC_ATS_CNTL__DISABLE_PRI_MASK 0x00000002L 35 #define ATC_ATS_CNTL__DISABLE_PRI__SHIFT 0x00000001 [all …]
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/linux-6.12.1/drivers/gpu/drm/nouveau/include/nvhw/class/ |
D | cla0b5.h | 27 #define NVA0B5_SET_SRC_PHYS_MODE (0x00000260) 28 #define NVA0B5_SET_SRC_PHYS_MODE_TARGET 1:0 29 #define NVA0B5_SET_SRC_PHYS_MODE_TARGET_LOCAL_FB (0x00000000) 30 #define NVA0B5_SET_SRC_PHYS_MODE_TARGET_COHERENT_SYSMEM (0x00000001) 31 #define NVA0B5_SET_SRC_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM (0x00000002) 32 #define NVA0B5_SET_DST_PHYS_MODE (0x00000264) 33 #define NVA0B5_SET_DST_PHYS_MODE_TARGET 1:0 34 #define NVA0B5_SET_DST_PHYS_MODE_TARGET_LOCAL_FB (0x00000000) 35 #define NVA0B5_SET_DST_PHYS_MODE_TARGET_COHERENT_SYSMEM (0x00000001) 36 #define NVA0B5_SET_DST_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM (0x00000002) [all …]
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/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/oss/ |
D | oss_1_0_sh_mask.h | 26 #define CC_DRM_ID_STRAPS__ATI_REV_ID_MASK 0xf0000000L 27 #define CC_DRM_ID_STRAPS__ATI_REV_ID__SHIFT 0x0000001c 28 #define CC_DRM_ID_STRAPS__DEVICE_ID_MASK 0x000ffff0L 29 #define CC_DRM_ID_STRAPS__DEVICE_ID__SHIFT 0x00000004 30 #define CC_DRM_ID_STRAPS__MAJOR_REV_ID_MASK 0x00f00000L 31 #define CC_DRM_ID_STRAPS__MAJOR_REV_ID__SHIFT 0x00000014 32 #define CC_DRM_ID_STRAPS__MINOR_REV_ID_MASK 0x0f000000L 33 #define CC_DRM_ID_STRAPS__MINOR_REV_ID__SHIFT 0x00000018 34 #define CC_SYS_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0x00ff0000L 35 #define CC_SYS_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x00000010 [all …]
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/linux-6.12.1/Documentation/devicetree/bindings/memory-controllers/ |
D | nvidia,tegra20-emc.yaml | 38 const: 0 41 const: 0 145 "^emc-table@[0-9]+$": 165 const: 0 172 "^emc-table@[0-9]+$": 199 reg = <0x7000f400 0x400>; 200 interrupts = <0 78 4>; 207 #interconnect-cells = <0>; 209 #size-cells = <0>; 213 emc-tables@0 { [all …]
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