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/linux-6.12.1/Documentation/driver-api/
Dreset.rst1 .. SPDX-License-Identifier: GPL-2.0-only
4 Reset controller API
10 Reset controllers are central units that control the reset signals to multiple
12 The reset controller API is split into two parts:
13 the `consumer driver interface <#consumer-driver-interface>`__ (`API reference
14 <#reset-consumer-api>`__), which allows peripheral drivers to request control
15 over their reset input signals, and the `reset controller driver interface
16 <#reset-controller-driver-interface>`__ (`API reference
17 <#reset-controller-driver-api>`__), which is used by drivers for reset
18 controller devices to register their reset controls to provide them to the
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/linux-6.12.1/drivers/reset/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
6 bool "Reset Controller Support"
9 Generic Reset Controller support.
11 This framework is designed to abstract reset handling of devices
12 via GPIOs or SoC-internal reset controller modules.
19 tristate "Altera Arria10 System Resource Reset"
22 This option enables support for the external reset functions for
26 bool "AR71xx Reset Driver" if COMPILE_TEST
29 This enables the ATH79 reset controller driver that supports the
30 AR71xx SoC reset controller.
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DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 obj-y += core.o
3 obj-y += hisilicon/
4 obj-y += starfive/
5 obj-y += sti/
6 obj-y += tegra/
7 obj-$(CONFIG_RESET_A10SR) += reset-a10sr.o
8 obj-$(CONFIG_RESET_ATH79) += reset-ath79.o
9 obj-$(CONFIG_RESET_AXS10X) += reset-axs10x.o
10 obj-$(CONFIG_RESET_BCM6345) += reset-bcm6345.o
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Dreset-ti-sci.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Texas Instrument's System Control Interface (TI-SCI) reset driver
5 * Copyright (C) 2015-2017 Texas Instruments Incorporated - https://www.ti.com/
14 #include <linux/reset-controller.h>
18 * struct ti_sci_reset_control - reset control structure
19 * @dev_id: SoC-specific device identifier
20 * @reset_mask: reset mask to use for toggling reset
21 * @lock: synchronize reset_mask read-modify-writes
30 * struct ti_sci_reset_data - reset controller information structure
31 * @rcdev: reset controller entity
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Dreset-ti-syscon.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * TI SYSCON regmap reset driver
5 * Copyright (C) 2015-2016 Texas Instruments Incorporated - https://www.ti.com/
15 #include <linux/reset-controller.h>
17 #include <dt-bindings/reset/ti-syscon.h>
20 * struct ti_syscon_reset_control - reset control structure
21 * @assert_offset: reset assert control register offset from syscon base
22 * @assert_bit: reset assert bit in the reset assert control register
23 * @deassert_offset: reset deassert control register offset from syscon base
24 * @deassert_bit: reset deassert bit in the reset deassert control register
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Dcore.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Reset Controller framework
21 #include <linux/reset.h>
22 #include <linux/reset-controller.h>
37 * struct reset_control - a reset control
38 * @rcdev: a pointer to the reset controller device
39 * this reset control belongs to
40 * @list: list entry for the rcdev's reset controller list
41 * @id: ID of the reset controller in the reset
46 * @array: Is this an array of reset controls (1)?
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Dreset-scmi.c1 // SPDX-License-Identifier: GPL-2.0
3 * ARM System Control and Management Interface (ARM SCMI) reset driver
5 * Copyright (C) 2019-2021 ARM Ltd.
11 #include <linux/reset-controller.h>
17 * struct scmi_reset_data - reset controller information structure
18 * @rcdev: reset controller entity
27 #define to_scmi_handle(p) (to_scmi_reset_data(p)->ph)
30 * scmi_reset_assert() - assert device reset
31 * @rcdev: reset controller entity
32 * @id: ID of the reset to be asserted
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/linux-6.12.1/Documentation/devicetree/bindings/reset/
Dzynq-reset.txt1 Xilinx Zynq Reset Manager
3 The Zynq AP-SoC has several different resets.
8 - compatible: "xlnx,zynq-reset"
9 - reg: SLCR offset and size taken via syscon <0x200 0x48>
10 - syscon: <&slcr>
12 - #reset-cells: Must be 1
14 The Zynq Reset Manager needs to be a childnode of the SLCR.
18 compatible = "xlnx,zynq-reset";
20 #reset-cells = <1>;
24 Reset outputs:
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Dsocionext,uniphier-reset.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/reset/socionext,uniphier-reset.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: UniPhier reset controller
10 - Masahiro Yamada <yamada.masahiro@socionext.com>
15 - description: System reset
17 - socionext,uniphier-ld4-reset
18 - socionext,uniphier-pro4-reset
19 - socionext,uniphier-sld8-reset
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Dreset.txt1 = Reset Signal Device Tree Bindings =
3 This binding is intended to represent the hardware reset signals present
4 internally in most IC (SoC, FPGA, ...) designs. Reset signals for whole
8 Hardware blocks typically receive a reset signal. This signal is generated by
9 a reset provider (e.g. power management or clock module) and received by a
10 reset consumer (the module being reset, or a module managing when a sub-
11 ordinate module is reset). This binding exists to represent the provider and
14 A reset signal is represented by the phandle of the provider, plus a reset
15 specifier - a list of DT cells that represents the reset signal within the
16 provider. The length (number of cells) and semantics of the reset specifier
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Dti-syscon-reset.txt1 TI SysCon Reset Controller
4 Almost all SoCs have hardware modules that require reset control in addition
5 to clock and power control for their functionality. The reset control is
6 typically provided by means of memory-mapped I/O registers. These registers are
12 A SysCon Reset Controller node defines a device that uses a syscon node
13 and provides reset management functionality for various hardware modules
16 SysCon Reset Controller Node
18 Each of the reset provider/controller nodes should be a child of a syscon
22 --------------------
23 - compatible : Should be,
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Dsocionext,uniphier-glue-reset.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/reset/socionext,uniphier-glue-reset.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Socionext UniPhier peripheral core reset in glue layer
10 Some peripheral core reset belongs to its own glue layer. Before using
11 this core reset, it is necessary to control the clocks and resets to
16 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
21 - socionext,uniphier-pro4-usb3-reset
22 - socionext,uniphier-pro5-usb3-reset
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Dxlnx,zynqmp-reset.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/reset/xlnx,zynqmp-reset.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Zynq UltraScale+ MPSoC and Versal reset
10 - Mubin Sayyed <mubin.sayyed@amd.com>
11 - Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
16 The PS reset subsystem is responsible for handling the external reset
17 input to the device and that all internal reset requirements are met
20 Please also refer to reset.txt in this directory for common reset
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Damlogic,meson-reset.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/reset/amlogic,meson-reset.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Amlogic Meson SoC Reset Controller
11 - Neil Armstrong <neil.armstrong@linaro.org>
16 - amlogic,meson8b-reset # Reset Controller on Meson8b and compatible SoCs
17 - amlogic,meson-gxbb-reset # Reset Controller on GXBB and compatible SoCs
18 - amlogic,meson-axg-reset # Reset Controller on AXG and compatible SoCs
19 - amlogic,meson-a1-reset # Reset Controller on A1 and compatible SoCs
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Dsnps,hsdk-reset.txt1 Binding for the Synopsys HSDK reset controller
3 This binding uses the common reset binding[1].
5 [1] Documentation/devicetree/bindings/reset/reset.txt
8 - compatible: should be "snps,hsdk-reset".
9 - reg: should always contain 2 pairs address - length: first for reset
10 configuration register and second for corresponding SW reset and status bits
12 - #reset-cells: from common reset binding; Should always be set to 1.
15 reset: reset@880 {
16 compatible = "snps,hsdk-reset";
17 #reset-cells = <1>;
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Dimg,pistachio-reset.txt1 Pistachio Reset Controller
4 This binding describes a reset controller device that is used to enable and
5 disable individual IP blocks within the Pistachio SoC using "soft reset"
8 The actual action taken when soft reset is asserted is hardware dependent.
13 Please refer to Documentation/devicetree/bindings/reset/reset.txt
14 for common reset controller binding usage.
18 - compatible: Contains "img,pistachio-reset"
20 - #reset-cells: Contains 1
25 compatible = "img,pistachio-cr-periph", "syscon", "simple-mfd";
28 clock-names = "sys";
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Dhisilicon,hi3660-reset.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/reset/hisilicon,hi3660-reset.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Hisilicon System Reset Controller
10 - Wei Xu <xuwei5@hisilicon.com>
13 Please also refer to reset.txt in this directory for common reset
15 The reset controller registers are part of the system-ctl block on
21 - items:
22 - const: hisilicon,hi3660-reset
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Dfsl,imx7-src.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/reset/fsl,imx7-src.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX7 System Reset Controller
10 - Andrey Smirnov <andrew.smirnov@gmail.com>
13 The system reset controller can be used to reset various set of
14 peripherals. Device nodes that need access to reset lines should
15 specify them as a reset phandle in their corresponding node as
16 specified in reset.txt.
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/linux-6.12.1/drivers/power/reset/
Dat91-reset.c2 * Atmel AT91 SAM9 & SAMA5 SoCs reset code
6 * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcosoft.com>
20 #include <linux/reset-controller.h>
26 #include <dt-bindings/reset/sama7g5-reset.h>
28 #define AT91_RSTC_CR 0x00 /* Reset Controller Control Register */
29 #define AT91_RSTC_PROCRST BIT(0) /* Processor Reset */
30 #define AT91_RSTC_PERRST BIT(2) /* Peripheral Reset */
31 #define AT91_RSTC_EXTRST BIT(3) /* External Reset */
34 #define AT91_RSTC_SR 0x04 /* Reset Controller Status Register */
35 #define AT91_RSTC_URSTS BIT(0) /* User Reset Status */
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/linux-6.12.1/include/linux/
Dreset.h1 /* SPDX-License-Identifier: GPL-2.0 */
14 * struct reset_control_bulk_data - Data used for bulk reset control operations.
16 * @id: reset control consumer ID
17 * @rstc: struct reset_control * to store the associated reset control
19 * The reset APIs provide a series of reset_control_bulk_*() API calls as
20 * a convenience to consumers which require multiple reset controls.
114 return optional ? 0 : -ENOTSUPP; in __device_reset()
122 return optional ? NULL : ERR_PTR(-ENOTSUPP); in __of_reset_control_get()
130 return optional ? NULL : ERR_PTR(-ENOTSUPP); in __reset_control_get()
167 return optional ? 0 : -EOPNOTSUPP; in __reset_control_bulk_get()
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Dreset-controller.h1 /* SPDX-License-Identifier: GPL-2.0 */
10 * struct reset_control_ops - reset controller driver callbacks
12 * @reset: for self-deasserting resets, does all necessary
13 * things to reset the device
14 * @assert: manually assert the reset line, if supported
15 * @deassert: manually deassert the reset line, if supported
16 * @status: return the status of the reset line, if supported
19 int (*reset)(struct reset_controller_dev *rcdev, unsigned long id); member
30 * struct reset_control_lookup - represents a single lookup entry
32 * @list: internal list of all reset lookup entries
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/linux-6.12.1/drivers/infiniband/hw/irdma/
Di40iw_hw.h1 /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */
2 /* Copyright (c) 2015 - 2021 Intel Corporation */
5 #define I40E_VFPE_CQPTAIL1 0x0000A000 /* Reset: VFR */
6 #define I40E_VFPE_CQPDB1 0x0000BC00 /* Reset: VFR */
7 #define I40E_VFPE_CCQPSTATUS1 0x0000B800 /* Reset: VFR */
8 #define I40E_VFPE_CCQPHIGH1 0x00009800 /* Reset: VFR */
9 #define I40E_VFPE_CCQPLOW1 0x0000AC00 /* Reset: VFR */
10 #define I40E_VFPE_CQARM1 0x0000B400 /* Reset: VFR */
11 #define I40E_VFPE_CQACK1 0x0000B000 /* Reset: VFR */
12 #define I40E_VFPE_AEQALLOC1 0x0000A400 /* Reset: VFR */
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/linux-6.12.1/Documentation/devicetree/bindings/power/reset/
Dkeystone-reset.txt1 * Device tree bindings for Texas Instruments keystone reset
3 This node is intended to allow SoC reset in case of software reset
6 The Keystone SoCs can contain up to 4 watchdog timers to reset
7 SoC. Each watchdog timer event input is connected to the Reset Mux
8 block. The Reset Mux block can be configured to cause reset or not.
10 Additionally soft or hard reset can be configured.
14 - compatible: ti,keystone-reset
16 - ti,syscon-pll: phandle/offset pair. The phandle to syscon used to
18 reset control registers.
20 - ti,syscon-dev: phandle/offset pair. The phandle to syscon used to
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/linux-6.12.1/drivers/clk/visconti/
Dreset.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Toshiba Visconti ARM SoC reset controller
16 #include "reset.h"
25 struct visconti_reset *reset = to_visconti_reset(rcdev); in visconti_reset_assert() local
26 const struct visconti_reset_data *data = &reset->resets[id]; in visconti_reset_assert()
27 u32 rst = BIT(data->rs_idx); in visconti_reset_assert()
31 spin_lock_irqsave(reset->lock, flags); in visconti_reset_assert()
32 ret = regmap_update_bits(reset->regmap, data->rson_offset, rst, rst); in visconti_reset_assert()
33 spin_unlock_irqrestore(reset->lock, flags); in visconti_reset_assert()
40 struct visconti_reset *reset = to_visconti_reset(rcdev); in visconti_reset_deassert() local
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/linux-6.12.1/drivers/gpu/drm/i915/gt/
Dintel_reset.c1 // SPDX-License-Identifier: MIT
3 * Copyright © 2008-2018 Intel Corporation
41 struct drm_i915_file_private *file_priv = ctx->file_priv; in client_mark_guilty()
52 prev_hang = xchg(&file_priv->hang_timestamp, jiffies); in client_mark_guilty()
57 atomic_add(score, &file_priv->ban_score); in client_mark_guilty()
59 drm_dbg(&ctx->i915->drm, in client_mark_guilty()
61 ctx->name, score, in client_mark_guilty()
62 atomic_read(&file_priv->ban_score)); in client_mark_guilty()
73 if (intel_context_is_closed(rq->context)) in mark_guilty()
77 ctx = rcu_dereference(rq->context->gem_context); in mark_guilty()
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