1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved. 5 */ 6 7 #ifndef _CNSS_PCI_H 8 #define _CNSS_PCI_H 9 10 #include <linux/cma.h> 11 #include <linux/iommu.h> 12 #include <linux/qcom-iommu-util.h> 13 #include <linux/mhi.h> 14 #if IS_ENABLED(CONFIG_MHI_BUS_MISC) 15 #include <linux/mhi_misc.h> 16 #endif 17 #if IS_ENABLED(CONFIG_PCI_MSM) 18 #include <linux/msm_pcie.h> 19 #endif 20 #include <linux/of_reserved_mem.h> 21 #include <linux/pci.h> 22 #include <linux/sched_clock.h> 23 #include <linux/version.h> 24 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(6, 2, 0)) 25 #include <linux/sched/clock.h> 26 #endif 27 28 29 #include "main.h" 30 31 #define PM_OPTIONS_DEFAULT 0 32 #define PCI_LINK_DOWN 0 33 34 #ifdef CONFIG_CNSS_SUPPORT_DUAL_DEV 35 #define LINK_TRAINING_RETRY_MAX_TIMES 2 36 #else 37 #define LINK_TRAINING_RETRY_MAX_TIMES 3 38 #endif 39 40 #define LINK_TRAINING_RETRY_DELAY_MS 500 41 #define MSI_USERS 4 42 43 #define CNSS_MHI_IN_MISSION_MODE(ee) (ee == MHI_EE_AMSS || \ 44 ee == MHI_EE_WFW || \ 45 ee == MHI_EE_FP) 46 47 enum cnss_mhi_state { 48 CNSS_MHI_INIT, 49 CNSS_MHI_DEINIT, 50 CNSS_MHI_POWER_ON, 51 CNSS_MHI_POWERING_OFF, 52 CNSS_MHI_POWER_OFF, 53 CNSS_MHI_FORCE_POWER_OFF, 54 CNSS_MHI_SUSPEND, 55 CNSS_MHI_RESUME, 56 CNSS_MHI_TRIGGER_RDDM, 57 CNSS_MHI_RDDM, 58 CNSS_MHI_RDDM_DONE, 59 }; 60 61 enum pci_link_status { 62 PCI_GEN1, 63 PCI_GEN2, 64 PCI_DEF, 65 }; 66 67 enum cnss_rtpm_id { 68 RTPM_ID_CNSS, 69 RTPM_ID_MHI, 70 RTPM_ID_MAX, 71 }; 72 73 enum cnss_pci_reg_dev_mask { 74 REG_MASK_QCA6390, 75 REG_MASK_QCA6490, 76 REG_MASK_KIWI, 77 REG_MASK_MANGO, 78 REG_MASK_PEACH, 79 }; 80 81 enum cnss_smmu_fault_time { 82 SMMU_CB_ENTRY, 83 SMMU_CB_DOORBELL_RING, 84 SMMU_CB_EXIT, 85 SMMU_CB_MAX, 86 }; 87 88 struct cnss_msi_user { 89 char *name; 90 int num_vectors; 91 u32 base_vector; 92 }; 93 94 struct cnss_msi_config { 95 int total_vectors; 96 int total_users; 97 struct cnss_msi_user *users; 98 }; 99 100 struct cnss_pci_reg { 101 char *name; 102 u32 offset; 103 }; 104 105 struct cnss_pci_debug_reg { 106 u32 offset; 107 u32 val; 108 }; 109 110 struct cnss_misc_reg { 111 unsigned long dev_mask; 112 u8 wr; 113 u32 offset; 114 u32 val; 115 }; 116 117 struct cnss_pm_stats { 118 atomic_t runtime_get; 119 atomic_t runtime_put; 120 atomic_t runtime_get_id[RTPM_ID_MAX]; 121 atomic_t runtime_put_id[RTPM_ID_MAX]; 122 u64 runtime_get_timestamp_id[RTPM_ID_MAX]; 123 u64 runtime_put_timestamp_id[RTPM_ID_MAX]; 124 }; 125 126 struct cnss_print_optimize { 127 int msi_log_chk[MSI_USERS]; 128 int msi_addr_chk; 129 }; 130 131 struct cnss_pci_data { 132 struct pci_dev *pci_dev; 133 struct cnss_plat_data *plat_priv; 134 const struct pci_device_id *pci_device_id; 135 u32 device_id; 136 u16 revision_id; 137 u64 dma_bit_mask; 138 struct cnss_wlan_driver *driver_ops; 139 u8 pci_link_state; 140 u8 pci_link_down_ind; 141 struct pci_saved_state *saved_state; 142 struct pci_saved_state *default_state; 143 #if IS_ENABLED(CONFIG_PCI_MSM) 144 struct msm_pcie_register_event msm_pci_event; 145 #endif 146 struct cnss_pm_stats pm_stats; 147 atomic_t auto_suspended; 148 atomic_t drv_connected; 149 u8 drv_connected_last; 150 u32 qmi_send_usage_count; 151 u16 def_link_speed; 152 u16 def_link_width; 153 u16 cur_link_speed; 154 int wake_gpio; 155 int wake_irq; 156 u32 wake_counter; 157 u8 monitor_wake_intr; 158 struct iommu_domain *iommu_domain; 159 u8 smmu_s1_enable; 160 dma_addr_t smmu_iova_start; 161 size_t smmu_iova_len; 162 dma_addr_t smmu_iova_ipa_start; 163 dma_addr_t smmu_iova_ipa_current; 164 size_t smmu_iova_ipa_len; 165 void __iomem *bar; 166 struct cnss_msi_config *msi_config; 167 u32 msi_ep_base_data; 168 u32 msix_addr; 169 struct mhi_controller *mhi_ctrl; 170 unsigned long mhi_state; 171 u32 remap_window; 172 struct completion wake_event_complete; 173 struct timer_list dev_rddm_timer; 174 struct timer_list boot_debug_timer; 175 struct delayed_work time_sync_work; 176 u8 disable_pc; 177 struct mutex bus_lock; /* mutex for suspend and resume bus */ 178 struct cnss_pci_debug_reg *debug_reg; 179 struct cnss_misc_reg *wcss_reg; 180 struct cnss_misc_reg *pcie_reg; 181 struct cnss_misc_reg *wlaon_reg; 182 struct cnss_misc_reg *syspm_reg; 183 unsigned long misc_reg_dev_mask; 184 u8 iommu_geometry; 185 bool drv_supported; 186 bool is_smmu_fault; 187 unsigned long long smmu_fault_timestamp[SMMU_CB_MAX]; 188 }; 189 cnss_set_pci_priv(struct pci_dev * pci_dev,void * data)190 static inline void cnss_set_pci_priv(struct pci_dev *pci_dev, void *data) 191 { 192 pci_set_drvdata(pci_dev, data); 193 } 194 cnss_get_pci_priv(struct pci_dev * pci_dev)195 static inline struct cnss_pci_data *cnss_get_pci_priv(struct pci_dev *pci_dev) 196 { 197 return pci_get_drvdata(pci_dev); 198 } 199 cnss_pci_priv_to_plat_priv(void * bus_priv)200 static inline struct cnss_plat_data *cnss_pci_priv_to_plat_priv(void *bus_priv) 201 { 202 struct cnss_pci_data *pci_priv = bus_priv; 203 204 return pci_priv->plat_priv; 205 } 206 cnss_pci_set_monitor_wake_intr(void * bus_priv,bool val)207 static inline void cnss_pci_set_monitor_wake_intr(void *bus_priv, bool val) 208 { 209 struct cnss_pci_data *pci_priv = bus_priv; 210 211 pci_priv->monitor_wake_intr = val; 212 } 213 cnss_pci_get_monitor_wake_intr(void * bus_priv)214 static inline bool cnss_pci_get_monitor_wake_intr(void *bus_priv) 215 { 216 struct cnss_pci_data *pci_priv = bus_priv; 217 218 return pci_priv->monitor_wake_intr; 219 } 220 cnss_pci_set_auto_suspended(void * bus_priv,int val)221 static inline void cnss_pci_set_auto_suspended(void *bus_priv, int val) 222 { 223 struct cnss_pci_data *pci_priv = bus_priv; 224 225 atomic_set(&pci_priv->auto_suspended, val); 226 } 227 cnss_pci_get_auto_suspended(void * bus_priv)228 static inline int cnss_pci_get_auto_suspended(void *bus_priv) 229 { 230 struct cnss_pci_data *pci_priv = bus_priv; 231 232 return atomic_read(&pci_priv->auto_suspended); 233 } 234 cnss_pci_set_drv_connected(void * bus_priv,int val)235 static inline void cnss_pci_set_drv_connected(void *bus_priv, int val) 236 { 237 struct cnss_pci_data *pci_priv = bus_priv; 238 239 atomic_set(&pci_priv->drv_connected, val); 240 } 241 cnss_pci_get_drv_connected(void * bus_priv)242 static inline int cnss_pci_get_drv_connected(void *bus_priv) 243 { 244 struct cnss_pci_data *pci_priv = bus_priv; 245 246 return atomic_read(&pci_priv->drv_connected); 247 } 248 249 void cnss_mhi_controller_set_base(struct cnss_pci_data *pci_priv, 250 phys_addr_t base); 251 int cnss_pci_check_link_status(struct cnss_pci_data *pci_priv); 252 int cnss_suspend_pci_link(struct cnss_pci_data *pci_priv); 253 int cnss_resume_pci_link(struct cnss_pci_data *pci_priv); 254 int cnss_pci_recover_link_down(struct cnss_pci_data *pci_priv); 255 int cnss_pci_init(struct cnss_plat_data *plat_priv); 256 void cnss_pci_deinit(struct cnss_plat_data *plat_priv); 257 void cnss_pci_add_fw_prefix_name(struct cnss_pci_data *pci_priv, 258 char *prefix_name, char *name); 259 int cnss_pci_alloc_fw_mem(struct cnss_pci_data *pci_priv); 260 int cnss_pci_alloc_qdss_mem(struct cnss_pci_data *pci_priv); 261 void cnss_pci_free_qdss_mem(struct cnss_pci_data *pci_priv); 262 int cnss_pci_load_tme_patch(struct cnss_pci_data *pci_priv); 263 int cnss_pci_load_tme_opt_file(struct cnss_pci_data *pci_priv, 264 enum wlfw_tme_lite_file_type_v01 file); 265 int cnss_pci_load_m3(struct cnss_pci_data *pci_priv); 266 void cnss_pci_free_blob_mem(struct cnss_pci_data *pci_priv); 267 int cnss_pci_load_aux(struct cnss_pci_data *pci_priv); 268 int cnss_pci_handle_dev_sol_irq(struct cnss_pci_data *pci_priv); 269 int cnss_pci_start_mhi(struct cnss_pci_data *pci_priv); 270 void cnss_pci_collect_dump_info(struct cnss_pci_data *pci_priv, bool in_panic); 271 #ifdef CONFIG_CNSS2_SSR_DRIVER_DUMP 272 void cnss_pci_collect_host_dump_info(struct cnss_pci_data *pci_priv); 273 #else 274 static inline cnss_pci_collect_host_dump_info(struct cnss_pci_data * pci_priv)275 void cnss_pci_collect_host_dump_info(struct cnss_pci_data *pci_priv) 276 { 277 } 278 #endif 279 void cnss_pci_device_crashed(struct cnss_pci_data *pci_priv); 280 void cnss_pci_clear_dump_info(struct cnss_pci_data *pci_priv); 281 u32 cnss_pci_get_wake_msi(struct cnss_pci_data *pci_priv); 282 int cnss_pci_force_fw_assert_hdlr(struct cnss_pci_data *pci_priv); 283 int cnss_pci_qmi_send_get(struct cnss_pci_data *pci_priv); 284 int cnss_pci_qmi_send_put(struct cnss_pci_data *pci_priv); 285 void cnss_pci_fw_boot_timeout_hdlr(struct cnss_pci_data *pci_priv); 286 int cnss_pci_call_driver_probe(struct cnss_pci_data *pci_priv); 287 int cnss_pci_call_driver_remove(struct cnss_pci_data *pci_priv); 288 int cnss_pci_dev_powerup(struct cnss_pci_data *pci_priv); 289 int cnss_pci_dev_shutdown(struct cnss_pci_data *pci_priv); 290 int cnss_pci_dev_crash_shutdown(struct cnss_pci_data *pci_priv); 291 int cnss_pci_dev_ramdump(struct cnss_pci_data *pci_priv); 292 int cnss_pci_register_driver_hdlr(struct cnss_pci_data *pci_priv, void *data); 293 int cnss_pci_unregister_driver_hdlr(struct cnss_pci_data *pci_priv); 294 int cnss_pci_call_driver_modem_status(struct cnss_pci_data *pci_priv, 295 int modem_current_status); 296 void cnss_pci_pm_runtime_show_usage_count(struct cnss_pci_data *pci_priv); 297 int cnss_pci_pm_request_resume(struct cnss_pci_data *pci_priv); 298 int cnss_pci_pm_runtime_resume(struct cnss_pci_data *pci_priv); 299 int cnss_pci_pm_runtime_get(struct cnss_pci_data *pci_priv, 300 enum cnss_rtpm_id id); 301 int cnss_pci_pm_runtime_get_sync(struct cnss_pci_data *pci_priv, 302 enum cnss_rtpm_id id); 303 void cnss_pci_pm_runtime_get_noresume(struct cnss_pci_data *pci_priv, 304 enum cnss_rtpm_id id); 305 int cnss_pci_pm_runtime_put_autosuspend(struct cnss_pci_data *pci_priv, 306 enum cnss_rtpm_id id); 307 void cnss_pci_pm_runtime_put_noidle(struct cnss_pci_data *pci_priv, 308 enum cnss_rtpm_id id); 309 void cnss_pci_pm_runtime_mark_last_busy(struct cnss_pci_data *pci_priv); 310 int cnss_pci_update_status(struct cnss_pci_data *pci_priv, 311 enum cnss_driver_status status); 312 int cnss_pci_call_driver_uevent(struct cnss_pci_data *pci_priv, 313 enum cnss_driver_status status, void *data); 314 int cnss_pcie_is_device_down(struct cnss_pci_data *pci_priv); 315 int cnss_pci_shutdown_cleanup(struct cnss_pci_data *pci_priv); 316 int cnss_pci_suspend_bus(struct cnss_pci_data *pci_priv); 317 int cnss_pci_resume_bus(struct cnss_pci_data *pci_priv); 318 int cnss_pci_debug_reg_read(struct cnss_pci_data *pci_priv, u32 offset, 319 u32 *val, bool raw_access); 320 int cnss_pci_debug_reg_write(struct cnss_pci_data *pci_priv, u32 offset, 321 u32 val, bool raw_access); 322 int cnss_pci_get_iova(struct cnss_pci_data *pci_priv, u64 *addr, u64 *size); 323 int cnss_pci_get_iova_ipa(struct cnss_pci_data *pci_priv, u64 *addr, 324 u64 *size); 325 bool cnss_pci_is_smmu_s1_enabled(struct cnss_pci_data *pci_priv); 326 void cnss_pci_handle_linkdown(struct cnss_pci_data *pci_priv); 327 328 int cnss_pci_update_time_sync_period(struct cnss_pci_data *pci_priv, 329 unsigned int time_sync_period); 330 int cnss_pci_set_therm_cdev_state(struct cnss_pci_data *pci_priv, 331 unsigned long thermal_state, 332 int tcdev_id); 333 int cnss_pci_get_user_msi_assignment(struct cnss_pci_data *pci_priv, 334 char *user_name, 335 int *num_vectors, 336 u32 *user_base_data, 337 u32 *base_vector); 338 void cnss_register_iommu_fault_handler_irq(struct cnss_pci_data *pci_priv); 339 #endif /* _CNSS_PCI_H */ 340