1  /*
2   * Copyright 2022 Advanced Micro Devices, Inc.
3   *
4   * Permission is hereby granted, free of charge, to any person obtaining a
5   * copy of this software and associated documentation files (the "Software"),
6   * to deal in the Software without restriction, including without limitation
7   * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8   * and/or sell copies of the Software, and to permit persons to whom the
9   * Software is furnished to do so, subject to the following conditions:
10   *
11   * The above copyright notice and this permission notice shall be included in
12   * all copies or substantial portions of the Software.
13   *
14   * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15   * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16   * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17   * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18   * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19   * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20   * OTHER DEALINGS IN THE SOFTWARE.
21   *
22   */
23  
24  #ifndef __AMDGPU_RING_MUX__
25  #define __AMDGPU_RING_MUX__
26  
27  #include <linux/timer.h>
28  #include <linux/spinlock.h>
29  #include "amdgpu_ring.h"
30  
31  struct amdgpu_ring;
32  
33  /**
34   * struct amdgpu_mux_entry - the entry recording software rings copying information.
35   * @ring: the pointer to the software ring.
36   * @start_ptr_in_hw_ring: last start location copied to in the hardware ring.
37   * @end_ptr_in_hw_ring: last end location copied to in the hardware ring.
38   * @sw_cptr: the position of the copy pointer in the sw ring.
39   * @sw_rptr: the read pointer in software ring.
40   * @sw_wptr: the write pointer in software ring.
41   * @list: list head for amdgpu_mux_chunk
42   */
43  struct amdgpu_mux_entry {
44  	struct amdgpu_ring      *ring;
45  	u64                     start_ptr_in_hw_ring;
46  	u64                     end_ptr_in_hw_ring;
47  	u64                     sw_cptr;
48  	u64                     sw_rptr;
49  	u64                     sw_wptr;
50  	struct list_head        list;
51  };
52  
53  enum amdgpu_ring_mux_offset_type {
54  	AMDGPU_MUX_OFFSET_TYPE_CONTROL,
55  	AMDGPU_MUX_OFFSET_TYPE_DE,
56  	AMDGPU_MUX_OFFSET_TYPE_CE,
57  };
58  
59  enum ib_complete_status {
60  	/* IB not started/reset value, default value. */
61  	IB_COMPLETION_STATUS_DEFAULT = 0,
62  	/* IB preempted, started but not completed. */
63  	IB_COMPLETION_STATUS_PREEMPTED = 1,
64  	/* IB completed. */
65  	IB_COMPLETION_STATUS_COMPLETED = 2,
66  };
67  
68  struct amdgpu_ring_mux {
69  	struct amdgpu_ring      *real_ring;
70  
71  	struct amdgpu_mux_entry *ring_entry;
72  	unsigned int            num_ring_entries;
73  	unsigned int            ring_entry_size;
74  	/*the lock for copy data from different software rings*/
75  	spinlock_t              lock;
76  	bool                    s_resubmit;
77  	uint32_t                seqno_to_resubmit;
78  	u64                     wptr_resubmit;
79  	struct timer_list       resubmit_timer;
80  
81  	bool                    pending_trailing_fence_signaled;
82  };
83  
84  /**
85   * struct amdgpu_mux_chunk - save the location of indirect buffer's package on softare rings.
86   * @entry: the list entry.
87   * @sync_seq: the fence seqno related with the saved IB.
88   * @start:- start location on the software ring.
89   * @end:- end location on the software ring.
90   * @control_offset:- the PRE_RESUME bit position used for resubmission.
91   * @de_offset:- the anchor in write_data for de meta of resubmission.
92   * @ce_offset:- the anchor in write_data for ce meta of resubmission.
93   */
94  struct amdgpu_mux_chunk {
95  	struct list_head        entry;
96  	uint32_t                sync_seq;
97  	u64                     start;
98  	u64                     end;
99  	u64                     cntl_offset;
100  	u64                     de_offset;
101  	u64                     ce_offset;
102  };
103  
104  int amdgpu_ring_mux_init(struct amdgpu_ring_mux *mux, struct amdgpu_ring *ring,
105  			 unsigned int entry_size);
106  void amdgpu_ring_mux_fini(struct amdgpu_ring_mux *mux);
107  int amdgpu_ring_mux_add_sw_ring(struct amdgpu_ring_mux *mux, struct amdgpu_ring *ring);
108  void amdgpu_ring_mux_set_wptr(struct amdgpu_ring_mux *mux, struct amdgpu_ring *ring, u64 wptr);
109  u64 amdgpu_ring_mux_get_wptr(struct amdgpu_ring_mux *mux, struct amdgpu_ring *ring);
110  u64 amdgpu_ring_mux_get_rptr(struct amdgpu_ring_mux *mux, struct amdgpu_ring *ring);
111  void amdgpu_ring_mux_start_ib(struct amdgpu_ring_mux *mux, struct amdgpu_ring *ring);
112  void amdgpu_ring_mux_end_ib(struct amdgpu_ring_mux *mux, struct amdgpu_ring *ring);
113  void amdgpu_ring_mux_ib_mark_offset(struct amdgpu_ring_mux *mux, struct amdgpu_ring *ring,
114  				    u64 offset, enum amdgpu_ring_mux_offset_type type);
115  bool amdgpu_mcbp_handle_trailing_fence_irq(struct amdgpu_ring_mux *mux);
116  
117  u64 amdgpu_sw_ring_get_rptr_gfx(struct amdgpu_ring *ring);
118  u64 amdgpu_sw_ring_get_wptr_gfx(struct amdgpu_ring *ring);
119  void amdgpu_sw_ring_set_wptr_gfx(struct amdgpu_ring *ring);
120  void amdgpu_sw_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count);
121  void amdgpu_sw_ring_ib_begin(struct amdgpu_ring *ring);
122  void amdgpu_sw_ring_ib_end(struct amdgpu_ring *ring);
123  void amdgpu_sw_ring_ib_mark_offset(struct amdgpu_ring *ring, enum amdgpu_ring_mux_offset_type type);
124  const char *amdgpu_sw_ring_name(int idx);
125  unsigned int amdgpu_sw_ring_priority(int idx);
126  
127  #endif
128