1 /* 2 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #if defined(WCN6450_HEADERS_DEF) 18 19 #include "msmhwiobase.h" 20 #include "hwio.h" 21 22 #define WCN6450_CE0_BASE_ADDRESS HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE 23 #define WCN6450_CE1_BASE_ADDRESS HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE 24 25 #define WCN6450_SR_WR_INDEX_OFFSET \ 26 (HWIO_HOST_SOC_A_WFSS_CE0_SRC_WR_INDEX_ADDR - \ 27 WCN6450_CE0_BASE_ADDRESS) 28 #define WCN6450_DST_WR_INDEX_OFFSET \ 29 (HWIO_HOST_SOC_A_WFSS_CE0_DST_WR_INDEX_ADDR - \ 30 WCN6450_CE0_BASE_ADDRESS) 31 #define WCN6450_SRC_WATERMARK_OFFSET \ 32 (HWIO_HOST_SOC_A_WFSS_CE0_SRC_WATERMARK_ADDR - \ 33 WCN6450_CE0_BASE_ADDRESS) 34 #define WCN6450_SRC_WATERMARK_LOW_MASK \ 35 HWIO_HOST_SOC_A_WFSS_CE0_SRC_WATERMARK_SR_LOW_WATER_MARK_THRESOLD_BMSK 36 #define WCN6450_SRC_WATERMARK_LOW_LSB \ 37 HWIO_HOST_SOC_A_WFSS_CE0_SRC_WATERMARK_SR_LOW_WATER_MARK_THRESOLD_SHFT 38 #define WCN6450_SRC_WATERMARK_HIGH_MASK \ 39 HWIO_HOST_SOC_A_WFSS_CE0_SRC_WATERMARK_SR_HIGH_WATER_MARK_THRESHOLD_BMSK 40 #define WCN6450_SRC_WATERMARK_HIGH_LSB \ 41 HWIO_HOST_SOC_A_WFSS_CE0_SRC_WATERMARK_SR_HIGH_WATER_MARK_THRESHOLD_SHFT 42 #define WCN6450_DST_WATERMARK_OFFSET \ 43 (HWIO_HOST_SOC_A_WFSS_CE0_DST_WATERMARK_ADDR - \ 44 WCN6450_CE0_BASE_ADDRESS) 45 #define WCN6450_DST_WATERMARK_LOW_MASK \ 46 HWIO_HOST_SOC_A_WFSS_CE0_DST_WATERMARK_DR_LOW_WATER_MARK_THRESHOLD_BMSK 47 #define WCN6450_DST_WATERMARK_LOW_LSB \ 48 HWIO_HOST_SOC_A_WFSS_CE0_DST_WATERMARK_DR_LOW_WATER_MARK_THRESHOLD_SHFT 49 #define WCN6450_DST_WATERMARK_HIGH_MASK \ 50 HWIO_HOST_SOC_A_WFSS_CE0_DST_WATERMARK_DR_HIGH_WATER_MARK_THRESHOLD_BMSK 51 #define WCN6450_DST_WATERMARK_HIGH_LSB \ 52 HWIO_HOST_SOC_A_WFSS_CE0_DST_WATERMARK_DR_HIGH_WATER_MARK_THRESHOLD_SHFT 53 #define WCN6450_CURRENT_SRRI_OFFSET \ 54 (HWIO_HOST_SOC_A_WFSS_CE0_CURRENT_SRRI_ADDR - \ 55 WCN6450_CE0_BASE_ADDRESS) 56 #define WCN6450_CURRENT_DRRI_OFFSET \ 57 (HWIO_HOST_SOC_A_WFSS_CE0_CURRENT_DRRI_ADDR - \ 58 WCN6450_CE0_BASE_ADDRESS) 59 #define WCN6450_HOST_IS_SRC_RING_HIGH_WATERMARK_MASK \ 60 HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_SRC_RING_HIGH_WATERMARK_BMSK 61 #define WCN6450_HOST_IS_SRC_RING_LOW_WATERMARK_MASK \ 62 HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_SRC_RING_LOW_WATERMARK_BMSK 63 #define WCN6450_HOST_IS_DST_RING_HIGH_WATERMARK_MASK \ 64 HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_DST_RING_HIGH_WATERMARK_BMSK 65 #define WCN6450_HOST_IS_DST_RING_LOW_WATERMARK_MASK \ 66 HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_DST_RING_LOW_WATERMARK_BMSK 67 #define WCN6450_HOST_IS_OFFSET (HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_ADDR \ 68 - WCN6450_CE0_BASE_ADDRESS) 69 #define WCN6450_MISC_IS_OFFSET (HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_ADDR \ 70 - WCN6450_CE0_BASE_ADDRESS) 71 #define WCN6450_HOST_IS_COPY_COMPLETE_MASK \ 72 HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_COPY_COMPLETE_BMSK 73 #define WCN6450_CE_COMMON_WRAPPER_BASE_ADDRESS \ 74 HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_REG_BASE 75 #define WCN6450_CE_COMMON_WRAPPER_INTERRUPT_SUMMARY_ADDRESS_OFFSET \ 76 (HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_HOST_INTERRUPT_SUMMARY_ADDR \ 77 - WCN6450_CE_COMMON_WRAPPER_BASE_ADDRESS) 78 #define WCN6450_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK \ 79 HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_HOST_INTERRUPT_SUMMARY_HOST_BMSK 80 #define WCN6450_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB \ 81 HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_HOST_INTERRUPT_SUMMARY_HOST_SHFT 82 #define WCN6450_CE_DDR_ADDRESS_FOR_RRI_LOW \ 83 (HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_LOW_ADDR \ 84 - WCN6450_CE_COMMON_WRAPPER_BASE_ADDRESS) 85 #define WCN6450_CE_DDR_ADDRESS_FOR_RRI_HIGH \ 86 (HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_HIGH_ADDR \ 87 - WCN6450_CE_COMMON_WRAPPER_BASE_ADDRESS) 88 #define WCN6450_HOST_IE_OFFSET (HWIO_HOST_SOC_A_WFSS_CE0_HOST_IE_ADDR \ 89 - WCN6450_CE0_BASE_ADDRESS) 90 #define WCN6450_HOST_IE_COPY_COMPLETE_MASK \ 91 HWIO_HOST_SOC_A_WFSS_CE0_HOST_IE_COPY_COMPLETE_BMSK 92 #define WCN6450_HOST_IE_SRC_BATCH_TIMER_MASK \ 93 HWIO_HOST_SOC_A_WFSS_CE0_HOST_IE_SRC_TIMER_BATCH_BMSK 94 #define WCN6450_HOST_IE_DST_BATCH_TIMER_MASK \ 95 HWIO_HOST_SOC_A_WFSS_CE0_HOST_IE_DST_TIMER_BATCH_BMSK 96 #define WCN6450_SR_BA_OFFSET (HWIO_HOST_SOC_A_WFSS_CE0_SR_BA_LOW_ADDR \ 97 - WCN6450_CE0_BASE_ADDRESS) 98 #define WCN6450_SR_BA_HIGH_OFFSET (HWIO_HOST_SOC_A_WFSS_CE0_SR_BA_HIGH_ADDR \ 99 - WCN6450_CE0_BASE_ADDRESS) 100 #define WCN6450_SR_SIZE_OFFSET (HWIO_HOST_SOC_A_WFSS_CE0_SR_SIZE_ADDR \ 101 - WCN6450_CE0_BASE_ADDRESS) 102 #define WCN6450_DR_BA_OFFSET (HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_LOW_ADDR \ 103 - WCN6450_CE0_BASE_ADDRESS) 104 #define WCN6450_DR_BA_HIGH_OFFSET (HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_HIGH_ADDR \ 105 - WCN6450_CE0_BASE_ADDRESS) 106 #define WCN6450_DR_SIZE_OFFSET (HWIO_HOST_SOC_A_WFSS_CE0_DR_SIZE_ADDR \ 107 - WCN6450_CE0_BASE_ADDRESS) 108 #define WCN6450_CE_CTRL1_OFFSET (HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_ADDR \ 109 - WCN6450_CE0_BASE_ADDRESS) 110 #define WCN6450_CE_CTRL1_DMAX_LENGTH_MASK \ 111 HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_DEST_MAX_LENGTH_BMSK 112 #define WCN6450_CE_CTRL1_DMAX_LENGTH_LSB \ 113 HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_DEST_MAX_LENGTH_SHFT 114 #define WCN6450_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK \ 115 HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_BMSK 116 #define WCN6450_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB \ 117 HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_SHFT 118 #define WCN6450_CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK \ 119 HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_DST_RING_BYTE_SWAP_EN_BMSK 120 #define WCN6450_CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB \ 121 HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_DST_RING_BYTE_SWAP_EN_SHFT 122 #define WCN6450_CE_CTRL1_IDX_UPD_EN_MASK \ 123 HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_IDX_UPD_EN_BMSK 124 #define WCN6450_CE_CMD_REGISTER_OFFSET (HWIO_HOST_SOC_A_WFSS_CE0_CE_CMD_ADDR \ 125 - WCN6450_CE0_BASE_ADDRESS) 126 #define WCN6450_CE_MSI_ADDRESS \ 127 (HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_ADDR_LOW_ADDR - \ 128 WCN6450_CE0_BASE_ADDRESS) 129 #define WCN6450_CE_MSI_ADDRESS_HIGH \ 130 (HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_ADDR_HIGH_ADDR - \ 131 WCN6450_CE0_BASE_ADDRESS) 132 #define WCN6450_CE_MSI_DATA (HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_DATA_ADDR \ 133 - WCN6450_CE0_BASE_ADDRESS) 134 #define WCN6450_CE_MSI_ENABLE_MASK \ 135 HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_HOST_MSI_EN_BMSK 136 #define WCN6450_CE_SRC_BATCH_TIMER_THRESH_MASK \ 137 HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 138 #define WCN6450_CE_SRC_BATCH_COUNTER_THRESH_MASK \ 139 HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 140 #define WCN6450_CE_SRC_BATCH_TIMER_THRESH_LSB \ 141 HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 142 #define WCN6450_CE_SRC_BATCH_COUNTER_THRESH_LSB \ 143 HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 144 #define WCN6450_CE_SRC_BATCH_TIMER_INT_SETUP_OFFSET \ 145 (HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_SETUP_ADDR \ 146 - WCN6450_CE0_BASE_ADDRESS) 147 #define WCN6450_CE_DST_BATCH_TIMER_THRESH_MASK \ 148 HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 149 #define WCN6450_CE_DST_BATCH_COUNTER_THRESH_MASK \ 150 HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 151 #define WCN6450_CE_DST_BATCH_TIMER_THRESH_LSB \ 152 HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 153 #define WCN6450_CE_DST_BATCH_COUNTER_THRESH_LSB \ 154 HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 155 #define WCN6450_CE_DST_BATCH_TIMER_INT_SETUP_OFFSET \ 156 (HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_SETUP_ADDR \ 157 - WCN6450_CE0_BASE_ADDRESS) 158 #define WCN6450_MISC_IE_OFFSET (HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_ADDR \ 159 - WCN6450_CE0_BASE_ADDRESS) 160 #define WCN6450_MISC_IS_AXI_ERR_MASK \ 161 HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_AXI_BUS_ERR_BMSK 162 #define WCN6450_MISC_IS_SRC_LEN_ERR_MASK \ 163 HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_SRC_LEN_ERR_BMSK 164 #define WCN6450_MISC_IS_DST_MAX_LEN_VIO_MASK \ 165 HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_DST_MAX_LEN_VIO_BMSK 166 #define WCN6450_MISC_IS_DST_RING_OVERFLOW_MASK \ 167 HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_DST_RING_OVERFLOW_BMSK 168 #define WCN6450_MISC_IS_SRC_RING_OVERFLOW_MASK \ 169 HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_SRC_RING_OVERFLOW_BMSK 170 171 #define WCN6450_MISC_IS_DST_ADDR_ERR_MASK MISSING 172 #define WCN6450_CE_WRAPPER_DEBUG_OFFSET MISSING 173 #define WCN6450_CE_WRAPPER_DEBUG_SEL_MSB MISSING 174 #define WCN6450_CE_WRAPPER_DEBUG_SEL_LSB MISSING 175 #define WCN6450_CE_WRAPPER_DEBUG_SEL_MASK MISSING 176 #define WCN6450_CE_DEBUG_OFFSET MISSING 177 #define WCN6450_CE_DEBUG_SEL_MSB MISSING 178 #define WCN6450_CE_DEBUG_SEL_LSB MISSING 179 #define WCN6450_CE_DEBUG_SEL_MASK MISSING 180 #define MISSING_FOR_WCN6450 MISSING 181 #define WCN6450_CE_COUNT 12 182 183 #define SHADOW_REG_VAL_START_OFFSET 0x00000504 184 #define SHADOW_REGISTER_VAL(x) ((SHADOW_REG_VAL_START_OFFSET) + (4 * (x))) 185 186 #define WCN6450_A_LOCAL_SHADOW_REG_VALUE_0 SHADOW_REGISTER_VAL(0) 187 #define WCN6450_A_LOCAL_SHADOW_REG_VALUE_1 SHADOW_REGISTER_VAL(1) 188 #define WCN6450_A_LOCAL_SHADOW_REG_VALUE_2 SHADOW_REGISTER_VAL(2) 189 #define WCN6450_A_LOCAL_SHADOW_REG_VALUE_3 SHADOW_REGISTER_VAL(3) 190 #define WCN6450_A_LOCAL_SHADOW_REG_VALUE_4 SHADOW_REGISTER_VAL(4) 191 #define WCN6450_A_LOCAL_SHADOW_REG_VALUE_5 SHADOW_REGISTER_VAL(5) 192 #define WCN6450_A_LOCAL_SHADOW_REG_VALUE_6 SHADOW_REGISTER_VAL(6) 193 #define WCN6450_A_LOCAL_SHADOW_REG_VALUE_7 SHADOW_REGISTER_VAL(7) 194 #define WCN6450_A_LOCAL_SHADOW_REG_VALUE_8 SHADOW_REGISTER_VAL(8) 195 #define WCN6450_A_LOCAL_SHADOW_REG_VALUE_9 SHADOW_REGISTER_VAL(9) 196 #define WCN6450_A_LOCAL_SHADOW_REG_VALUE_10 SHADOW_REGISTER_VAL(10) 197 #define WCN6450_A_LOCAL_SHADOW_REG_VALUE_11 SHADOW_REGISTER_VAL(11) 198 #define WCN6450_A_LOCAL_SHADOW_REG_VALUE_12 SHADOW_REGISTER_VAL(12) 199 #define WCN6450_A_LOCAL_SHADOW_REG_VALUE_13 SHADOW_REGISTER_VAL(13) 200 #define WCN6450_A_LOCAL_SHADOW_REG_VALUE_14 SHADOW_REGISTER_VAL(14) 201 #define WCN6450_A_LOCAL_SHADOW_REG_VALUE_15 SHADOW_REGISTER_VAL(15) 202 #define WCN6450_A_LOCAL_SHADOW_REG_VALUE_16 SHADOW_REGISTER_VAL(16) 203 #define WCN6450_A_LOCAL_SHADOW_REG_VALUE_17 SHADOW_REGISTER_VAL(17) 204 #define WCN6450_A_LOCAL_SHADOW_REG_VALUE_18 SHADOW_REGISTER_VAL(18) 205 #define WCN6450_A_LOCAL_SHADOW_REG_VALUE_19 SHADOW_REGISTER_VAL(19) 206 #define WCN6450_A_LOCAL_SHADOW_REG_VALUE_20 SHADOW_REGISTER_VAL(20) 207 #define WCN6450_A_LOCAL_SHADOW_REG_VALUE_21 SHADOW_REGISTER_VAL(21) 208 #define WCN6450_A_LOCAL_SHADOW_REG_VALUE_22 SHADOW_REGISTER_VAL(22) 209 #define WCN6450_A_LOCAL_SHADOW_REG_VALUE_23 SHADOW_REGISTER_VAL(23) 210 211 struct targetdef_s wcn6450_targetdef = { 212 .d_FW_INDICATOR_ADDRESS = MISSING_FOR_WCN6450, 213 .d_SR_WR_INDEX_ADDRESS = WCN6450_SR_WR_INDEX_OFFSET, 214 .d_DST_WATERMARK_ADDRESS = WCN6450_DST_WATERMARK_OFFSET, 215 .d_CE_COUNT = WCN6450_CE_COUNT, 216 }; 217 218 struct hostdef_s wcn6450_hostdef = { 219 .d_HOST_CE_COUNT = WCN6450_CE_COUNT, 220 .d_MUX_ID_MASK = 0xf000, 221 .d_TRANSACTION_ID_MASK = 0x0fff, 222 .d_DESC_DATA_FLAG_MASK = 0x7FFF1F00, 223 }; 224 225 struct ce_reg_def wcn6450_ce_targetdef = { 226 .d_DST_WR_INDEX_ADDRESS = WCN6450_DST_WR_INDEX_OFFSET, 227 .d_SRC_WATERMARK_ADDRESS = WCN6450_SRC_WATERMARK_OFFSET, 228 .d_SRC_WATERMARK_LOW_MASK = WCN6450_SRC_WATERMARK_LOW_MASK, 229 .d_SRC_WATERMARK_HIGH_MASK = WCN6450_SRC_WATERMARK_HIGH_MASK, 230 .d_DST_WATERMARK_LOW_MASK = WCN6450_DST_WATERMARK_LOW_MASK, 231 .d_DST_WATERMARK_HIGH_MASK = WCN6450_DST_WATERMARK_HIGH_MASK, 232 .d_CURRENT_SRRI_ADDRESS = WCN6450_CURRENT_SRRI_OFFSET, 233 .d_CURRENT_DRRI_ADDRESS = WCN6450_CURRENT_DRRI_OFFSET, 234 .d_HOST_IS_SRC_RING_HIGH_WATERMARK_MASK = 235 WCN6450_HOST_IS_SRC_RING_HIGH_WATERMARK_MASK, 236 .d_HOST_IS_SRC_RING_LOW_WATERMARK_MASK = 237 WCN6450_HOST_IS_SRC_RING_LOW_WATERMARK_MASK, 238 .d_HOST_IS_DST_RING_HIGH_WATERMARK_MASK = 239 WCN6450_HOST_IS_DST_RING_HIGH_WATERMARK_MASK, 240 .d_HOST_IS_DST_RING_LOW_WATERMARK_MASK = 241 WCN6450_HOST_IS_DST_RING_LOW_WATERMARK_MASK, 242 .d_HOST_IS_ADDRESS = WCN6450_HOST_IS_OFFSET, 243 .d_MISC_IS_ADDRESS = WCN6450_MISC_IS_OFFSET, 244 .d_HOST_IS_COPY_COMPLETE_MASK = WCN6450_HOST_IS_COPY_COMPLETE_MASK, 245 .d_CE_WRAPPER_BASE_ADDRESS = WCN6450_CE_COMMON_WRAPPER_BASE_ADDRESS, 246 .d_CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS = 247 WCN6450_CE_COMMON_WRAPPER_INTERRUPT_SUMMARY_ADDRESS_OFFSET, 248 .d_CE_DDR_ADDRESS_FOR_RRI_LOW = 249 WCN6450_CE_DDR_ADDRESS_FOR_RRI_LOW, 250 .d_CE_DDR_ADDRESS_FOR_RRI_HIGH = 251 WCN6450_CE_DDR_ADDRESS_FOR_RRI_HIGH, 252 .d_HOST_IE_ADDRESS = WCN6450_HOST_IE_OFFSET, 253 .d_HOST_IE_COPY_COMPLETE_MASK = WCN6450_HOST_IE_COPY_COMPLETE_MASK, 254 .d_HOST_IE_SRC_TIMER_BATCH_MASK = WCN6450_HOST_IE_SRC_BATCH_TIMER_MASK, 255 .d_HOST_IE_DST_TIMER_BATCH_MASK = WCN6450_HOST_IE_DST_BATCH_TIMER_MASK, 256 .d_SR_BA_ADDRESS = WCN6450_SR_BA_OFFSET, 257 .d_SR_BA_ADDRESS_HIGH = WCN6450_SR_BA_HIGH_OFFSET, 258 .d_SR_SIZE_ADDRESS = WCN6450_SR_SIZE_OFFSET, 259 .d_CE_CTRL1_ADDRESS = WCN6450_CE_CTRL1_OFFSET, 260 .d_CE_CTRL1_DMAX_LENGTH_MASK = WCN6450_CE_CTRL1_DMAX_LENGTH_MASK, 261 .d_DR_BA_ADDRESS = WCN6450_DR_BA_OFFSET, 262 .d_DR_BA_ADDRESS_HIGH = WCN6450_DR_BA_HIGH_OFFSET, 263 .d_DR_SIZE_ADDRESS = WCN6450_DR_SIZE_OFFSET, 264 .d_CE_CMD_REGISTER = WCN6450_CE_CMD_REGISTER_OFFSET, 265 .d_CE_MSI_ADDRESS = WCN6450_CE_MSI_ADDRESS, 266 .d_CE_MSI_ADDRESS_HIGH = WCN6450_CE_MSI_ADDRESS_HIGH, 267 .d_CE_MSI_DATA = WCN6450_CE_MSI_DATA, 268 .d_CE_MSI_ENABLE_BIT = WCN6450_CE_MSI_ENABLE_MASK, 269 .d_MISC_IE_ADDRESS = WCN6450_MISC_IE_OFFSET, 270 .d_MISC_IS_AXI_ERR_MASK = WCN6450_MISC_IS_AXI_ERR_MASK, 271 .d_MISC_IS_DST_ADDR_ERR_MASK = WCN6450_MISC_IS_DST_ADDR_ERR_MASK, 272 .d_MISC_IS_SRC_LEN_ERR_MASK = WCN6450_MISC_IS_SRC_LEN_ERR_MASK, 273 .d_MISC_IS_DST_MAX_LEN_VIO_MASK = WCN6450_MISC_IS_DST_MAX_LEN_VIO_MASK, 274 .d_MISC_IS_DST_RING_OVERFLOW_MASK = 275 WCN6450_MISC_IS_DST_RING_OVERFLOW_MASK, 276 .d_MISC_IS_SRC_RING_OVERFLOW_MASK = 277 WCN6450_MISC_IS_SRC_RING_OVERFLOW_MASK, 278 .d_SRC_WATERMARK_LOW_LSB = WCN6450_SRC_WATERMARK_LOW_LSB, 279 .d_SRC_WATERMARK_HIGH_LSB = WCN6450_SRC_WATERMARK_HIGH_LSB, 280 .d_DST_WATERMARK_LOW_LSB = WCN6450_DST_WATERMARK_LOW_LSB, 281 .d_DST_WATERMARK_HIGH_LSB = WCN6450_DST_WATERMARK_HIGH_LSB, 282 .d_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK = 283 WCN6450_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK, 284 .d_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB = 285 WCN6450_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB, 286 .d_CE_CTRL1_DMAX_LENGTH_LSB = WCN6450_CE_CTRL1_DMAX_LENGTH_LSB, 287 .d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK = 288 WCN6450_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK, 289 .d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK = 290 WCN6450_CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK, 291 .d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB = 292 WCN6450_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB, 293 .d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB = 294 WCN6450_CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB, 295 .d_CE_CTRL1_IDX_UPD_EN_MASK = WCN6450_CE_CTRL1_IDX_UPD_EN_MASK, 296 .d_CE_WRAPPER_DEBUG_OFFSET = WCN6450_CE_WRAPPER_DEBUG_OFFSET, 297 .d_CE_WRAPPER_DEBUG_SEL_MSB = WCN6450_CE_WRAPPER_DEBUG_SEL_MSB, 298 .d_CE_WRAPPER_DEBUG_SEL_LSB = WCN6450_CE_WRAPPER_DEBUG_SEL_LSB, 299 .d_CE_WRAPPER_DEBUG_SEL_MASK = WCN6450_CE_WRAPPER_DEBUG_SEL_MASK, 300 .d_CE_DEBUG_OFFSET = WCN6450_CE_DEBUG_OFFSET, 301 .d_CE_DEBUG_SEL_MSB = WCN6450_CE_DEBUG_SEL_MSB, 302 .d_CE_DEBUG_SEL_LSB = WCN6450_CE_DEBUG_SEL_LSB, 303 .d_CE_DEBUG_SEL_MASK = WCN6450_CE_DEBUG_SEL_MASK, 304 .d_CE0_BASE_ADDRESS = WCN6450_CE0_BASE_ADDRESS, 305 .d_CE1_BASE_ADDRESS = WCN6450_CE1_BASE_ADDRESS, 306 .d_A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_ENABLES = 307 MISSING_FOR_WCN6450, 308 .d_A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_STATUS = 309 MISSING_FOR_WCN6450, 310 .d_CE_SRC_BATCH_TIMER_THRESH_MASK = 311 WCN6450_CE_SRC_BATCH_TIMER_THRESH_MASK, 312 .d_CE_SRC_BATCH_COUNTER_THRESH_MASK = 313 WCN6450_CE_SRC_BATCH_COUNTER_THRESH_MASK, 314 .d_CE_SRC_BATCH_TIMER_THRESH_LSB = 315 WCN6450_CE_SRC_BATCH_TIMER_THRESH_LSB, 316 .d_CE_SRC_BATCH_COUNTER_THRESH_LSB = 317 WCN6450_CE_SRC_BATCH_COUNTER_THRESH_LSB, 318 .d_CE_DST_BATCH_TIMER_THRESH_MASK = 319 WCN6450_CE_DST_BATCH_TIMER_THRESH_MASK, 320 .d_CE_DST_BATCH_COUNTER_THRESH_MASK = 321 WCN6450_CE_DST_BATCH_COUNTER_THRESH_MASK, 322 .d_CE_DST_BATCH_TIMER_THRESH_LSB = 323 WCN6450_CE_DST_BATCH_TIMER_THRESH_LSB, 324 .d_CE_DST_BATCH_COUNTER_THRESH_LSB = 325 WCN6450_CE_DST_BATCH_COUNTER_THRESH_LSB, 326 .d_CE_SRC_BATCH_TIMER_INT_SETUP = 327 WCN6450_CE_SRC_BATCH_TIMER_INT_SETUP_OFFSET, 328 .d_CE_DST_BATCH_TIMER_INT_SETUP = 329 WCN6450_CE_DST_BATCH_TIMER_INT_SETUP_OFFSET, 330 }; 331 332 struct host_shadow_regs_s wcn6450_host_shadow_regs = { 333 .d_A_LOCAL_SHADOW_REG_VALUE_0 = 334 WCN6450_A_LOCAL_SHADOW_REG_VALUE_0, 335 .d_A_LOCAL_SHADOW_REG_VALUE_1 = 336 WCN6450_A_LOCAL_SHADOW_REG_VALUE_1, 337 .d_A_LOCAL_SHADOW_REG_VALUE_2 = 338 WCN6450_A_LOCAL_SHADOW_REG_VALUE_2, 339 .d_A_LOCAL_SHADOW_REG_VALUE_3 = 340 WCN6450_A_LOCAL_SHADOW_REG_VALUE_3, 341 .d_A_LOCAL_SHADOW_REG_VALUE_4 = 342 WCN6450_A_LOCAL_SHADOW_REG_VALUE_4, 343 .d_A_LOCAL_SHADOW_REG_VALUE_5 = 344 WCN6450_A_LOCAL_SHADOW_REG_VALUE_5, 345 .d_A_LOCAL_SHADOW_REG_VALUE_6 = 346 WCN6450_A_LOCAL_SHADOW_REG_VALUE_6, 347 .d_A_LOCAL_SHADOW_REG_VALUE_7 = 348 WCN6450_A_LOCAL_SHADOW_REG_VALUE_7, 349 .d_A_LOCAL_SHADOW_REG_VALUE_8 = 350 WCN6450_A_LOCAL_SHADOW_REG_VALUE_8, 351 .d_A_LOCAL_SHADOW_REG_VALUE_9 = 352 WCN6450_A_LOCAL_SHADOW_REG_VALUE_9, 353 .d_A_LOCAL_SHADOW_REG_VALUE_10 = 354 WCN6450_A_LOCAL_SHADOW_REG_VALUE_10, 355 .d_A_LOCAL_SHADOW_REG_VALUE_11 = 356 WCN6450_A_LOCAL_SHADOW_REG_VALUE_11, 357 .d_A_LOCAL_SHADOW_REG_VALUE_12 = 358 WCN6450_A_LOCAL_SHADOW_REG_VALUE_12, 359 .d_A_LOCAL_SHADOW_REG_VALUE_13 = 360 WCN6450_A_LOCAL_SHADOW_REG_VALUE_13, 361 .d_A_LOCAL_SHADOW_REG_VALUE_14 = 362 WCN6450_A_LOCAL_SHADOW_REG_VALUE_14, 363 .d_A_LOCAL_SHADOW_REG_VALUE_15 = 364 WCN6450_A_LOCAL_SHADOW_REG_VALUE_15, 365 .d_A_LOCAL_SHADOW_REG_VALUE_16 = 366 WCN6450_A_LOCAL_SHADOW_REG_VALUE_16, 367 .d_A_LOCAL_SHADOW_REG_VALUE_17 = 368 WCN6450_A_LOCAL_SHADOW_REG_VALUE_17, 369 .d_A_LOCAL_SHADOW_REG_VALUE_18 = 370 WCN6450_A_LOCAL_SHADOW_REG_VALUE_18, 371 .d_A_LOCAL_SHADOW_REG_VALUE_19 = 372 WCN6450_A_LOCAL_SHADOW_REG_VALUE_19, 373 .d_A_LOCAL_SHADOW_REG_VALUE_20 = 374 WCN6450_A_LOCAL_SHADOW_REG_VALUE_20, 375 .d_A_LOCAL_SHADOW_REG_VALUE_21 = 376 WCN6450_A_LOCAL_SHADOW_REG_VALUE_21, 377 .d_A_LOCAL_SHADOW_REG_VALUE_22 = 378 WCN6450_A_LOCAL_SHADOW_REG_VALUE_22, 379 .d_A_LOCAL_SHADOW_REG_VALUE_23 = 380 WCN6450_A_LOCAL_SHADOW_REG_VALUE_23, 381 }; 382 #endif 383