1 // SPDX-License-Identifier: MIT 2 // 3 // Copyright 2024 Advanced Micro Devices, Inc. 4 5 #ifndef __DCN401_CLK_MGR_H_ 6 #define __DCN401_CLK_MGR_H_ 7 8 #define DCN401_CLK_MGR_MAX_SEQUENCE_SIZE 30 9 10 union dcn401_clk_mgr_block_sequence_params { 11 struct { 12 /* inputs */ 13 uint32_t num_displays; 14 } update_num_displays_params; 15 struct { 16 /* inputs */ 17 uint32_t ppclk; 18 uint16_t freq_mhz; 19 /* outputs */ 20 uint32_t *response; 21 } update_hardmin_params; 22 struct { 23 /* inputs */ 24 uint32_t ppclk; 25 int freq_khz; 26 /* outputs */ 27 uint32_t *response; 28 } update_hardmin_optimized_params; 29 struct { 30 /* inputs */ 31 uint16_t uclk_mhz; 32 uint16_t fclk_mhz; 33 } update_idle_hardmin_params; 34 struct { 35 /* inputs */ 36 uint16_t freq_mhz; 37 } update_deep_sleep_dcfclk_params; 38 struct { 39 /* inputs */ 40 bool support; 41 } update_pstate_support_params; 42 struct { 43 /* inputs */ 44 unsigned int num_ways; 45 } update_cab_for_uclk_params; 46 struct { 47 /* inputs */ 48 bool enable; 49 } update_wait_for_dmub_ack_params; 50 struct { 51 /* inputs */ 52 bool mod_drr_for_pstate; 53 } indicate_drr_status_params; 54 struct { 55 /* inputs */ 56 struct dc_state *context; 57 int *ref_dppclk_khz; 58 bool safe_to_lower; 59 } update_dppclk_dto_params; 60 struct { 61 /* inputs */ 62 struct dc_state *context; 63 int *ref_dtbclk_khz; 64 } update_dtbclk_dto_params; 65 struct { 66 /* inputs */ 67 struct dc_state *context; 68 } update_dentist_params; 69 struct { 70 /* inputs */ 71 struct dmcu *dmcu; 72 unsigned int wait; 73 } update_psr_wait_loop_params; 74 }; 75 76 enum dcn401_clk_mgr_block_sequence_func { 77 CLK_MGR401_READ_CLOCKS_FROM_DENTIST, 78 CLK_MGR401_UPDATE_NUM_DISPLAYS, 79 CLK_MGR401_UPDATE_HARDMIN_PPCLK, 80 CLK_MGR401_UPDATE_HARDMIN_PPCLK_OPTIMIZED, 81 CLK_MGR401_UPDATE_ACTIVE_HARDMINS, 82 CLK_MGR401_UPDATE_IDLE_HARDMINS, 83 CLK_MGR401_UPDATE_DEEP_SLEEP_DCFCLK, 84 CLK_MGR401_UPDATE_FCLK_PSTATE_SUPPORT, 85 CLK_MGR401_UPDATE_UCLK_PSTATE_SUPPORT, 86 CLK_MGR401_UPDATE_CAB_FOR_UCLK, 87 CLK_MGR401_UPDATE_WAIT_FOR_DMUB_ACK, 88 CLK_MGR401_INDICATE_DRR_STATUS, 89 CLK_MGR401_UPDATE_DPPCLK_DTO, 90 CLK_MGR401_UPDATE_DTBCLK_DTO, 91 CLK_MGR401_UPDATE_DENTIST, 92 CLK_MGR401_UPDATE_PSR_WAIT_LOOP, 93 }; 94 95 struct dcn401_clk_mgr_block_sequence { 96 union dcn401_clk_mgr_block_sequence_params params; 97 enum dcn401_clk_mgr_block_sequence_func func; 98 }; 99 100 struct dcn401_clk_mgr { 101 struct clk_mgr_internal base; 102 103 struct dcn401_clk_mgr_block_sequence block_sequence[DCN401_CLK_MGR_MAX_SEQUENCE_SIZE]; 104 }; 105 106 void dcn401_init_clocks(struct clk_mgr *clk_mgr_base); 107 108 struct clk_mgr_internal *dcn401_clk_mgr_construct(struct dc_context *ctx, 109 struct dccg *dccg); 110 111 void dcn401_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr); 112 113 #endif /* __DCN401_CLK_MGR_H_ */ 114