1 /* 2 * Copyright (c) 2017-2021 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /** 21 * @file htt_stats.h 22 * 23 * @details the public header file of HTT STATS 24 */ 25 #ifndef __HTT_STATS_H__ 26 #define __HTT_STATS_H__ 27 28 #include <htt_deps.h> /* A_UINT32 */ 29 #include <htt_common.h> 30 #include <htt.h> /* HTT stats TLV struct def and tag defs */ 31 32 33 /* HTT_STATS_VAR_LEN_ARRAY1: 34 * This macro is for converting the definition of existing variable-length 35 * arrays within TLV structs of the form "type name[1];" to use the form 36 * "type name[];" while ensuring that the length of the TLV struct is 37 * unmodified by the conversion. 38 * In general, any new variable-length structs should simply use 39 * "type name[];" directly, rather than using HTT_STATS_VAR_LEN_ARRAY1. 40 * However, if there's a legitimate reason to make the new variable-length 41 * struct appear to not have a variable length, HTT_STATS_VAR_LEN_ARRAY1 42 * can be used for this purpose. 43 */ 44 45 #if defined(ATH_TARGET) || defined(__WINDOWS__) 46 #define HTT_STATS_VAR_LEN_ARRAY1(type, name) type name[1] 47 #else 48 /* 49 * Certain build settings of the Linux kernel don't allow zero-element 50 * arrays, and C++ doesn't allow zero-length empty structs. 51 * Confirm that there's no build that combines kernel with C++. 52 */ 53 #ifdef __cplusplus 54 #error unsupported combination of kernel and C plus plus 55 #endif 56 #define HTT_STATS_DUMMY_ZERO_LEN_FIELD struct {} dummy_zero_len_field 57 58 #define HTT_STATS_VAR_LEN_ARRAY1(type, name) \ 59 union { \ 60 type name ## __first_elem; \ 61 struct { \ 62 HTT_STATS_DUMMY_ZERO_LEN_FIELD; \ 63 type name[]; \ 64 }; \ 65 } 66 #endif 67 68 69 /** 70 * htt_dbg_ext_stats_type - 71 * The base structure for each of the stats_type is only for reference 72 * Host should use this information to know the type of TLVs to expect 73 * for a particular stats type. 74 * 75 * Max supported stats :- 256. 76 */ 77 enum htt_dbg_ext_stats_type { 78 /** HTT_DBG_EXT_STATS_RESET 79 * PARAM: 80 * - config_param0 : start_offset (stats type) 81 * - config_param1 : stats bmask from start offset 82 * - config_param2 : stats bmask from start offset + 32 83 * - config_param3 : stats bmask from start offset + 64 84 * RESP MSG: 85 * - No response sent. 86 */ 87 HTT_DBG_EXT_STATS_RESET = 0, 88 89 /** HTT_DBG_EXT_STATS_PDEV_TX 90 * PARAMS: 91 * - No Params 92 * RESP MSG: 93 * - htt_tx_pdev_stats_t 94 */ 95 HTT_DBG_EXT_STATS_PDEV_TX = 1, 96 97 /** HTT_DBG_EXT_STATS_PDEV_RX 98 * PARAMS: 99 * - No Params 100 * RESP MSG: 101 * - htt_rx_pdev_stats_t 102 */ 103 HTT_DBG_EXT_STATS_PDEV_RX = 2, 104 105 /** HTT_DBG_EXT_STATS_PDEV_TX_HWQ 106 * PARAMS: 107 * - config_param0: [Bit31: Bit0] HWQ mask 108 * RESP MSG: 109 * - htt_tx_hwq_stats_t 110 */ 111 HTT_DBG_EXT_STATS_PDEV_TX_HWQ = 3, 112 113 /** HTT_DBG_EXT_STATS_PDEV_TX_SCHED 114 * PARAMS: 115 * - config_param0: [Bit31: Bit0] TXQ mask 116 * RESP MSG: 117 * - htt_stats_tx_sched_t 118 */ 119 HTT_DBG_EXT_STATS_PDEV_TX_SCHED = 4, 120 121 /** HTT_DBG_EXT_STATS_PDEV_ERROR 122 * PARAMS: 123 * - No Params 124 * RESP MSG: 125 * - htt_hw_err_stats_t 126 */ 127 HTT_DBG_EXT_STATS_PDEV_ERROR = 5, 128 129 /** HTT_DBG_EXT_STATS_PDEV_TQM 130 * PARAMS: 131 * - No Params 132 * RESP MSG: 133 * - htt_tx_tqm_pdev_stats_t 134 */ 135 HTT_DBG_EXT_STATS_PDEV_TQM = 6, 136 137 /** HTT_DBG_EXT_STATS_TQM_CMDQ 138 * PARAMS: 139 * - config_param0: 140 * [Bit15: Bit0 ] cmdq id :if 0xFFFF print all cmdq's 141 * [Bit31: Bit16] reserved 142 * RESP MSG: 143 * - htt_tx_tqm_cmdq_stats_t 144 */ 145 HTT_DBG_EXT_STATS_TQM_CMDQ = 7, 146 147 /** HTT_DBG_EXT_STATS_TX_DE_INFO 148 * PARAMS: 149 * - No Params 150 * RESP MSG: 151 * - htt_tx_de_stats_t 152 */ 153 HTT_DBG_EXT_STATS_TX_DE_INFO = 8, 154 155 /** HTT_DBG_EXT_STATS_PDEV_TX_RATE 156 * PARAMS: 157 * - No Params 158 * RESP MSG: 159 * - htt_tx_pdev_rate_stats_t 160 */ 161 HTT_DBG_EXT_STATS_PDEV_TX_RATE = 9, 162 163 /** HTT_DBG_EXT_STATS_PDEV_RX_RATE 164 * PARAMS: 165 * - No Params 166 * RESP MSG: 167 * - htt_rx_pdev_rate_stats_t 168 */ 169 HTT_DBG_EXT_STATS_PDEV_RX_RATE = 10, 170 171 /** HTT_DBG_EXT_STATS_PEER_INFO 172 * PARAMS: 173 * - config_param0: 174 * [Bit0] - [0] for sw_peer_id, [1] for mac_addr based request 175 * [Bit15 : Bit 1] htt_peer_stats_req_mode_t 176 * [Bit31 : Bit16] sw_peer_id 177 * config_param1: 178 * peer_stats_req_type_mask:32 (enum htt_peer_stats_tlv_enum) 179 * 0 bit htt_peer_stats_cmn_tlv 180 * 1 bit htt_peer_details_tlv 181 * 2 bit htt_tx_peer_rate_stats_tlv 182 * 3 bit htt_rx_peer_rate_stats_tlv 183 * 4 bit htt_tx_tid_stats_tlv/htt_tx_tid_stats_v1_tlv 184 * 5 bit htt_rx_tid_stats_tlv 185 * 6 bit htt_msdu_flow_stats_tlv 186 * 7 bit htt_peer_sched_stats_tlv 187 * 8 bit htt_peer_ax_ofdma_stats_tlv 188 * 9 bit htt_peer_be_ofdma_stats_tlv 189 * - config_param2: [Bit31 : Bit0] mac_addr31to0 190 * - config_param3: [Bit15 : Bit0] mac_addr47to32 191 * [Bit 16] If this bit is set, reset per peer stats 192 * of corresponding tlv indicated by config 193 * param 1. 194 * HTT_DBG_EXT_PEER_STATS_RESET_GET will be 195 * used to get this bit position. 196 * WMI_SERVICE_PER_PEER_HTT_STATS_RESET 197 * indicates that FW supports per peer HTT 198 * stats reset. 199 * [Bit31 : Bit17] reserved 200 * RESP MSG: 201 * - htt_peer_stats_t 202 */ 203 HTT_DBG_EXT_STATS_PEER_INFO = 11, 204 205 /** HTT_DBG_EXT_STATS_TX_SELFGEN_INFO 206 * PARAMS: 207 * - No Params 208 * RESP MSG: 209 * - htt_tx_pdev_selfgen_stats_t 210 */ 211 HTT_DBG_EXT_STATS_TX_SELFGEN_INFO = 12, 212 213 /** HTT_DBG_EXT_STATS_TX_MU_HWQ 214 * PARAMS: 215 * - config_param0: [Bit31: Bit0] HWQ mask 216 * RESP MSG: 217 * - htt_tx_hwq_mu_mimo_stats_t 218 */ 219 HTT_DBG_EXT_STATS_TX_MU_HWQ = 13, 220 221 /** HTT_DBG_EXT_STATS_RING_IF_INFO 222 * PARAMS: 223 * - config_param0: 224 * [Bit15: Bit0 ] ring id :if 0xFFFF print all rings 225 * [Bit31: Bit16] reserved 226 * RESP MSG: 227 * - htt_ring_if_stats_t 228 */ 229 HTT_DBG_EXT_STATS_RING_IF_INFO = 14, 230 231 /** HTT_DBG_EXT_STATS_SRNG_INFO 232 * PARAMS: 233 * - config_param0: 234 * [Bit15: Bit0 ] ring id :if 0xFFFF print all rings 235 * [Bit31: Bit16] reserved 236 * - No Params 237 * RESP MSG: 238 * - htt_sring_stats_t 239 */ 240 HTT_DBG_EXT_STATS_SRNG_INFO = 15, 241 242 /** HTT_DBG_EXT_STATS_SFM_INFO 243 * PARAMS: 244 * - No Params 245 * RESP MSG: 246 * - htt_sfm_stats_t 247 */ 248 HTT_DBG_EXT_STATS_SFM_INFO = 16, 249 250 /** HTT_DBG_EXT_STATS_PDEV_TX_MU 251 * PARAMS: 252 * - No Params 253 * RESP MSG: 254 * - htt_tx_pdev_mu_mimo_stats_t 255 */ 256 HTT_DBG_EXT_STATS_PDEV_TX_MU = 17, 257 258 /** HTT_DBG_EXT_STATS_ACTIVE_PEERS_LIST 259 * PARAMS: 260 * - config_param0: 261 * [Bit7 : Bit0] vdev_id:8 262 * note:0xFF to get all active peers based on pdev_mask. 263 * [Bit31 : Bit8] rsvd:24 264 * RESP MSG: 265 * - htt_active_peer_details_list_t 266 */ 267 HTT_DBG_EXT_STATS_ACTIVE_PEERS_LIST = 18, 268 269 /** HTT_DBG_EXT_STATS_PDEV_CCA_STATS 270 * PARAMS: 271 * - config_param0: 272 * [Bit0] - Clear bit0 to read 1sec,100ms & cumulative CCA stats. 273 * Set bit0 to 1 to read 1sec interval histogram. 274 * [Bit1] - 100ms interval histogram 275 * [Bit3] - Cumulative CCA stats 276 * RESP MSG: 277 * - htt_pdev_cca_stats_t 278 */ 279 HTT_DBG_EXT_STATS_PDEV_CCA_STATS = 19, 280 281 /** HTT_DBG_EXT_STATS_TWT_SESSIONS 282 * PARAMS: 283 * - config_param0: 284 * No params 285 * RESP MSG: 286 * - htt_pdev_twt_sessions_stats_t 287 */ 288 HTT_DBG_EXT_STATS_TWT_SESSIONS = 20, 289 290 /** HTT_DBG_EXT_STATS_REO_CNTS 291 * PARAMS: 292 * - config_param0: 293 * No params 294 * RESP MSG: 295 * - htt_soc_reo_resource_stats_t 296 */ 297 HTT_DBG_EXT_STATS_REO_RESOURCE_STATS = 21, 298 299 /** HTT_DBG_EXT_STATS_TX_SOUNDING_INFO 300 * PARAMS: 301 * - config_param0: 302 * [Bit0] vdev_id_set:1 303 * set to 1 if vdev_id is set and vdev stats are requested. 304 * set to 0 if pdev_stats sounding stats are requested. 305 * [Bit8 : Bit1] vdev_id:8 306 * note:0xFF to get all active vdevs based on pdev_mask. 307 * [Bit31 : Bit9] rsvd:22 308 * 309 * RESP MSG: 310 * - htt_tx_sounding_stats_t 311 */ 312 HTT_DBG_EXT_STATS_TX_SOUNDING_INFO = 22, 313 314 /** HTT_DBG_EXT_STATS_PDEV_OBSS_PD_STATS 315 * PARAMS: 316 * - config_param0: 317 * No params 318 * RESP MSG: 319 * - htt_pdev_obss_pd_stats_t 320 */ 321 HTT_DBG_EXT_STATS_PDEV_OBSS_PD_STATS = 23, 322 323 /** HTT_DBG_EXT_STATS_RING_BACKPRESSURE_STATS 324 * PARAMS: 325 * - config_param0: 326 * No params 327 * RESP MSG: 328 * - htt_stats_ring_backpressure_stats_t 329 */ 330 HTT_DBG_EXT_STATS_RING_BACKPRESSURE_STATS = 24, 331 332 /** HTT_DBG_EXT_STATS_LATENCY_PROF_STATS 333 * PARAMS: 334 * 335 * RESP MSG: 336 * - htt_latency_prof_stats_tlv showing latency profile stats for 337 * high-level (pdev or vdev level) events such as tx/rx suspend 338 * or resume, or UMAC, DMAC, or PMAC reset. 339 */ 340 HTT_DBG_EXT_STATS_LATENCY_PROF_STATS = 25, 341 342 /** HTT_DBG_EXT_STATS_PDEV_UL_TRIGGER 343 * PARAMS: 344 * - No Params 345 * RESP MSG: 346 * - htt_rx_pdev_ul_trig_stats_t 347 */ 348 HTT_DBG_EXT_STATS_PDEV_UL_TRIG_STATS = 26, 349 350 /** HTT_DBG_EXT_STATS_PDEV_UL_MUMIMO_TRIG_STATS = 27 351 * PARAMS: 352 * - No Params 353 * RESP MSG: 354 * - htt_rx_pdev_ul_mumimo_trig_stats_t 355 */ 356 HTT_DBG_EXT_STATS_PDEV_UL_MUMIMO_TRIG_STATS = 27, 357 358 /** HTT_DBG_EXT_STATS_FSE_RX 359 * PARAMS: 360 * - No Params 361 * RESP MSG: 362 * - htt_rx_fse_stats_t 363 */ 364 HTT_DBG_EXT_STATS_FSE_RX = 28, 365 366 /** HTT_DBG_EXT_PEER_CTRL_PATH_TXRX_STATS 367 * PARAMS: 368 * - config_param0: [Bit0] : [1] for mac_addr based request 369 * - config_param1: [Bit31 : Bit0] mac_addr31to0 370 * - config_param2: [Bit15 : Bit0] mac_addr47to32 371 * RESP MSG: 372 * - htt_ctrl_path_txrx_stats_t 373 */ 374 HTT_DBG_EXT_PEER_CTRL_PATH_TXRX_STATS = 29, 375 376 /** HTT_DBG_EXT_STATS_PDEV_RX_RATE_EXT 377 * PARAMS: 378 * - No Params 379 * RESP MSG: 380 * - htt_rx_pdev_rate_ext_stats_t 381 */ 382 HTT_DBG_EXT_STATS_PDEV_RX_RATE_EXT = 30, 383 384 /** HTT_DBG_EXT_STATS_PDEV_TX_RATE_TXBF 385 * PARAMS: 386 * - No Params 387 * RESP MSG: 388 * - htt_tx_pdev_txbf_rate_stats_t 389 */ 390 HTT_DBG_EXT_STATS_PDEV_TX_RATE_TXBF = 31, 391 392 /** HTT_DBG_EXT_STATS_TXBF_OFDMA 393 */ 394 HTT_DBG_EXT_STATS_TXBF_OFDMA = 32, 395 396 /** HTT_DBG_EXT_STA_11AX_UL_STATS 397 * PARAMS: 398 * - No Params 399 * RESP MSG: 400 * - htt_sta_11ax_ul_stats 401 */ 402 HTT_DBG_EXT_STA_11AX_UL_STATS = 33, 403 404 /** HTT_DBG_EXT_VDEV_RTT_RESP_STATS 405 * PARAMS: 406 * - config_param0: 407 * [Bit7 : Bit0] vdev_id:8 408 * [Bit31 : Bit8] rsvd:24 409 * RESP MSG: 410 * - 411 */ 412 HTT_DBG_EXT_VDEV_RTT_RESP_STATS = 34, 413 414 /** HTT_DBG_EXT_PKTLOG_AND_HTT_RING_STATS 415 * PARAMS: 416 * - No Params 417 * RESP MSG: 418 * - htt_pktlog_and_htt_ring_stats_t 419 */ 420 HTT_DBG_EXT_PKTLOG_AND_HTT_RING_STATS = 35, 421 422 /** HTT_DBG_EXT_STATS_DLPAGER_STATS 423 * PARAMS: 424 * 425 * RESP MSG: 426 * - htt_dlpager_stats_t 427 */ 428 HTT_DBG_EXT_STATS_DLPAGER_STATS = 36, 429 430 /** HTT_DBG_EXT_PHY_COUNTERS_AND_PHY_STATS 431 * PARAMS: 432 * - No Params 433 * RESP MSG: 434 * - htt_phy_counters_and_phy_stats_t 435 */ 436 HTT_DBG_EXT_PHY_COUNTERS_AND_PHY_STATS = 37, 437 438 /** HTT_DBG_EXT_VDEVS_TXRX_STATS 439 * PARAMS: 440 * - No Params 441 * RESP MSG: 442 * - htt_vdevs_txrx_stats_t 443 */ 444 HTT_DBG_EXT_VDEVS_TXRX_STATS = 38, 445 446 HTT_DBG_EXT_VDEV_RTT_INITIATOR_STATS = 39, 447 448 /** HTT_DBG_EXT_PDEV_PER_STATS 449 * PARAMS: 450 * - No Params 451 * RESP MSG: 452 * - htt_tx_pdev_per_stats_t 453 */ 454 HTT_DBG_EXT_PDEV_PER_STATS = 40, 455 456 HTT_DBG_EXT_AST_ENTRIES = 41, 457 458 /** HTT_DBG_EXT_RX_RING_STATS 459 * PARAMS: 460 * - No Params 461 * RESP MSG: 462 * - htt_rx_fw_ring_stats_tlv_v 463 */ 464 HTT_DBG_EXT_RX_RING_STATS = 42, 465 466 /** HTT_STRM_GEN_MPDUS_STATS, HTT_STRM_GEN_MPDUS_DETAILS_STATS 467 * PARAMS: 468 * - No params 469 * RESP MSG: HTT_T2H STREAMING_STATS_IND (not EXT_STATS_CONF) 470 * - HTT_STRM_GEN_MPDUS_STATS: 471 * htt_stats_strm_gen_mpdus_tlv_t 472 * - HTT_STRM_GEN_MPDUS_DETAILS_STATS: 473 * htt_stats_strm_gen_mpdus_details_tlv_t 474 */ 475 HTT_STRM_GEN_MPDUS_STATS = 43, 476 HTT_STRM_GEN_MPDUS_DETAILS_STATS = 44, 477 478 /** HTT_DBG_SOC_ERROR_STATS 479 * PARAMS: 480 * - No Params 481 * RESP MSG: 482 * - htt_dmac_reset_stats_tlv 483 */ 484 HTT_DBG_SOC_ERROR_STATS = 45, 485 486 /** HTT_DBG_PDEV_PUNCTURE_STATS 487 * PARAMS: 488 * - param 0: enum from htt_tx_pdev_puncture_stats_upload_t, indicating 489 * the stats to upload 490 * RESP MSG: 491 * - one or more htt_pdev_puncture_stats_tlv, depending on param 0 492 */ 493 HTT_DBG_PDEV_PUNCTURE_STATS = 46, 494 495 /** HTT_DBG_EXT_STATS_ML_PEERS_INFO 496 * PARAMS: 497 * - param 0: 498 * Bit 0 -> HTT_ML_PEER_DETAILS_TLV always enabled by default 499 * Bit 1 -> HTT_ML_PEER_EXT_DETAILS_TLV will be uploaded when 500 * this bit is set 501 * Bit 2 -> HTT_ML_LINK_INFO_TLV will be uploaded when this bit is set 502 * RESP MSG: 503 * - htt_ml_peer_stats_t 504 */ 505 HTT_DBG_EXT_STATS_ML_PEERS_INFO = 47, 506 507 /** HTT_DBG_ODD_MANDATORY_STATS 508 * params: 509 * None 510 * Response MSG: 511 * htt_odd_mandatory_pdev_stats_tlv 512 */ 513 HTT_DBG_ODD_MANDATORY_STATS = 48, 514 515 /** HTT_DBG_PDEV_SCHED_ALGO_STATS 516 * PARAMS: 517 * - No Params 518 * RESP MSG: 519 * - htt_pdev_sched_algo_ofdma_stats_tlv 520 */ 521 HTT_DBG_PDEV_SCHED_ALGO_STATS = 49, 522 523 /** HTT_DBG_ODD_MANDATORY_MUMIMO_STATS 524 * params: 525 * None 526 * Response MSG: 527 * htt_odd_mandatory_mumimo_pdev_stats_tlv 528 */ 529 HTT_DBG_ODD_MANDATORY_MUMIMO_STATS = 50, 530 /** HTT_DBG_ODD_MANDATORY_MUOFDMA_STATS 531 * params: 532 * None 533 * Response MSG: 534 * htt_odd_mandatory_muofdma_pdev_stats_tlv 535 */ 536 HTT_DBG_ODD_MANDATORY_MUOFDMA_STATS = 51, 537 538 /** HTT_DBG_EXT_PHY_PROF_CAL_STATS 539 * params: 540 * None 541 * Response MSG: 542 * htt_stats_latency_prof_cal_data_tlv 543 */ 544 HTT_DBG_EXT_PHY_PROF_CAL_STATS = 52, 545 546 /** HTT_DBG_EXT_STATS_PDEV_BW_MGR 547 * PARAMS: 548 * - No Params 549 * RESP MSG: 550 * - htt_pdev_bw_mgr_stats_t 551 */ 552 HTT_DBG_EXT_STATS_PDEV_BW_MGR = 53, 553 554 /** HTT_DBG_PDEV_MBSSID_CTRL_FRAME_STATS 555 * PARAMS: 556 * - No Params 557 * RESP MSG: 558 * - htt_pdev_mbssid_ctrl_frame_stats 559 */ 560 HTT_DBG_PDEV_MBSSID_CTRL_FRAME_STATS = 54, 561 562 /** HTT_DBG_SOC_SSR_STATS 563 * Used for non-MLO UMAC recovery stats. 564 * PARAMS: 565 * - No Params 566 * RESP MSG: 567 * - htt_umac_ssr_stats_tlv 568 */ 569 HTT_DBG_SOC_SSR_STATS = 55, 570 571 /** HTT_DBG_MLO_UMAC_SSR_STATS 572 * Used for MLO UMAC recovery stats. 573 * PARAMS: 574 * - No Params 575 * RESP MSG: 576 * - htt_mlo_umac_ssr_stats_tlv 577 */ 578 HTT_DBG_MLO_UMAC_SSR_STATS = 56, 579 580 /** HTT_DBG_PDEV_TDMA_STATS 581 * PARAMS: 582 * - No Params 583 * RESP MSG: 584 * - htt_pdev_tdma_stats_tlv 585 */ 586 HTT_DBG_PDEV_TDMA_STATS = 57, 587 588 /** HTT_DBG_CODEL_STATS 589 * PARAMS: 590 * - No Params 591 * RESP MSG: 592 * - htt_codel_svc_class_stats_tlv 593 * - htt_codel_msduq_stats_tlv 594 */ 595 HTT_DBG_CODEL_STATS = 58, 596 597 /** HTT_DBG_ODD_PDEV_BE_TX_MU_OFDMA_STATS 598 * PARAMS: 599 * - No Params 600 * RESP MSG: 601 * - htt_tx_pdev_mpdu_stats_tlv 602 */ 603 HTT_DBG_ODD_PDEV_BE_TX_MU_OFDMA_STATS = 59, 604 605 /** HTT_DBG_EXT_STATS_PDEV_UL_TRIGGER 606 * PARAMS: 607 * - No Params 608 * RESP MSG: 609 * - htt_rx_pdev_be_ul_ofdma_user_stats_tlv 610 */ 611 HTT_DBG_ODD_UL_BE_OFDMA_STATS = 60, 612 613 /** HTT_DBG_ODD_BE_TXBF_OFDMA_STATS 614 */ 615 HTT_DBG_ODD_BE_TXBF_OFDMA_STATS = 61, 616 617 /** HTT_DBG_ODD_STATS_PDEV_BE_UL_MUMIMO_TRIG_STATS 618 * PARAMS: 619 * - No Params 620 * RESP MSG: 621 * - htt_rx_pdev_be_ul_ofdma_user_stats_tlv 622 */ 623 HTT_DBG_ODD_STATS_PDEV_BE_UL_MUMIMO_TRIG_STATS = 62, 624 625 /** HTT_DBG_MLO_SCHED_STATS 626 * PARAMS: 627 * - No Params 628 * RESP MSG: 629 * - htt_pdev_mlo_sched_stats_tlv 630 */ 631 HTT_DBG_MLO_SCHED_STATS = 63, 632 633 /** HTT_DBG_PDEV_MLO_IPC_STATS 634 * PARAMS: 635 * - No Params 636 * RESP MSG: 637 * - htt_pdev_mlo_ipc_stats_tlv 638 */ 639 HTT_DBG_PDEV_MLO_IPC_STATS = 64, 640 641 /** HTT_DBG_EXT_PDEV_RTT_RESP_STATS 642 * PARAMS: 643 * - No Params 644 * RESP MSG: 645 * - htt_stats_pdev_rtt_resp_stats_tlv 646 * - htt_stats_pdev_rtt_hw_stats_tlv 647 * - htt_stats_pdev_rtt_tbr_selfgen_queued_stats_tlv 648 * - htt_stats_pdev_rtt_tbr_cmd_result_stats_tlv 649 */ 650 HTT_DBG_EXT_PDEV_RTT_RESP_STATS = 65, 651 652 /** HTT_DBG_EXT_PDEV_RTT_INITIATOR_STATS 653 * PARAMS: 654 * - No Params 655 * RESP MSG: 656 * - htt_stats_pdev_rtt_init_stats_tlv 657 * - htt_stats_pdev_rtt_hw_stats_tlv 658 */ 659 HTT_DBG_EXT_PDEV_RTT_INITIATOR_STATS = 66, 660 661 /** HTT_DBG_EXT_STATS_LATENCY_PROF_STATS_LO 662 * PARAMS: 663 * 664 * RESP MSG: 665 * - htt_latency_prof_stats_tlv showing latency profile stats for 666 * finer-grained events than HTT_DBG_EXT_STATS_LATENCY_PROF_STATS, 667 * such as individual steps within a larger pdev or vdev event. 668 */ 669 HTT_DBG_EXT_STATS_LATENCY_PROF_STATS_LO = 67, 670 671 /** HTT_DBG_GTX_STATS 672 * PARAMS: 673 * - No Params 674 * RESP MSG: 675 * - htt_pdev_gtx_stats_tlv 676 */ 677 HTT_DBG_GTX_STATS = 68, 678 679 680 /* keep this last */ 681 HTT_DBG_NUM_EXT_STATS = 256, 682 }; 683 684 /* 685 * Macros to get/set the bit field in config param[3] that indicates to 686 * clear corresponding per peer stats specified by config param 1 687 */ 688 #define HTT_DBG_EXT_PEER_STATS_RESET_M 0x00010000 689 #define HTT_DBG_EXT_PEER_STATS_RESET_S 16 690 691 #define HTT_DBG_EXT_PEER_STATS_RESET_GET(_var) \ 692 (((_var) & HTT_DBG_EXT_PEER_STATS_RESET_M) >> \ 693 HTT_DBG_EXT_PEER_STATS_RESET_S) 694 695 #define HTT_DBG_EXT_PEER_STATS_RESET_SET(_var, _val) \ 696 do { \ 697 HTT_CHECK_SET_VAL(HTT_DBG_EXT_PEER_STATS_RESET, _val); \ 698 ((_var) |= ((_val) << HTT_DBG_EXT_PEER_STATS_RESET_S)); \ 699 } while (0) 700 701 #define HTT_STATS_SUBTYPE_MAX 16 702 703 /* htt_mu_stats_upload_t 704 * Enumerations for specifying whether to upload all MU stats in response to 705 * HTT_DBG_EXT_STATS_PDEV_TX_MU, or if not all, then which subset. 706 */ 707 typedef enum { 708 /* HTT_UPLOAD_MU_STATS: upload all MU stats: 709 * UL MU-MIMO + DL MU-MIMO + UL MU-OFDMA + DL MU-OFDMA 710 * (note: included OFDMA stats are limited to 11ax) 711 */ 712 HTT_UPLOAD_MU_STATS, 713 714 /* HTT_UPLOAD_MU_MIMO_STATS: upload UL MU-MIMO + DL MU-MIMO stats */ 715 HTT_UPLOAD_MU_MIMO_STATS, 716 717 /* HTT_UPLOAD_MU_OFDMA_STATS: 718 * upload UL MU-OFDMA + DL MU-OFDMA stats (note: 11ax only stats) 719 */ 720 HTT_UPLOAD_MU_OFDMA_STATS, 721 722 HTT_UPLOAD_DL_MU_MIMO_STATS, 723 HTT_UPLOAD_UL_MU_MIMO_STATS, 724 /* HTT_UPLOAD_DL_MU_OFDMA_STATS: 725 * upload DL MU-OFDMA stats (note: 11ax only stats) 726 */ 727 HTT_UPLOAD_DL_MU_OFDMA_STATS, 728 /* HTT_UPLOAD_UL_MU_OFDMA_STATS: 729 * upload UL MU-OFDMA stats (note: 11ax only stats) 730 */ 731 HTT_UPLOAD_UL_MU_OFDMA_STATS, 732 733 /* 734 * Upload BE UL MU-OFDMA + BE DL MU-OFDMA stats, 735 * TLV: htt_tx_pdev_dl_be_mu_ofdma_sch_stats_tlv and 736 * htt_tx_pdev_ul_be_mu_ofdma_sch_stats_tlv 737 */ 738 HTT_UPLOAD_BE_MU_OFDMA_STATS, 739 740 /* 741 * Upload BE DL MU-OFDMA 742 * TLV: htt_tx_pdev_dl_be_mu_ofdma_sch_stats_tlv 743 */ 744 HTT_UPLOAD_BE_DL_MU_OFDMA_STATS, 745 746 /* 747 * Upload BE UL MU-OFDMA 748 * TLV: htt_tx_pdev_ul_be_mu_ofdma_sch_stats_tlv 749 */ 750 HTT_UPLOAD_BE_UL_MU_OFDMA_STATS, 751 } htt_mu_stats_upload_t; 752 753 /* htt_tx_rate_stats_upload_t 754 * Enumerations for specifying which stats to upload in response to 755 * HTT_DBG_EXT_STATS_PDEV_TX_RATE. 756 */ 757 typedef enum { 758 /* 11abgn, 11ac, and 11ax TX stats, and a few 11be SU stats 759 * 760 * TLV: htt_tx_pdev_rate_stats_tlv 761 */ 762 HTT_TX_RATE_STATS_DEFAULT, 763 764 /* 765 * Upload 11be OFDMA TX stats 766 * 767 * TLV: htt_tx_pdev_rate_stats_be_ofdma_tlv 768 */ 769 HTT_TX_RATE_STATS_UPLOAD_11BE_OFDMA, 770 } htt_tx_rate_stats_upload_t; 771 772 /* htt_rx_ul_trigger_stats_upload_t 773 * Enumerations for specifying which stats to upload in response to 774 * HTT_DBG_EXT_STATS_PDEV_TX_RATE. 775 */ 776 typedef enum { 777 /* Upload 11ax UL OFDMA RX Trigger stats 778 * 779 * TLV: htt_rx_pdev_ul_trigger_stats_tlv 780 */ 781 HTT_RX_UL_TRIGGER_STATS_UPLOAD_11AX_OFDMA, 782 783 /* 784 * Upload 11be UL OFDMA RX Trigger stats 785 * 786 * TLV: htt_rx_pdev_be_ul_trigger_stats_tlv 787 */ 788 HTT_RX_UL_TRIGGER_STATS_UPLOAD_11BE_OFDMA, 789 } htt_rx_ul_trigger_stats_upload_t; 790 791 /* 792 * The htt_rx_ul_mumimo_trigger_stats_upload_t enum values are 793 * provided by the host as one of the config param elements in 794 * the HTT_H2T EXT_STATS_REQ message, for stats type == 795 * HTT_DBG_EXT_STATS_PDEV_UL_MUMIMO_TRIG_STATS. 796 */ 797 typedef enum { 798 /* 799 * Upload 11ax UL MUMIMO RX Trigger stats 800 * TLV: htt_rx_pdev_ul_mumimo_trig_stats_tlv 801 */ 802 HTT_RX_UL_MUMIMO_TRIGGER_STATS_UPLOAD_11AX, 803 804 /* 805 * Upload 11be UL MUMIMO RX Trigger stats 806 * TLV: htt_rx_pdev_ul_mumimo_trig_be_stats_tlv 807 */ 808 HTT_RX_UL_MUMIMO_TRIGGER_STATS_UPLOAD_11BE, 809 } htt_rx_ul_mumimo_trigger_stats_upload_t; 810 811 /* htt_tx_pdev_txbf_ofdma_stats_upload_t 812 * Enumerations for specifying which stats to upload in response to 813 * HTT_DBG_EXT_STATS_TXBF_OFDMA. 814 */ 815 typedef enum { 816 /* upload 11ax TXBF OFDMA stats 817 * 818 * TLV: htt_tx_pdev_ax_txbf_ofdma_stats_t 819 */ 820 HTT_UPLOAD_AX_TXBF_OFDMA_STATS, 821 822 /* 823 * Upload 11be TXBF OFDMA stats 824 * 825 * TLV: htt_tx_pdev_be_txbf_ofdma_stats_t 826 */ 827 HTT_UPLOAD_BE_TXBF_OFDMA_STATS, 828 } htt_tx_pdev_txbf_ofdma_stats_upload_t; 829 830 /* htt_tx_pdev_puncture_stats_upload_t 831 * Enumerations for specifying which stats to upload in response to 832 * HTT_DBG_PDEV_PUNCTURE_STATS. 833 */ 834 typedef enum { 835 /* upload puncture stats for all supported modes, both TX and RX */ 836 HTT_UPLOAD_PUNCTURE_STATS_ALL, 837 838 /* upload puncture stats for all supported TX modes */ 839 HTT_UPLOAD_PUNCTURE_STATS_TX, 840 841 /* upload puncture stats for all supported RX modes */ 842 HTT_UPLOAD_PUNCTURE_STATS_RX, 843 } htt_tx_pdev_puncture_stats_upload_t; 844 845 #define HTT_STATS_MAX_STRING_SZ32 4 846 #define HTT_STATS_MACID_INVALID 0xff 847 #define HTT_TX_HWQ_MAX_DIFS_LATENCY_BINS 10 848 #define HTT_TX_HWQ_MAX_CMD_RESULT_STATS 13 849 #define HTT_TX_HWQ_MAX_CMD_STALL_STATS 5 850 #define HTT_TX_HWQ_MAX_FES_RESULT_STATS 10 851 #define HTT_PDEV_STATS_PPDU_DUR_HIST_BINS 16 852 #define HTT_PDEV_STATS_PPDU_DUR_HIST_INTERVAL_US 250 853 854 typedef enum { 855 HTT_STATS_TX_PDEV_NO_DATA_UNDERRUN = 0, 856 HTT_STATS_TX_PDEV_DATA_UNDERRUN_BETWEEN_MPDU = 1, 857 HTT_STATS_TX_PDEV_DATA_UNDERRUN_WITHIN_MPDU = 2, 858 HTT_TX_PDEV_MAX_URRN_STATS = 3, 859 } htt_tx_pdev_underrun_enum; 860 861 #define HTT_TX_PDEV_MAX_FLUSH_REASON_STATS 150 862 #define HTT_TX_PDEV_MAX_SIFS_BURST_STATS 9 863 #define HTT_TX_PDEV_MAX_SIFS_BURST_HIST_STATS 10 864 #define HTT_TX_PDEV_MAX_PHY_ERR_STATS 18 865 /* HTT_TX_PDEV_SCHED_TX_MODE_MAX: 866 * DEPRECATED - num sched tx mode max is 8 867 */ 868 #define HTT_TX_PDEV_SCHED_TX_MODE_MAX 4 869 #define HTT_TX_PDEV_NUM_SCHED_ORDER_LOG 20 870 871 #define HTT_RX_STATS_REFILL_MAX_RING 4 872 #define HTT_RX_STATS_RXDMA_MAX_ERR 16 873 #define HTT_RX_STATS_FW_DROP_REASON_MAX 16 874 875 /* Bytes stored in little endian order */ 876 /* Length should be multiple of DWORD */ 877 typedef struct { 878 htt_tlv_hdr_t tlv_hdr; 879 HTT_STATS_VAR_LEN_ARRAY1(A_UINT32, data); /* Can be variable length */ 880 } htt_stats_string_tlv; 881 882 #define HTT_TX_PDEV_STATS_CMN_MAC_ID_M 0x000000ff 883 #define HTT_TX_PDEV_STATS_CMN_MAC_ID_S 0 884 885 #define HTT_TX_PDEV_STATS_CMN_MAC_ID_GET(_var) \ 886 (((_var) & HTT_TX_PDEV_STATS_CMN_MAC_ID_M) >> \ 887 HTT_TX_PDEV_STATS_CMN_MAC_ID_S) 888 889 #define HTT_TX_PDEV_STATS_CMN_MAC_ID_SET(_var, _val) \ 890 do { \ 891 HTT_CHECK_SET_VAL(HTT_TX_PDEV_STATS_CMN_MAC_ID, _val); \ 892 ((_var) |= ((_val) << HTT_TX_PDEV_STATS_CMN_MAC_ID_S)); \ 893 } while (0) 894 895 /* == TX PDEV STATS == */ 896 typedef struct { 897 htt_tlv_hdr_t tlv_hdr; 898 899 /** 900 * BIT [ 7 : 0] :- mac_id 901 * BIT [31 : 8] :- reserved 902 */ 903 A_UINT32 mac_id__word; 904 /** Num PPDUs queued to HW */ 905 A_UINT32 hw_queued; 906 /** Num PPDUs reaped from HW */ 907 A_UINT32 hw_reaped; 908 /** Num underruns */ 909 A_UINT32 underrun; 910 /** Num HW Paused counter */ 911 A_UINT32 hw_paused; 912 /** Num HW flush counter */ 913 A_UINT32 hw_flush; 914 /** Num HW filtered counter */ 915 A_UINT32 hw_filt; 916 /** Num PPDUs cleaned up in TX abort */ 917 A_UINT32 tx_abort; 918 /** Num MPDUs requeued by SW */ 919 A_UINT32 mpdu_requed; 920 /** excessive retries */ 921 A_UINT32 tx_xretry; 922 /** Last used data hw rate code */ 923 A_UINT32 data_rc; 924 /** frames dropped due to excessive SW retries */ 925 A_UINT32 mpdu_dropped_xretry; 926 /** illegal rate phy errors */ 927 A_UINT32 illgl_rate_phy_err; 928 /** wal pdev continuous xretry */ 929 A_UINT32 cont_xretry; 930 /** wal pdev tx timeout */ 931 A_UINT32 tx_timeout; 932 /** wal pdev resets */ 933 A_UINT32 pdev_resets; 934 /** PHY/BB underrun */ 935 A_UINT32 phy_underrun; 936 /** MPDU is more than txop limit */ 937 A_UINT32 txop_ovf; 938 /** Number of Sequences posted */ 939 A_UINT32 seq_posted; 940 /** Number of Sequences failed queueing */ 941 A_UINT32 seq_failed_queueing; 942 /** Number of Sequences completed */ 943 A_UINT32 seq_completed; 944 /** Number of Sequences restarted */ 945 A_UINT32 seq_restarted; 946 /** Number of MU Sequences posted */ 947 A_UINT32 mu_seq_posted; 948 /** Number of time HW ring is paused between seq switch within ISR */ 949 A_UINT32 seq_switch_hw_paused; 950 /** Number of times seq continuation in DSR */ 951 A_UINT32 next_seq_posted_dsr; 952 /** Number of times seq continuation in ISR */ 953 A_UINT32 seq_posted_isr; 954 /** Number of seq_ctrl cached. */ 955 A_UINT32 seq_ctrl_cached; 956 /** Number of MPDUs successfully transmitted */ 957 A_UINT32 mpdu_count_tqm; 958 /** Number of MSDUs successfully transmitted */ 959 A_UINT32 msdu_count_tqm; 960 /** Number of MPDUs dropped */ 961 A_UINT32 mpdu_removed_tqm; 962 /** Number of MSDUs dropped */ 963 A_UINT32 msdu_removed_tqm; 964 /** Num MPDUs flushed by SW, HWPAUSED, SW TXABORT (Reset,channel change) */ 965 A_UINT32 mpdus_sw_flush; 966 /** Num MPDUs filtered by HW, all filter condition (TTL expired) */ 967 A_UINT32 mpdus_hw_filter; 968 /** 969 * Num MPDUs truncated by PDG 970 * (TXOP, TBTT, PPDU_duration based on rate, dyn_bw) 971 */ 972 A_UINT32 mpdus_truncated; 973 /** Num MPDUs that was tried but didn't receive ACK or BA */ 974 A_UINT32 mpdus_ack_failed; 975 /** Num MPDUs that was dropped due to expiry (MSDU TTL) */ 976 A_UINT32 mpdus_expired; 977 /** Num MPDUs that was retried within seq_ctrl (MGMT/LEGACY) */ 978 A_UINT32 mpdus_seq_hw_retry; 979 /** Num of TQM acked cmds processed */ 980 A_UINT32 ack_tlv_proc; 981 /** coex_abort_mpdu_cnt valid */ 982 A_UINT32 coex_abort_mpdu_cnt_valid; 983 /** coex_abort_mpdu_cnt from TX FES stats */ 984 A_UINT32 coex_abort_mpdu_cnt; 985 /** 986 * Number of total PPDUs 987 * (DATA, MGMT, excludes selfgen) tried over the air (OTA) 988 */ 989 A_UINT32 num_total_ppdus_tried_ota; 990 /** Number of data PPDUs tried over the air (OTA) */ 991 A_UINT32 num_data_ppdus_tried_ota; 992 /** Num Local control/mgmt frames (MSDUs) queued */ 993 A_UINT32 local_ctrl_mgmt_enqued; 994 /** 995 * Num Local control/mgmt frames (MSDUs) done 996 * It includes all local ctrl/mgmt completions 997 * (acked, no ack, flush, TTL, etc) 998 */ 999 A_UINT32 local_ctrl_mgmt_freed; 1000 /** Num Local data frames (MSDUs) queued */ 1001 A_UINT32 local_data_enqued; 1002 /** 1003 * Num Local data frames (MSDUs) done 1004 * It includes all local data completions 1005 * (acked, no ack, flush, TTL, etc) 1006 */ 1007 A_UINT32 local_data_freed; 1008 1009 /** Num MPDUs tried by SW */ 1010 A_UINT32 mpdu_tried; 1011 /** Num of waiting seq posted in ISR completion handler */ 1012 A_UINT32 isr_wait_seq_posted; 1013 1014 A_UINT32 tx_active_dur_us_low; 1015 A_UINT32 tx_active_dur_us_high; 1016 /** Number of MPDUs dropped after max retries */ 1017 A_UINT32 remove_mpdus_max_retries; 1018 /** Num HTT cookies dispatched */ 1019 A_UINT32 comp_delivered; 1020 /** successful ppdu transmissions */ 1021 A_UINT32 ppdu_ok; 1022 /** Scheduler self triggers */ 1023 A_UINT32 self_triggers; 1024 /** FES duration of last tx data PPDU in us (sch_eval_end - ppdu_start) */ 1025 A_UINT32 tx_time_dur_data; 1026 /** Num of times sequence terminated due to ppdu duration < burst limit */ 1027 A_UINT32 seq_qdepth_repost_stop; 1028 /** Num of times MU sequence terminated due to MSDUs reaching threshold */ 1029 A_UINT32 mu_seq_min_msdu_repost_stop; 1030 /** Num of times SU sequence terminated due to MSDUs reaching threshold */ 1031 A_UINT32 seq_min_msdu_repost_stop; 1032 /** Num of times sequence terminated due to no TXOP available */ 1033 A_UINT32 seq_txop_repost_stop; 1034 /** Num of times the next sequence got cancelled */ 1035 A_UINT32 next_seq_cancel; 1036 /** Num of times fes offset was misaligned */ 1037 A_UINT32 fes_offsets_err_cnt; 1038 /** Num of times peer denylisted for MU-MIMO transmission */ 1039 A_UINT32 num_mu_peer_blacklisted; 1040 /** Num of times mu_ofdma seq posted */ 1041 A_UINT32 mu_ofdma_seq_posted; 1042 /** Num of times UL MU MIMO seq posted */ 1043 A_UINT32 ul_mumimo_seq_posted; 1044 /** Num of times UL OFDMA seq posted */ 1045 A_UINT32 ul_ofdma_seq_posted; 1046 /** Num of times Thermal module suspended scheduler */ 1047 A_UINT32 thermal_suspend_cnt; 1048 /** Num of times DFS module suspended scheduler */ 1049 A_UINT32 dfs_suspend_cnt; 1050 /** Num of times TX abort module suspended scheduler */ 1051 A_UINT32 tx_abort_suspend_cnt; 1052 /** 1053 * This field is a target-specific bit mask of suspended PPDU tx queues. 1054 * Since the bit mask definition is different for different targets, 1055 * this field is not meant for general use, but rather for debugging use. 1056 */ 1057 A_UINT32 tgt_specific_opaque_txq_suspend_info; 1058 /** 1059 * Last SCHEDULER suspend reason 1060 * 1 -> Thermal Module 1061 * 2 -> DFS Module 1062 * 3 -> Tx Abort Module 1063 */ 1064 A_UINT32 last_suspend_reason; 1065 /** Num of dynamic mimo ps dlmumimo sequences posted */ 1066 A_UINT32 num_dyn_mimo_ps_dlmumimo_sequences; 1067 /** Num of times su bf sequences are denylisted */ 1068 A_UINT32 num_su_txbf_denylisted; 1069 /** pdev uptime in microseconds **/ 1070 A_UINT32 pdev_up_time_us_low; 1071 A_UINT32 pdev_up_time_us_high; 1072 /** count of ofdma sequences flushed */ 1073 A_UINT32 ofdma_seq_flush; 1074 } htt_stats_tx_pdev_cmn_tlv; 1075 /* preserve old name alias for new name consistent with the tag name */ 1076 typedef htt_stats_tx_pdev_cmn_tlv htt_tx_pdev_stats_cmn_tlv; 1077 1078 #define HTT_TX_PDEV_STATS_URRN_TLV_SZ(_num_elems) (sizeof(A_UINT32) * (_num_elems)) 1079 /* NOTE: Variable length TLV, use length spec to infer array size */ 1080 typedef struct { 1081 htt_tlv_hdr_t tlv_hdr; 1082 1083 /* HTT_TX_PDEV_MAX_URRN_STATS */ 1084 HTT_STATS_VAR_LEN_ARRAY1(A_UINT32, urrn_stats); 1085 } htt_stats_tx_pdev_underrun_tlv; 1086 /* preserve old name alias for new name consistent with the tag name */ 1087 typedef htt_stats_tx_pdev_underrun_tlv htt_tx_pdev_stats_urrn_tlv_v; 1088 1089 #define HTT_TX_PDEV_STATS_FLUSH_TLV_SZ(_num_elems) (sizeof(A_UINT32) * (_num_elems)) 1090 /* NOTE: Variable length TLV, use length spec to infer array size */ 1091 typedef struct { 1092 htt_tlv_hdr_t tlv_hdr; 1093 1094 /* HTT_TX_PDEV_MAX_FLUSH_REASON_STATS */ 1095 HTT_STATS_VAR_LEN_ARRAY1(A_UINT32, flush_errs); 1096 } htt_stats_tx_pdev_flush_tlv; 1097 /* preserve old name alias for new name consistent with the tag name */ 1098 typedef htt_stats_tx_pdev_flush_tlv htt_tx_pdev_stats_flush_tlv_v; 1099 1100 #define HTT_TX_PDEV_STATS_MLO_ABORT_TLV_SZ(_num_elems) (sizeof(A_UINT32) * (_num_elems)) 1101 /* NOTE: Variable length TLV, use length spec to infer array size */ 1102 typedef struct { 1103 htt_tlv_hdr_t tlv_hdr; 1104 1105 /* HTT_TX_PDEV_MAX_MLO_ABORT_REASON_STATS */ 1106 HTT_STATS_VAR_LEN_ARRAY1(A_UINT32, mlo_abort_cnt); 1107 } htt_stats_tx_pdev_mlo_abort_tlv; 1108 /* preserve old name alias for new name consistent with the tag name */ 1109 typedef htt_stats_tx_pdev_mlo_abort_tlv htt_tx_pdev_stats_mlo_abort_tlv_v; 1110 1111 #define HTT_TX_PDEV_STATS_MLO_TXOP_ABORT_TLV_SZ(_num_elems) (sizeof(A_UINT32) * (_num_elems)) 1112 /* NOTE: Variable length TLV, use length spec to infer array size */ 1113 typedef struct { 1114 htt_tlv_hdr_t tlv_hdr; 1115 1116 /* HTT_TX_PDEV_MAX_MLO_ABORT_REASON_STATS */ 1117 HTT_STATS_VAR_LEN_ARRAY1(A_UINT32, mlo_txop_abort_cnt); 1118 } htt_stats_tx_pdev_mlo_txop_abort_tlv; 1119 /* preserve old name alias for new name consistent with the tag name */ 1120 typedef htt_stats_tx_pdev_mlo_txop_abort_tlv 1121 htt_tx_pdev_stats_mlo_txop_abort_tlv_v; 1122 1123 #define HTT_TX_PDEV_STATS_SIFS_TLV_SZ(_num_elems) (sizeof(A_UINT32) * (_num_elems)) 1124 /* NOTE: Variable length TLV, use length spec to infer array size */ 1125 typedef struct { 1126 htt_tlv_hdr_t tlv_hdr; 1127 1128 /* HTT_TX_PDEV_MAX_SIFS_BURST_STATS */ 1129 HTT_STATS_VAR_LEN_ARRAY1(A_UINT32, sifs_status); 1130 } htt_stats_tx_pdev_sifs_tlv; 1131 /* preserve old name alias for new name consistent with the tag name */ 1132 typedef htt_stats_tx_pdev_sifs_tlv htt_tx_pdev_stats_sifs_tlv_v; 1133 1134 #define HTT_TX_PDEV_STATS_PHY_ERR_TLV_SZ(_num_elems) (sizeof(A_UINT32) * (_num_elems)) 1135 /* NOTE: Variable length TLV, use length spec to infer array size */ 1136 typedef struct { 1137 htt_tlv_hdr_t tlv_hdr; 1138 1139 /* HTT_TX_PDEV_MAX_PHY_ERR_STATS */ 1140 HTT_STATS_VAR_LEN_ARRAY1(A_UINT32, phy_errs); 1141 } htt_stats_tx_pdev_phy_err_tlv; 1142 /* preserve old name alias for new name consistent with the tag name */ 1143 typedef htt_stats_tx_pdev_phy_err_tlv htt_tx_pdev_stats_phy_err_tlv_v; 1144 1145 /* 1146 * Each array in the below struct has 16 elements, to cover the 16 possible 1147 * values for the CW and AIFS parameters. Each element within the array 1148 * stores the counter indicating how many transmissions have occurred with 1149 * that particular value for the MU EDCA parameter in question. 1150 */ 1151 #define HTT_STATS_MUEDCA_VALUE_MAX 16 1152 typedef struct { /* DEPRECATED */ 1153 htt_tlv_hdr_t tlv_hdr; 1154 A_UINT32 aifs[HTT_NUM_AC_WMM][HTT_STATS_MUEDCA_VALUE_MAX]; 1155 A_UINT32 cw_min[HTT_NUM_AC_WMM][HTT_STATS_MUEDCA_VALUE_MAX]; 1156 A_UINT32 cw_max[HTT_NUM_AC_WMM][HTT_STATS_MUEDCA_VALUE_MAX]; 1157 } htt_stats_tx_pdev_muedca_params_stats_tlv; 1158 /* preserve old name alias for new name consistent with the tag name */ 1159 typedef htt_stats_tx_pdev_muedca_params_stats_tlv 1160 htt_tx_pdev_muedca_params_stats_tlv_v; 1161 1162 typedef struct { 1163 htt_tlv_hdr_t tlv_hdr; 1164 A_UINT32 relaxed_mu_edca[HTT_NUM_AC_WMM]; 1165 A_UINT32 mumimo_aggressive_mu_edca[HTT_NUM_AC_WMM]; 1166 A_UINT32 mumimo_relaxed_mu_edca[HTT_NUM_AC_WMM]; 1167 A_UINT32 muofdma_aggressive_mu_edca[HTT_NUM_AC_WMM]; 1168 A_UINT32 muofdma_relaxed_mu_edca[HTT_NUM_AC_WMM]; 1169 A_UINT32 latency_mu_edca[HTT_NUM_AC_WMM]; 1170 A_UINT32 psd_boost_mu_edca[HTT_NUM_AC_WMM]; 1171 } htt_stats_tx_pdev_mu_edca_params_stats_tlv; 1172 /* preserve old name alias for new name consistent with the tag name */ 1173 typedef htt_stats_tx_pdev_mu_edca_params_stats_tlv 1174 htt_tx_pdev_mu_edca_params_stats_tlv_v; 1175 1176 typedef struct { 1177 htt_tlv_hdr_t tlv_hdr; 1178 A_UINT32 ul_mumimo_less_aggressive[HTT_NUM_AC_WMM]; 1179 A_UINT32 ul_mumimo_medium_aggressive[HTT_NUM_AC_WMM]; 1180 A_UINT32 ul_mumimo_highly_aggressive[HTT_NUM_AC_WMM]; 1181 A_UINT32 ul_mumimo_default_relaxed[HTT_NUM_AC_WMM]; 1182 A_UINT32 ul_muofdma_less_aggressive[HTT_NUM_AC_WMM]; 1183 A_UINT32 ul_muofdma_medium_aggressive[HTT_NUM_AC_WMM]; 1184 A_UINT32 ul_muofdma_highly_aggressive[HTT_NUM_AC_WMM]; 1185 A_UINT32 ul_muofdma_default_relaxed[HTT_NUM_AC_WMM]; 1186 } htt_stats_tx_pdev_ap_edca_params_stats_tlv; 1187 /* preserve old name alias for new name consistent with the tag name */ 1188 typedef htt_stats_tx_pdev_ap_edca_params_stats_tlv 1189 htt_tx_pdev_ap_edca_params_stats_tlv_v; 1190 1191 #define HTT_TX_PDEV_SIFS_BURST_HIST_STATS 10 1192 #define HTT_TX_PDEV_STATS_SIFS_HIST_TLV_SZ(_num_elems) (sizeof(A_UINT32) * (_num_elems)) 1193 /* NOTE: Variable length TLV, use length spec to infer array size */ 1194 typedef struct { 1195 htt_tlv_hdr_t tlv_hdr; 1196 1197 /* HTT_TX_PDEV_SIFS_BURST_HIST_STATS */ 1198 HTT_STATS_VAR_LEN_ARRAY1(A_UINT32, sifs_hist_status); 1199 } htt_stats_tx_pdev_sifs_hist_tlv; 1200 /* preserve old name alias for new name consistent with the tag name */ 1201 typedef htt_stats_tx_pdev_sifs_hist_tlv htt_tx_pdev_stats_sifs_hist_tlv_v; 1202 1203 typedef struct { 1204 htt_tlv_hdr_t tlv_hdr; 1205 A_UINT32 num_data_ppdus_legacy_su; 1206 A_UINT32 num_data_ppdus_ac_su; 1207 A_UINT32 num_data_ppdus_ax_su; 1208 A_UINT32 num_data_ppdus_ac_su_txbf; 1209 A_UINT32 num_data_ppdus_ax_su_txbf; 1210 } htt_stats_tx_pdev_tx_ppdu_stats_tlv; 1211 /* preserve old name alias for new name consistent with the tag name */ 1212 typedef htt_stats_tx_pdev_tx_ppdu_stats_tlv 1213 htt_tx_pdev_stats_tx_ppdu_stats_tlv_v; 1214 1215 typedef enum { 1216 HTT_TX_WAL_ISR_SCHED_SUCCESS, 1217 HTT_TX_WAL_ISR_SCHED_FILTER, 1218 HTT_TX_WAL_ISR_SCHED_RESP_TIMEOUT, 1219 HTT_TX_WAL_ISR_SCHED_RATES_EXHAUSTED, 1220 HTT_TX_WAL_ISR_SCHED_DATA_EXHAUSTED, 1221 HTT_TX_WAL_ISR_SCHED_SEQ_ABORT, 1222 HTT_TX_WAL_ISR_SCHED_NOTIFY_FRAME_ENCOUNTERED, 1223 HTT_TX_WAL_ISR_SCHED_COMPLETION, 1224 HTT_TX_WAL_ISR_SCHED_IN_PROGRESS, 1225 } htt_tx_wal_tx_isr_sched_status; 1226 1227 /* [0]- nr4 , [1]- nr8 */ 1228 #define HTT_STATS_NUM_NR_BINS 2 1229 /* Termination status stated in htt_tx_wal_tx_isr_sched_status */ 1230 #define HTT_STATS_MAX_NUM_SCHED_STATUS 9 1231 #define HTT_STATS_MAX_NUM_MU_PPDU_PER_BURST 10 1232 #define HTT_STATS_MAX_NUM_SCHED_STATUS_WORDS \ 1233 (HTT_STATS_NUM_NR_BINS * HTT_STATS_MAX_NUM_SCHED_STATUS) 1234 #define HTT_STATS_MAX_NUM_MU_PPDU_PER_BURST_WORDS \ 1235 (HTT_STATS_NUM_NR_BINS * HTT_STATS_MAX_NUM_MU_PPDU_PER_BURST) 1236 1237 typedef enum { 1238 HTT_STATS_HWMODE_AC = 0, 1239 HTT_STATS_HWMODE_AX = 1, 1240 HTT_STATS_HWMODE_BE = 2, 1241 } htt_stats_hw_mode; 1242 1243 typedef struct { 1244 htt_tlv_hdr_t tlv_hdr; 1245 1246 A_UINT32 hw_mode; /* HTT_STATS_HWMODE_xx */ 1247 1248 A_UINT32 mu_mimo_num_seq_term_status[HTT_STATS_MAX_NUM_SCHED_STATUS_WORDS]; 1249 1250 A_UINT32 mu_mimo_num_ppdu_completed_per_burst[HTT_STATS_MAX_NUM_MU_PPDU_PER_BURST_WORDS]; 1251 1252 A_UINT32 mu_mimo_num_seq_posted[HTT_STATS_NUM_NR_BINS]; 1253 1254 A_UINT32 mu_mimo_num_ppdu_posted_per_burst[HTT_STATS_MAX_NUM_MU_PPDU_PER_BURST_WORDS]; 1255 } htt_stats_mu_ppdu_dist_tlv; 1256 /* preserve old name alias for new name consistent with the tag name */ 1257 typedef htt_stats_mu_ppdu_dist_tlv htt_pdev_mu_ppdu_dist_tlv_v; 1258 1259 #define HTT_TX_PDEV_STATS_TRIED_MPDU_CNT_HIST_TLV_SZ(_num_elems) (sizeof(A_UINT32) * (_num_elems)) 1260 /* NOTE: Variable length TLV, use length spec to infer array size . 1261 * 1262 * Tried_mpdu_cnt_hist is the histogram of MPDUs tries per HWQ. 1263 * The tries here is the count of the MPDUS within a PPDU that the 1264 * HW had attempted to transmit on air, for the HWSCH Schedule 1265 * command submitted by FW.It is not the retry attempts. 1266 * The histogram bins are 0-29, 30-59, 60-89 and so on. The are 1267 * 10 bins in this histogram. They are defined in FW using the 1268 * following macros 1269 * #define WAL_MAX_TRIED_MPDU_CNT_HISTOGRAM 9 1270 * #define WAL_TRIED_MPDU_CNT_HISTOGRAM_INTERVAL 30 1271 * 1272 */ 1273 typedef struct { 1274 htt_tlv_hdr_t tlv_hdr; 1275 A_UINT32 hist_bin_size; 1276 1277 /* HTT_TX_PDEV_TRIED_MPDU_CNT_HIST */ 1278 HTT_STATS_VAR_LEN_ARRAY1(A_UINT32, tried_mpdu_cnt_hist); 1279 } htt_stats_tx_pdev_tried_mpdu_cnt_hist_tlv; 1280 /* preserve old name alias for new name consistent with the tag name */ 1281 typedef htt_stats_tx_pdev_tried_mpdu_cnt_hist_tlv 1282 htt_tx_pdev_stats_tried_mpdu_cnt_hist_tlv_v; 1283 1284 typedef struct { 1285 htt_tlv_hdr_t tlv_hdr; 1286 /* Num MGMT MPDU transmitted by the target */ 1287 A_UINT32 fw_tx_mgmt_subtype[HTT_STATS_SUBTYPE_MAX]; 1288 } htt_stats_pdev_ctrl_path_tx_stats_tlv; 1289 /* preserve old name alias for new name consistent with the tag name */ 1290 typedef htt_stats_pdev_ctrl_path_tx_stats_tlv htt_pdev_ctrl_path_tx_stats_tlv_v; 1291 1292 /* STATS_TYPE: HTT_DBG_EXT_STATS_PDEV_TX 1293 * TLV_TAGS: 1294 * - HTT_STATS_TX_PDEV_CMN_TAG 1295 * - HTT_STATS_TX_PDEV_URRN_TAG 1296 * - HTT_STATS_TX_PDEV_SIFS_TAG 1297 * - HTT_STATS_TX_PDEV_FLUSH_TAG 1298 * - HTT_STATS_TX_PDEV_PHY_ERR_TAG 1299 * - HTT_STATS_TX_PDEV_SIFS_HIST_TAG 1300 * - HTT_STATS_TX_PDEV_TX_PPDU_STATS_TAG 1301 * - HTT_STATS_TX_PDEV_TRIED_MPDU_CNT_HIST_TAG 1302 * - HTT_STATS_PDEV_CTRL_PATH_TX_STATS_TAG 1303 * - HTT_STATS_MU_PPDU_DIST_TAG 1304 */ 1305 /* NOTE: 1306 * This structure is for documentation, and cannot be safely used directly. 1307 * Instead, use the constituent TLV structures to fill/parse. 1308 */ 1309 #ifdef ATH_TARGET 1310 typedef struct _htt_tx_pdev_stats { 1311 htt_stats_tx_pdev_cmn_tlv cmn_tlv; 1312 htt_stats_tx_pdev_underrun_tlv underrun_tlv; 1313 htt_stats_tx_pdev_sifs_tlv sifs_tlv; 1314 htt_stats_tx_pdev_flush_tlv flush_tlv; 1315 htt_stats_tx_pdev_phy_err_tlv phy_err_tlv; 1316 htt_stats_tx_pdev_sifs_hist_tlv sifs_hist_tlv; 1317 htt_stats_tx_pdev_tx_ppdu_stats_tlv tx_su_tlv; 1318 htt_stats_tx_pdev_tried_mpdu_cnt_hist_tlv tried_mpdu_cnt_hist_tlv; 1319 htt_stats_pdev_ctrl_path_tx_stats_tlv ctrl_path_tx_tlv; 1320 htt_stats_mu_ppdu_dist_tlv mu_ppdu_dist_tlv; 1321 } htt_tx_pdev_stats_t; 1322 #endif /* ATH_TARGET */ 1323 1324 /* == SOC ERROR STATS == */ 1325 1326 /* =============== PDEV ERROR STATS ============== */ 1327 #define HTT_STATS_MAX_HW_INTR_NAME_LEN 8 1328 typedef struct { 1329 htt_tlv_hdr_t tlv_hdr; 1330 /* Stored as little endian */ 1331 A_UINT8 hw_intr_name[HTT_STATS_MAX_HW_INTR_NAME_LEN]; 1332 A_UINT32 mask; 1333 A_UINT32 count; 1334 } htt_stats_hw_intr_misc_tlv; 1335 /* preserve old name alias for new name consistent with the tag name */ 1336 typedef htt_stats_hw_intr_misc_tlv htt_hw_stats_intr_misc_tlv; 1337 1338 #define HTT_STATS_MAX_HW_MODULE_NAME_LEN 8 1339 typedef struct { 1340 htt_tlv_hdr_t tlv_hdr; 1341 /* Stored as little endian */ 1342 A_UINT8 hw_module_name[HTT_STATS_MAX_HW_MODULE_NAME_LEN]; 1343 A_UINT32 count; 1344 } htt_stats_hw_wd_timeout_tlv; 1345 /* preserve old name alias for new name consistent with the tag name */ 1346 typedef htt_stats_hw_wd_timeout_tlv htt_hw_stats_wd_timeout_tlv; 1347 1348 #define HTT_HW_STATS_PDEV_ERRS_MAC_ID_M 0x000000ff 1349 #define HTT_HW_STATS_PDEV_ERRS_MAC_ID_S 0 1350 1351 #define HTT_HW_STATS_PDEV_ERRS_MAC_ID_GET(_var) \ 1352 (((_var) & HTT_HW_STATS_PDEV_ERRS_MAC_ID_M) >> \ 1353 HTT_HW_STATS_PDEV_ERRS_MAC_ID_S) 1354 1355 #define HTT_HW_STATS_PDEV_ERRS_MAC_ID_SET(_var, _val) \ 1356 do { \ 1357 HTT_CHECK_SET_VAL(HTT_HW_STATS_PDEV_ERRS_MAC_ID, _val); \ 1358 ((_var) |= ((_val) << HTT_HW_STATS_PDEV_ERRS_MAC_ID_S)); \ 1359 } while (0) 1360 1361 typedef struct { 1362 htt_tlv_hdr_t tlv_hdr; 1363 1364 /* BIT [ 7 : 0] :- mac_id 1365 * BIT [31 : 8] :- reserved 1366 */ 1367 A_UINT32 mac_id__word; 1368 A_UINT32 tx_abort; 1369 A_UINT32 tx_abort_fail_count; 1370 A_UINT32 rx_abort; 1371 A_UINT32 rx_abort_fail_count; 1372 A_UINT32 warm_reset; 1373 A_UINT32 cold_reset; 1374 A_UINT32 tx_flush; 1375 A_UINT32 tx_glb_reset; 1376 A_UINT32 tx_txq_reset; 1377 A_UINT32 rx_timeout_reset; 1378 A_UINT32 mac_cold_reset_restore_cal; 1379 A_UINT32 mac_cold_reset; 1380 A_UINT32 mac_warm_reset; 1381 A_UINT32 mac_only_reset; 1382 A_UINT32 phy_warm_reset; 1383 A_UINT32 phy_warm_reset_ucode_trig; 1384 A_UINT32 mac_warm_reset_restore_cal; 1385 A_UINT32 mac_sfm_reset; 1386 A_UINT32 phy_warm_reset_m3_ssr; 1387 A_UINT32 phy_warm_reset_reason_phy_m3; 1388 A_UINT32 phy_warm_reset_reason_tx_hw_stuck; 1389 A_UINT32 phy_warm_reset_reason_num_cca_rx_frame_stuck; 1390 A_UINT32 phy_warm_reset_reason_wal_rx_recovery_rst_rx_busy; 1391 A_UINT32 phy_warm_reset_reason_wal_rx_recovery_rst_mac_hang; 1392 A_UINT32 phy_warm_reset_reason_mac_reset_converted_phy_reset; 1393 1394 A_UINT32 wal_rx_recovery_rst_mac_hang_count; 1395 A_UINT32 wal_rx_recovery_rst_known_sig_count; 1396 A_UINT32 wal_rx_recovery_rst_no_rx_count; 1397 A_UINT32 wal_rx_recovery_rst_no_rx_consecutive_count; 1398 A_UINT32 wal_rx_recovery_rst_rx_busy_count; 1399 A_UINT32 wal_rx_recovery_rst_phy_mac_hang_count; 1400 A_UINT32 rx_flush_cnt; /* Num rx flush issued */ 1401 A_UINT32 phy_warm_reset_reason_tx_lifetime_expiry_cca_stuck; 1402 A_UINT32 phy_warm_reset_reason_tx_consecutive_flush9_war; 1403 A_UINT32 phy_warm_reset_reason_tx_hwsch_reset_war; 1404 A_UINT32 phy_warm_reset_reason_hwsch_wdog_or_cca_wdog_war; 1405 A_UINT32 fw_rx_rings_reset; 1406 /** 1407 * Num of iterations rx leak prevention successfully done. 1408 */ 1409 A_UINT32 rx_dest_drain_rx_descs_leak_prevention_done; 1410 /** 1411 * Num of rx descs successfully saved by rx leak prevention. 1412 */ 1413 A_UINT32 rx_dest_drain_rx_descs_saved_cnt; 1414 /* 1415 * Stats to debug reason Rx leak prevention 1416 * was not required to be kicked in. 1417 */ 1418 A_UINT32 rx_dest_drain_rxdma2reo_leak_detected; 1419 A_UINT32 rx_dest_drain_rxdma2fw_leak_detected; 1420 A_UINT32 rx_dest_drain_rxdma2wbm_leak_detected; 1421 A_UINT32 rx_dest_drain_rxdma1_2sw_leak_detected; 1422 A_UINT32 rx_dest_drain_rx_drain_ok_mac_idle; 1423 A_UINT32 rx_dest_drain_ok_mac_not_idle; 1424 A_UINT32 rx_dest_drain_prerequisite_invld; 1425 A_UINT32 rx_dest_drain_skip_for_non_lmac_reset; 1426 A_UINT32 rx_dest_drain_hw_fifo_not_empty_post_drain_wait; 1427 } htt_stats_hw_pdev_errs_tlv; 1428 /* preserve old name alias for new name consistent with the tag name */ 1429 typedef htt_stats_hw_pdev_errs_tlv htt_hw_stats_pdev_errs_tlv; 1430 1431 typedef struct { 1432 htt_tlv_hdr_t tlv_hdr; 1433 1434 /* BIT [ 7 : 0] :- mac_id 1435 * BIT [31 : 8] :- reserved 1436 */ 1437 A_UINT32 mac_id__word; 1438 A_UINT32 last_unpause_ppdu_id; 1439 A_UINT32 hwsch_unpause_wait_tqm_write; 1440 A_UINT32 hwsch_dummy_tlv_skipped; 1441 A_UINT32 hwsch_misaligned_offset_received; 1442 A_UINT32 hwsch_reset_count; 1443 A_UINT32 hwsch_dev_reset_war; 1444 A_UINT32 hwsch_delayed_pause; 1445 A_UINT32 hwsch_long_delayed_pause; 1446 A_UINT32 sch_rx_ppdu_no_response; 1447 A_UINT32 sch_selfgen_response; 1448 A_UINT32 sch_rx_sifs_resp_trigger; 1449 } htt_stats_whal_tx_tlv; 1450 /* preserve old name alias for new name consistent with the tag name */ 1451 typedef htt_stats_whal_tx_tlv htt_hw_stats_whal_tx_tlv; 1452 1453 typedef struct { 1454 htt_tlv_hdr_t tlv_hdr; 1455 1456 A_UINT32 wsib_event_watchdog_timeout; 1457 A_UINT32 wsib_event_slave_tlv_length_error; 1458 A_UINT32 wsib_event_slave_parity_error; 1459 A_UINT32 wsib_event_slave_direct_message; 1460 A_UINT32 wsib_event_slave_backpressure_error; 1461 A_UINT32 wsib_event_master_tlv_length_error; 1462 } htt_stats_whal_wsi_tlv; 1463 1464 typedef struct { 1465 htt_tlv_hdr_t tlv_hdr; 1466 /** 1467 * BIT [ 7 : 0] :- mac_id 1468 * BIT [31 : 8] :- reserved 1469 */ 1470 union { 1471 struct { 1472 A_UINT32 mac_id: 8, 1473 reserved: 24; 1474 }; 1475 A_UINT32 mac_id__word; 1476 }; 1477 1478 /** 1479 * hw_wars is a variable-length array, with each element counting 1480 * the number of occurrences of the corresponding type of HW WAR. 1481 * That is, hw_wars[0] indicates how many times HW WAR 0 occurred, 1482 * hw_wars[1] indicates how many times HW WAR 1 occurred, etc. 1483 * The target has an internal HW WAR mapping that it uses to keep 1484 * track of which HW WAR is WAR 0, which HW WAR is WAR 1, etc. 1485 */ 1486 HTT_STATS_VAR_LEN_ARRAY1(A_UINT32, hw_wars); 1487 } htt_stats_hw_war_tlv; 1488 /* preserve old name alias for new name consistent with the tag name */ 1489 typedef htt_stats_hw_war_tlv htt_hw_war_stats_tlv; 1490 /* provide properly-named macro */ 1491 #define HTT_STATS_HW_WAR_MAC_ID_GET(word) (word & 0xff) 1492 1493 /* STATS_TYPE: HTT_DBG_EXT_STATS_PDEV_ERROR 1494 * TLV_TAGS: 1495 * - HTT_STATS_HW_PDEV_ERRS_TAG 1496 * - HTT_STATS_HW_INTR_MISC_TAG (multiple) 1497 * - HTT_STATS_HW_WD_TIMEOUT_TAG (multiple) 1498 * - HTT_STATS_WHAL_TX_TAG 1499 * - HTT_STATS_HW_WAR_TAG 1500 */ 1501 /* NOTE: 1502 * This structure is for documentation, and cannot be safely used directly. 1503 * Instead, use the constituent TLV structures to fill/parse. 1504 */ 1505 #ifdef ATH_TARGET 1506 typedef struct _htt_pdev_err_stats { 1507 htt_stats_hw_pdev_errs_tlv pdev_errs; 1508 htt_stats_hw_intr_misc_tlv misc_stats[1]; 1509 htt_stats_hw_wd_timeout_tlv wd_timeout[1]; 1510 htt_stats_whal_tx_tlv whal_tx_stats; 1511 htt_stats_hw_war_tlv hw_war; 1512 } htt_hw_err_stats_t; 1513 #endif /* ATH_TARGET */ 1514 1515 /* ============ PEER STATS ============ */ 1516 1517 #define HTT_MSDU_FLOW_STATS_TX_FLOW_NUM_M 0x0000ffff 1518 #define HTT_MSDU_FLOW_STATS_TX_FLOW_NUM_S 0 1519 #define HTT_MSDU_FLOW_STATS_TID_NUM_M 0x000f0000 1520 #define HTT_MSDU_FLOW_STATS_TID_NUM_S 16 1521 #define HTT_MSDU_FLOW_STATS_DROP_M 0x00100000 1522 #define HTT_MSDU_FLOW_STATS_DROP_S 20 1523 1524 #define HTT_MSDU_FLOW_STATS_TX_FLOW_NUM_GET(_var) \ 1525 (((_var) & HTT_MSDU_FLOW_STATS_TX_FLOW_NUM_M) >> \ 1526 HTT_MSDU_FLOW_STATS_TX_FLOW_NUM_S) 1527 1528 #define HTT_MSDU_FLOW_STATS_TX_FLOW_NUM_SET(_var, _val) \ 1529 do { \ 1530 HTT_CHECK_SET_VAL(HTT_MSDU_FLOW_STATS_TX_FLOW_NUM, _val); \ 1531 ((_var) |= ((_val) << HTT_MSDU_FLOW_STATS_TX_FLOW_NUM_S)); \ 1532 } while (0) 1533 1534 #define HTT_MSDU_FLOW_STATS_TID_NUM_GET(_var) \ 1535 (((_var) & HTT_MSDU_FLOW_STATS_TID_NUM_M) >> \ 1536 HTT_MSDU_FLOW_STATS_TID_NUM_S) 1537 1538 #define HTT_MSDU_FLOW_STATS_TID_NUM_SET(_var, _val) \ 1539 do { \ 1540 HTT_CHECK_SET_VAL(HTT_MSDU_FLOW_STATS_TID_NUM, _val); \ 1541 ((_var) |= ((_val) << HTT_MSDU_FLOW_STATS_TID_NUM_S)); \ 1542 } while (0) 1543 1544 #define HTT_MSDU_FLOW_STATS_DROP_GET(_var) \ 1545 (((_var) & HTT_MSDU_FLOW_STATS_DROP_M) >> \ 1546 HTT_MSDU_FLOW_STATS_DROP_S) 1547 1548 #define HTT_MSDU_FLOW_STATS_DROP_SET(_var, _val) \ 1549 do { \ 1550 HTT_CHECK_SET_VAL(HTT_MSDU_FLOW_STATS_DROP, _val); \ 1551 ((_var) |= ((_val) << HTT_MSDU_FLOW_STATS_DROP_S)); \ 1552 } while (0) 1553 1554 typedef struct _htt_msdu_flow_stats_tlv { 1555 htt_tlv_hdr_t tlv_hdr; 1556 1557 A_UINT32 last_update_timestamp; 1558 A_UINT32 last_add_timestamp; 1559 A_UINT32 last_remove_timestamp; 1560 A_UINT32 total_processed_msdu_count; 1561 A_UINT32 cur_msdu_count_in_flowq; 1562 /** This will help to find which peer_id is stuck state */ 1563 A_UINT32 sw_peer_id; 1564 /** 1565 * BIT [15 : 0] :- tx_flow_number 1566 * BIT [19 : 16] :- tid_num 1567 * BIT [20 : 20] :- drop_rule 1568 * BIT [31 : 21] :- reserved 1569 */ 1570 A_UINT32 tx_flow_no__tid_num__drop_rule; 1571 A_UINT32 last_cycle_enqueue_count; 1572 A_UINT32 last_cycle_dequeue_count; 1573 A_UINT32 last_cycle_drop_count; 1574 /** 1575 * BIT [15 : 0] :- current_drop_th 1576 * BIT [31 : 16] :- reserved 1577 */ 1578 A_UINT32 current_drop_th; 1579 } htt_stats_peer_msdu_flowq_tlv; 1580 /* preserve old name alias for new name consistent with the tag name */ 1581 typedef htt_stats_peer_msdu_flowq_tlv htt_msdu_flow_stats_tlv; 1582 1583 #define MAX_HTT_TID_NAME 8 1584 1585 /* DWORD sw_peer_id__tid_num */ 1586 #define HTT_TX_TID_STATS_SW_PEER_ID_M 0x0000ffff 1587 #define HTT_TX_TID_STATS_SW_PEER_ID_S 0 1588 #define HTT_TX_TID_STATS_TID_NUM_M 0xffff0000 1589 #define HTT_TX_TID_STATS_TID_NUM_S 16 1590 1591 #define HTT_TX_TID_STATS_SW_PEER_ID_GET(_var) \ 1592 (((_var) & HTT_TX_TID_STATS_SW_PEER_ID_M) >> \ 1593 HTT_TX_TID_STATS_SW_PEER_ID_S) 1594 1595 #define HTT_TX_TID_STATS_SW_PEER_ID_SET(_var, _val) \ 1596 do { \ 1597 HTT_CHECK_SET_VAL(HTT_TX_TID_STATS_SW_PEER_ID, _val); \ 1598 ((_var) |= ((_val) << HTT_TX_TID_STATS_SW_PEER_ID_S)); \ 1599 } while (0) 1600 1601 #define HTT_TX_TID_STATS_TID_NUM_GET(_var) \ 1602 (((_var) & HTT_TX_TID_STATS_TID_NUM_M) >> \ 1603 HTT_TX_TID_STATS_TID_NUM_S) 1604 1605 #define HTT_TX_TID_STATS_TID_NUM_SET(_var, _val) \ 1606 do { \ 1607 HTT_CHECK_SET_VAL(HTT_TX_TID_STATS_TID_NUM, _val); \ 1608 ((_var) |= ((_val) << HTT_TX_TID_STATS_TID_NUM_S)); \ 1609 } while (0) 1610 1611 /* DWORD num_sched_pending__num_ppdu_in_hwq */ 1612 #define HTT_TX_TID_STATS_NUM_SCHED_PENDING_M 0x000000ff 1613 #define HTT_TX_TID_STATS_NUM_SCHED_PENDING_S 0 1614 #define HTT_TX_TID_STATS_NUM_PPDU_IN_HWQ_M 0x0000ff00 1615 #define HTT_TX_TID_STATS_NUM_PPDU_IN_HWQ_S 8 1616 1617 #define HTT_TX_TID_STATS_NUM_SCHED_PENDING_GET(_var) \ 1618 (((_var) & HTT_TX_TID_STATS_NUM_SCHED_PENDING_M) >> \ 1619 HTT_TX_TID_STATS_NUM_SCHED_PENDING_S) 1620 1621 #define HTT_TX_TID_STATS_NUM_SCHED_PENDING_SET(_var, _val) \ 1622 do { \ 1623 HTT_CHECK_SET_VAL(HTT_TX_TID_STATS_NUM_SCHED_PENDING, _val); \ 1624 ((_var) |= ((_val) << HTT_TX_TID_STATS_NUM_SCHED_PENDING_S)); \ 1625 } while (0) 1626 1627 #define HTT_TX_TID_STATS_NUM_PPDU_IN_HWQ_GET(_var) \ 1628 (((_var) & HTT_TX_TID_STATS_NUM_PPDU_IN_HWQ_M) >> \ 1629 HTT_TX_TID_STATS_NUM_PPDU_IN_HWQ_S) 1630 1631 #define HTT_TX_TID_STATS_NUM_PPDU_IN_HWQ_SET(_var, _val) \ 1632 do { \ 1633 HTT_CHECK_SET_VAL(HTT_TX_TID_STATS_NUM_PPDU_IN_HWQ, _val); \ 1634 ((_var) |= ((_val) << HTT_TX_TID_STATS_NUM_PPDU_IN_HWQ_S)); \ 1635 } while (0) 1636 1637 /* Tidq stats */ 1638 typedef struct _htt_tx_tid_stats_tlv { 1639 htt_tlv_hdr_t tlv_hdr; 1640 1641 /** Stored as little endian */ 1642 A_UINT8 tid_name[MAX_HTT_TID_NAME]; 1643 /** 1644 * BIT [15 : 0] :- sw_peer_id 1645 * BIT [31 : 16] :- tid_num 1646 */ 1647 A_UINT32 sw_peer_id__tid_num; 1648 /** 1649 * BIT [ 7 : 0] :- num_sched_pending 1650 * BIT [15 : 8] :- num_ppdu_in_hwq 1651 * BIT [31 : 16] :- reserved 1652 */ 1653 A_UINT32 num_sched_pending__num_ppdu_in_hwq; 1654 A_UINT32 tid_flags; 1655 /** per tid # of hw_queued ppdu */ 1656 A_UINT32 hw_queued; 1657 /** number of per tid successful PPDU */ 1658 A_UINT32 hw_reaped; 1659 /** per tid Num MPDUs filtered by HW */ 1660 A_UINT32 mpdus_hw_filter; 1661 1662 A_UINT32 qdepth_bytes; 1663 A_UINT32 qdepth_num_msdu; 1664 A_UINT32 qdepth_num_mpdu; 1665 A_UINT32 last_scheduled_tsmp; 1666 A_UINT32 pause_module_id; 1667 A_UINT32 block_module_id; 1668 /** tid tx airtime in sec */ 1669 A_UINT32 tid_tx_airtime; 1670 } htt_stats_tx_tid_details_tlv; 1671 /* preserve old name alias for new name consistent with the tag name */ 1672 typedef htt_stats_tx_tid_details_tlv htt_tx_tid_stats_tlv; 1673 1674 /* Tidq stats */ 1675 typedef struct _htt_tx_tid_stats_v1_tlv { 1676 htt_tlv_hdr_t tlv_hdr; 1677 /** Stored as little endian */ 1678 A_UINT8 tid_name[MAX_HTT_TID_NAME]; 1679 /** 1680 * BIT [15 : 0] :- sw_peer_id 1681 * BIT [31 : 16] :- tid_num 1682 */ 1683 A_UINT32 sw_peer_id__tid_num; 1684 /** 1685 * BIT [ 7 : 0] :- num_sched_pending 1686 * BIT [15 : 8] :- num_ppdu_in_hwq 1687 * BIT [31 : 16] :- reserved 1688 */ 1689 A_UINT32 num_sched_pending__num_ppdu_in_hwq; 1690 A_UINT32 tid_flags; 1691 /** Max qdepth in bytes reached by this tid */ 1692 A_UINT32 max_qdepth_bytes; 1693 /** number of msdus qdepth reached max */ 1694 A_UINT32 max_qdepth_n_msdus; 1695 A_UINT32 rsvd; 1696 1697 A_UINT32 qdepth_bytes; 1698 A_UINT32 qdepth_num_msdu; 1699 A_UINT32 qdepth_num_mpdu; 1700 A_UINT32 last_scheduled_tsmp; 1701 A_UINT32 pause_module_id; 1702 A_UINT32 block_module_id; 1703 /** tid tx airtime in sec */ 1704 A_UINT32 tid_tx_airtime; 1705 A_UINT32 allow_n_flags; 1706 /** 1707 * BIT [15 : 0] :- sendn_frms_allowed 1708 * BIT [31 : 16] :- reserved 1709 */ 1710 A_UINT32 sendn_frms_allowed; 1711 /* 1712 * tid_ext_flags, tid_ext2_flags, and tid_flush_reason are opaque fields 1713 * that cannot be interpreted by the host. 1714 * They are only for off-line debug. 1715 */ 1716 A_UINT32 tid_ext_flags; 1717 A_UINT32 tid_ext2_flags; 1718 A_UINT32 tid_flush_reason; 1719 A_UINT32 mlo_flush_tqm_status_pending_low; 1720 A_UINT32 mlo_flush_tqm_status_pending_high; 1721 A_UINT32 mlo_flush_partner_info_low; 1722 A_UINT32 mlo_flush_partner_info_high; 1723 A_UINT32 mlo_flush_initator_info_low; 1724 A_UINT32 mlo_flush_initator_info_high; 1725 /* 1726 * head_msdu_tqm_timestamp_us: 1727 * MSDU enqueue timestamp (TQM reference timestamp) for the MSDU 1728 * at the head of the MPDU queue 1729 * head_msdu_tqm_latency_us: 1730 * The age of the MSDU that is at the head of the MPDU queue, 1731 * i.e. the delta between the current TQM time and the MSDU's 1732 * enqueue timestamp. 1733 */ 1734 A_UINT32 head_msdu_tqm_timestamp_us; 1735 A_UINT32 head_msdu_tqm_latency_us; 1736 } htt_stats_tx_tid_details_v1_tlv; 1737 /* preserve old name alias for new name consistent with the tag name */ 1738 typedef htt_stats_tx_tid_details_v1_tlv htt_tx_tid_stats_v1_tlv; 1739 1740 #define HTT_RX_TID_STATS_SW_PEER_ID_M 0x0000ffff 1741 #define HTT_RX_TID_STATS_SW_PEER_ID_S 0 1742 #define HTT_RX_TID_STATS_TID_NUM_M 0xffff0000 1743 #define HTT_RX_TID_STATS_TID_NUM_S 16 1744 1745 #define HTT_RX_TID_STATS_SW_PEER_ID_GET(_var) \ 1746 (((_var) & HTT_RX_TID_STATS_SW_PEER_ID_M) >> \ 1747 HTT_RX_TID_STATS_SW_PEER_ID_S) 1748 1749 #define HTT_RX_TID_STATS_SW_PEER_ID_SET(_var, _val) \ 1750 do { \ 1751 HTT_CHECK_SET_VAL(HTT_RX_TID_STATS_SW_PEER_ID, _val); \ 1752 ((_var) |= ((_val) << HTT_RX_TID_STATS_SW_PEER_ID_S)); \ 1753 } while (0) 1754 1755 #define HTT_RX_TID_STATS_TID_NUM_GET(_var) \ 1756 (((_var) & HTT_RX_TID_STATS_TID_NUM_M) >> \ 1757 HTT_RX_TID_STATS_TID_NUM_S) 1758 1759 #define HTT_RX_TID_STATS_TID_NUM_SET(_var, _val) \ 1760 do { \ 1761 HTT_CHECK_SET_VAL(HTT_RX_TID_STATS_TID_NUM, _val); \ 1762 ((_var) |= ((_val) << HTT_RX_TID_STATS_TID_NUM_S)); \ 1763 } while (0) 1764 1765 typedef struct _htt_rx_tid_stats_tlv { 1766 htt_tlv_hdr_t tlv_hdr; 1767 1768 /** 1769 * BIT [15 : 0] : sw_peer_id 1770 * BIT [31 : 16] : tid_num 1771 */ 1772 A_UINT32 sw_peer_id__tid_num; 1773 /** Stored as little endian */ 1774 A_UINT8 tid_name[MAX_HTT_TID_NAME]; 1775 /** 1776 * dup_in_reorder not collected per tid for now, 1777 * as there is no wal_peer back ptr in data rx peer. 1778 */ 1779 A_UINT32 dup_in_reorder; 1780 A_UINT32 dup_past_outside_window; 1781 A_UINT32 dup_past_within_window; 1782 /** Number of per tid MSDUs with flag of decrypt_err */ 1783 A_UINT32 rxdesc_err_decrypt; 1784 /** tid rx airtime in sec */ 1785 A_UINT32 tid_rx_airtime; 1786 } htt_stats_rx_tid_details_tlv; 1787 /* preserve old name alias for new name consistent with the tag name */ 1788 typedef htt_stats_rx_tid_details_tlv htt_rx_tid_stats_tlv; 1789 1790 #define HTT_MAX_COUNTER_NAME 8 1791 typedef struct { 1792 htt_tlv_hdr_t tlv_hdr; 1793 /** Stored as little endian */ 1794 A_UINT8 counter_name[HTT_MAX_COUNTER_NAME]; 1795 A_UINT32 count; 1796 } htt_stats_counter_name_tlv; 1797 /* preserve old name alias for new name consistent with the tag name */ 1798 typedef htt_stats_counter_name_tlv htt_counter_tlv; 1799 1800 typedef struct { 1801 htt_tlv_hdr_t tlv_hdr; 1802 /** Number of rx PPDU */ 1803 A_UINT32 ppdu_cnt; 1804 /** Number of rx MPDU */ 1805 A_UINT32 mpdu_cnt; 1806 /** Number of rx MSDU */ 1807 A_UINT32 msdu_cnt; 1808 /** pause bitmap */ 1809 A_UINT32 pause_bitmap; 1810 /** block bitmap */ 1811 A_UINT32 block_bitmap; 1812 /** current timestamp */ 1813 A_UINT32 current_timestamp; 1814 /** Peer cumulative tx airtime in sec */ 1815 A_UINT32 peer_tx_airtime; 1816 /** Peer cumulative rx airtime in sec */ 1817 A_UINT32 peer_rx_airtime; 1818 /** Peer current rssi in dBm */ 1819 A_INT32 rssi; 1820 /** Total enqueued, dequeued and dropped MSDU's for peer */ 1821 A_UINT32 peer_enqueued_count_low; 1822 A_UINT32 peer_enqueued_count_high; 1823 A_UINT32 peer_dequeued_count_low; 1824 A_UINT32 peer_dequeued_count_high; 1825 A_UINT32 peer_dropped_count_low; 1826 A_UINT32 peer_dropped_count_high; 1827 /** Total ppdu transmitted bytes for peer: includes MAC header overhead */ 1828 A_UINT32 ppdu_transmitted_bytes_low; 1829 A_UINT32 ppdu_transmitted_bytes_high; 1830 A_UINT32 peer_ttl_removed_count; 1831 /** 1832 * inactive_time 1833 * Running duration of the time since last tx/rx activity by this peer, 1834 * units = seconds. 1835 * If the peer is currently active, this inactive_time will be 0x0. 1836 */ 1837 A_UINT32 inactive_time; 1838 /** Number of MPDUs dropped after max retries */ 1839 A_UINT32 remove_mpdus_max_retries; 1840 } htt_stats_peer_stats_cmn_tlv; 1841 /* preserve old name alias for new name consistent with the tag name */ 1842 typedef htt_stats_peer_stats_cmn_tlv htt_peer_stats_cmn_tlv; 1843 1844 #define HTT_PEER_DETAILS_ML_PEER_OFFSET_BYTES 32 1845 #define HTT_PEER_DETAILS_ML_PEER_OFFSET_DWORD 8 1846 #define HTT_PEER_DETAILS_ML_PEER_ID_VALID_M 0x00000001 1847 #define HTT_PEER_DETAILS_ML_PEER_ID_VALID_S 0 1848 #define HTT_PEER_DETAILS_ML_PEER_ID_M 0x00001ffe 1849 #define HTT_PEER_DETAILS_ML_PEER_ID_S 1 1850 #define HTT_PEER_DETAILS_LINK_IDX_M 0x001fe000 1851 #define HTT_PEER_DETAILS_LINK_IDX_S 13 1852 #define HTT_PEER_DETAILS_USE_PPE_M 0x00200000 1853 #define HTT_PEER_DETAILS_USE_PPE_S 21 1854 1855 1856 #define HTT_PEER_DETAILS_SRC_INFO_M 0x00000fff 1857 #define HTT_PEER_DETAILS_SRC_INFO_S 0 1858 1859 1860 #define HTT_PEER_DETAILS_SET(word, httsym, val) \ 1861 do { \ 1862 HTT_CHECK_SET_VAL(HTT_PEER_DETAILS_ ## httsym, val); \ 1863 (word) |= ((val) << HTT_PEER_DETAILS_ ## httsym ## _S); \ 1864 } while(0) 1865 1866 #define HTT_PEER_DETAILS_GET(word, httsym) \ 1867 (((word) & HTT_PEER_DETAILS_ ## httsym ## _M) >> HTT_PEER_DETAILS_ ## httsym ## _S) 1868 1869 typedef struct { 1870 htt_tlv_hdr_t tlv_hdr; 1871 /** This enum type of HTT_PEER_TYPE */ 1872 A_UINT32 peer_type; 1873 A_UINT32 sw_peer_id; 1874 /** 1875 * BIT [7 : 0] :- vdev_id 1876 * BIT [15 : 8] :- pdev_id 1877 * BIT [31 : 16] :- ast_indx 1878 */ 1879 A_UINT32 vdev_pdev_ast_idx; 1880 htt_mac_addr mac_addr; 1881 A_UINT32 peer_flags; 1882 A_UINT32 qpeer_flags; 1883 1884 /* Dword 8 */ 1885 union { 1886 A_UINT32 word__ml_peer_id_valid__ml_peer_id__link_idx__use_ppe; 1887 struct { 1888 A_UINT32 ml_peer_id_valid : 1, /* [0:0] */ 1889 ml_peer_id : 12, /* [12:1] */ 1890 link_idx : 8, /* [20:13] */ 1891 use_ppe : 1, /* [21:21] */ 1892 rsvd0 : 10; /* [31:22] */ 1893 }; 1894 }; 1895 1896 /* Dword 9 */ 1897 union { 1898 A_UINT32 word__src_info; 1899 struct { 1900 A_UINT32 src_info : 12, /* [11:0] */ 1901 rsvd1 : 20; /* [31:12] */ 1902 }; 1903 }; 1904 } htt_stats_peer_details_tlv; 1905 /* preserve old name alias for new name consistent with the tag name */ 1906 typedef htt_stats_peer_details_tlv htt_peer_details_tlv; 1907 1908 #define HTT_STATS_PEER_DETAILS_ML_PEER_ID_VALID_GET(word) ((word >> 0) & 0x1) 1909 #define HTT_STATS_PEER_DETAILS_ML_PEER_ID_GET(word) ((word >> 1) & 0xfff) 1910 #define HTT_STATS_PEER_DETAILS_LINK_IDX_GET(word) ((word >> 13) & 0xff) 1911 #define HTT_STATS_PEER_DETAILS_USE_PPE_GET(word) ((word >> 21) & 0x1) 1912 1913 #define HTT_STATS_PEER_DETAILS_SRC_INFO_GET(word) ((word >> 0) & 0xfff) 1914 1915 typedef struct { 1916 htt_tlv_hdr_t tlv_hdr; 1917 A_UINT32 sw_peer_id; 1918 A_UINT32 ast_index; 1919 htt_mac_addr mac_addr; 1920 A_UINT32 1921 pdev_id : 2, 1922 vdev_id : 8, 1923 next_hop : 1, 1924 mcast : 1, 1925 monitor_direct : 1, 1926 mesh_sta : 1, 1927 mec : 1, 1928 intra_bss : 1, 1929 chip_id : 2, 1930 ml_peer_id : 13, 1931 on_chip : 1; 1932 A_UINT32 1933 tx_monitor_override_sta : 1, 1934 rx_monitor_override_sta : 1, 1935 reserved1 : 30; 1936 } htt_stats_ast_entry_tlv; 1937 /* preserve old name alias for new name consistent with the tag name */ 1938 typedef htt_stats_ast_entry_tlv htt_ast_entry_tlv; 1939 1940 typedef enum { 1941 HTT_STATS_DIRECTION_TX, 1942 HTT_STATS_DIRECTION_RX, 1943 } HTT_STATS_DIRECTION; 1944 1945 typedef enum { 1946 HTT_STATS_PPDU_TYPE_MODE_SU, 1947 HTT_STATS_PPDU_TYPE_DL_MU_MIMO, 1948 HTT_STATS_PPDU_TYPE_UL_MU_MIMO, 1949 HTT_STATS_PPDU_TYPE_DL_MU_OFDMA, 1950 HTT_STATS_PPDU_TYPE_UL_MU_OFDMA, 1951 } HTT_STATS_PPDU_TYPE; 1952 1953 typedef enum { 1954 HTT_STATS_PREAM_OFDM, 1955 HTT_STATS_PREAM_CCK, 1956 HTT_STATS_PREAM_HT, 1957 HTT_STATS_PREAM_VHT, 1958 HTT_STATS_PREAM_HE, 1959 HTT_STATS_PREAM_EHT, 1960 HTT_STATS_PREAM_RSVD1, 1961 1962 HTT_STATS_PREAM_COUNT, 1963 } HTT_STATS_PREAM_TYPE; 1964 1965 #define HTT_TX_PEER_STATS_NUM_MCS_COUNTERS 12 /* 0-11 */ 1966 #define HTT_TX_PEER_STATS_NUM_EXTRA_MCS_COUNTERS 2 /* 12, 13 */ 1967 #define HTT_TX_PEER_STATS_NUM_EXTRA2_MCS_COUNTERS 2 /* 14, 15 */ 1968 /* HTT_TX_PEER_STATS_NUM_GI_COUNTERS: 1969 * GI Index 0: WHAL_GI_800 1970 * GI Index 1: WHAL_GI_400 1971 * GI Index 2: WHAL_GI_1600 1972 * GI Index 3: WHAL_GI_3200 1973 */ 1974 #define HTT_TX_PEER_STATS_NUM_GI_COUNTERS 4 1975 #define HTT_TX_PEER_STATS_NUM_DCM_COUNTERS 5 1976 /* HTT_TX_PEER_STATS_NUM_BW_COUNTERS: 1977 * bw index 0: rssi_pri20_chain0 1978 * bw index 1: rssi_ext20_chain0 1979 * bw index 2: rssi_ext40_low20_chain0 1980 * bw index 3: rssi_ext40_high20_chain0 1981 */ 1982 #define HTT_TX_PEER_STATS_NUM_BW_COUNTERS 4 1983 /* HTT_RX_PEER_STATS_NUM_BW_EXT_COUNTERS: 1984 * bw index 4 (bw ext index 0): rssi_ext80_low20_chain0 1985 * bw index 5 (bw ext index 1): rssi_ext80_low_high20_chain0 1986 * bw index 6 (bw ext index 2): rssi_ext80_high_low20_chain0 1987 * bw index 7 (bw ext index 3): rssi_ext80_high20_chain0 1988 */ 1989 #define HTT_RX_PEER_STATS_NUM_BW_EXT_COUNTERS 4 1990 #define HTT_RX_PDEV_STATS_NUM_BW_EXT_COUNTERS 4 1991 1992 /* HTT_RX STATS_NUM_BW_EXT_2_COUNTERS: 1993 * bw index 8 (bw ext_2 index 0): rssi_ext160_0_chainX 1994 * bw index 9 (bw ext_2 index 1): rssi_ext160_1_chainX 1995 * bw index 10 (bw ext_2 index 2): rssi_ext160_2_chainX 1996 * bw index 11 (bw ext_2 index 3): rssi_ext160_3_chainX 1997 * bw index 12 (bw ext_2 index 4): rssi_ext160_4_chainX 1998 * bw index 13 (bw ext_2 index 5): rssi_ext160_5_chainX 1999 * bw index 14 (bw ext_2 index 6): rssi_ext160_6_chainX 2000 * bw index 15 (bw ext_2 index 7): rssi_ext160_7_chainX 2001 */ 2002 #define HTT_RX_PDEV_STATS_NUM_BW_EXT_2_COUNTERS 8 2003 2004 #define HTT_TX_PEER_STATS_NUM_SPATIAL_STREAMS 8 2005 #define HTT_TX_PEER_STATS_NUM_PREAMBLE_TYPES HTT_STATS_PREAM_COUNT 2006 #define HTT_TX_PEER_STATS_NUM_REDUCED_CHAN_TYPES 2 /* 0 - Half, 1 - Quarter */ 2007 2008 typedef struct _htt_tx_peer_rate_stats_tlv { 2009 htt_tlv_hdr_t tlv_hdr; 2010 2011 /** Number of tx LDPC packets */ 2012 A_UINT32 tx_ldpc; 2013 /** Number of tx RTS packets */ 2014 A_UINT32 rts_cnt; 2015 /** RSSI value of last ack packet (units = dB above noise floor) */ 2016 A_UINT32 ack_rssi; 2017 2018 A_UINT32 tx_mcs[HTT_TX_PEER_STATS_NUM_MCS_COUNTERS]; 2019 A_UINT32 tx_su_mcs[HTT_TX_PEER_STATS_NUM_MCS_COUNTERS]; 2020 A_UINT32 tx_mu_mcs[HTT_TX_PEER_STATS_NUM_MCS_COUNTERS]; 2021 /** 2022 * element 0,1, ...7 -> NSS 1,2, ...8 2023 */ 2024 A_UINT32 tx_nss[HTT_TX_PEER_STATS_NUM_SPATIAL_STREAMS]; 2025 /** 2026 * element 0: 20 MHz, 1: 40 MHz, 2: 80 MHz, 3: 160 and 80+80 MHz 2027 */ 2028 A_UINT32 tx_bw[HTT_TX_PEER_STATS_NUM_BW_COUNTERS]; 2029 A_UINT32 tx_stbc[HTT_TX_PEER_STATS_NUM_MCS_COUNTERS]; 2030 A_UINT32 tx_pream[HTT_TX_PEER_STATS_NUM_PREAMBLE_TYPES]; 2031 2032 /** 2033 * Counters to track number of tx packets in each GI 2034 * (400us, 800us, 1600us & 3200us) in each mcs (0-11) 2035 */ 2036 A_UINT32 tx_gi[HTT_TX_PEER_STATS_NUM_GI_COUNTERS][HTT_TX_PEER_STATS_NUM_MCS_COUNTERS]; 2037 2038 /** Counters to track packets in dcm mcs (MCS 0, 1, 3, 4) */ 2039 A_UINT32 tx_dcm[HTT_TX_PEER_STATS_NUM_DCM_COUNTERS]; 2040 2041 /** Stats for MCS 12/13 */ 2042 A_UINT32 tx_mcs_ext[HTT_TX_PEER_STATS_NUM_EXTRA_MCS_COUNTERS]; 2043 A_UINT32 tx_su_mcs_ext[HTT_TX_PEER_STATS_NUM_EXTRA_MCS_COUNTERS]; 2044 A_UINT32 tx_mu_mcs_ext[HTT_TX_PEER_STATS_NUM_EXTRA_MCS_COUNTERS]; 2045 A_UINT32 tx_stbc_ext[HTT_TX_PEER_STATS_NUM_EXTRA_MCS_COUNTERS]; 2046 A_UINT32 tx_gi_ext[HTT_TX_PEER_STATS_NUM_GI_COUNTERS][HTT_TX_PEER_STATS_NUM_EXTRA_MCS_COUNTERS]; 2047 A_UINT32 reduced_tx_bw[HTT_TX_PEER_STATS_NUM_REDUCED_CHAN_TYPES][HTT_TX_PEER_STATS_NUM_BW_COUNTERS]; 2048 A_UINT32 tx_bw_320mhz; 2049 /* MCS 14,15 */ 2050 A_UINT32 tx_mcs_ext_2[HTT_TX_PEER_STATS_NUM_EXTRA2_MCS_COUNTERS]; 2051 } htt_stats_peer_tx_rate_stats_tlv; 2052 /* preserve old name alias for new name consistent with the tag name */ 2053 typedef htt_stats_peer_tx_rate_stats_tlv htt_tx_peer_rate_stats_tlv; 2054 2055 #define HTT_RX_PEER_STATS_NUM_MCS_COUNTERS 12 /* 0-11 */ 2056 #define HTT_RX_PEER_STATS_NUM_EXTRA_MCS_COUNTERS 2 /* 12, 13 */ 2057 #define HTT_RX_PEER_STATS_NUM_EXTRA2_MCS_COUNTERS 2 /* 14, 15 */ 2058 #define HTT_RX_PEER_STATS_NUM_GI_COUNTERS 4 2059 #define HTT_RX_PEER_STATS_NUM_DCM_COUNTERS 5 2060 #define HTT_RX_PEER_STATS_NUM_BW_COUNTERS 4 2061 #define HTT_RX_PEER_STATS_NUM_SPATIAL_STREAMS 8 2062 #define HTT_RX_PEER_STATS_NUM_PREAMBLE_TYPES HTT_STATS_PREAM_COUNT 2063 #define HTT_RX_PEER_STATS_NUM_REDUCED_CHAN_TYPES 2 /* 0 - Half, 1 - Quarter */ 2064 2065 typedef struct _htt_rx_peer_rate_stats_tlv { 2066 htt_tlv_hdr_t tlv_hdr; 2067 A_UINT32 nsts; 2068 2069 /** Number of rx LDPC packets */ 2070 A_UINT32 rx_ldpc; 2071 /** Number of rx RTS packets */ 2072 A_UINT32 rts_cnt; 2073 2074 /** units = dB above noise floor */ 2075 A_UINT32 rssi_mgmt; 2076 /** units = dB above noise floor */ 2077 A_UINT32 rssi_data; 2078 /** units = dB above noise floor */ 2079 A_UINT32 rssi_comb; 2080 A_UINT32 rx_mcs[HTT_RX_PEER_STATS_NUM_MCS_COUNTERS]; 2081 /** 2082 * element 0,1, ...7 -> NSS 1,2, ...8 2083 */ 2084 A_UINT32 rx_nss[HTT_RX_PEER_STATS_NUM_SPATIAL_STREAMS]; 2085 A_UINT32 rx_dcm[HTT_RX_PEER_STATS_NUM_DCM_COUNTERS]; 2086 A_UINT32 rx_stbc[HTT_RX_PEER_STATS_NUM_MCS_COUNTERS]; 2087 /** 2088 * element 0: 20 MHz, 1: 40 MHz, 2: 80 MHz, 3: 160 and 80+80 MHz 2089 */ 2090 A_UINT32 rx_bw[HTT_RX_PEER_STATS_NUM_BW_COUNTERS]; 2091 A_UINT32 rx_pream[HTT_RX_PEER_STATS_NUM_PREAMBLE_TYPES]; 2092 /** units = dB above noise floor */ 2093 A_UINT8 rssi_chain[HTT_RX_PEER_STATS_NUM_SPATIAL_STREAMS][HTT_RX_PEER_STATS_NUM_BW_COUNTERS]; 2094 2095 /** Counters to track number of rx packets in each GI in each mcs (0-11) */ 2096 A_UINT32 rx_gi[HTT_RX_PEER_STATS_NUM_GI_COUNTERS][HTT_RX_PEER_STATS_NUM_MCS_COUNTERS]; 2097 2098 A_UINT32 rx_ulofdma_non_data_ppdu; /** PPDU level */ 2099 A_UINT32 rx_ulofdma_data_ppdu; /** PPDU level */ 2100 A_UINT32 rx_ulofdma_mpdu_ok; /** MPDU level */ 2101 A_UINT32 rx_ulofdma_mpdu_fail; /** MPDU level */ 2102 A_INT8 rx_ul_fd_rssi[HTT_RX_PEER_STATS_NUM_SPATIAL_STREAMS]; /* dBm unit */ 2103 /* per_chain_rssi_pkt_type: 2104 * This field shows what type of rx frame the per-chain RSSI was computed 2105 * on, by recording the frame type and sub-type as bit-fields within this 2106 * field: 2107 * BIT [3 : 0] :- IEEE80211_FC0_TYPE 2108 * BIT [7 : 4] :- IEEE80211_FC0_SUBTYPE 2109 * BIT [31 : 8] :- Reserved 2110 */ 2111 A_UINT32 per_chain_rssi_pkt_type; 2112 A_INT8 rx_per_chain_rssi_in_dbm[HTT_RX_PEER_STATS_NUM_SPATIAL_STREAMS][HTT_RX_PEER_STATS_NUM_BW_COUNTERS]; 2113 2114 /** PPDU level */ 2115 A_UINT32 rx_ulmumimo_non_data_ppdu; 2116 /** PPDU level */ 2117 A_UINT32 rx_ulmumimo_data_ppdu; 2118 /** MPDU level */ 2119 A_UINT32 rx_ulmumimo_mpdu_ok; 2120 /** mpdu level */ 2121 A_UINT32 rx_ulmumimo_mpdu_fail; 2122 2123 /** units = dB above noise floor */ 2124 A_UINT8 rssi_chain_ext[HTT_RX_PEER_STATS_NUM_SPATIAL_STREAMS][HTT_RX_PEER_STATS_NUM_BW_EXT_COUNTERS]; 2125 2126 /** Stats for MCS 12/13 */ 2127 A_UINT32 rx_mcs_ext[HTT_RX_PEER_STATS_NUM_EXTRA_MCS_COUNTERS]; 2128 A_UINT32 rx_stbc_ext[HTT_RX_PEER_STATS_NUM_EXTRA_MCS_COUNTERS]; 2129 A_UINT32 rx_gi_ext[HTT_RX_PEER_STATS_NUM_GI_COUNTERS][HTT_RX_PEER_STATS_NUM_EXTRA_MCS_COUNTERS]; 2130 A_UINT32 reduced_rx_bw[HTT_RX_PEER_STATS_NUM_REDUCED_CHAN_TYPES][HTT_RX_PEER_STATS_NUM_BW_COUNTERS]; 2131 A_INT8 rx_per_chain_rssi_in_dbm_ext[HTT_RX_PEER_STATS_NUM_SPATIAL_STREAMS][HTT_RX_PEER_STATS_NUM_BW_EXT_COUNTERS]; 2132 A_UINT32 rx_bw_320mhz; 2133 /* MCS 14,15 */ 2134 A_UINT32 rx_mcs_ext_2[HTT_RX_PEER_STATS_NUM_EXTRA2_MCS_COUNTERS]; 2135 } htt_stats_peer_rx_rate_stats_tlv; 2136 /* preserve old name alias for new name consistent with the tag name */ 2137 typedef htt_stats_peer_rx_rate_stats_tlv htt_rx_peer_rate_stats_tlv; 2138 2139 typedef enum { 2140 HTT_PEER_STATS_REQ_MODE_NO_QUERY, 2141 HTT_PEER_STATS_REQ_MODE_QUERY_TQM, 2142 HTT_PEER_STATS_REQ_MODE_FLUSH_TQM, 2143 } htt_peer_stats_req_mode_t; 2144 2145 typedef enum { 2146 HTT_PEER_STATS_CMN_TLV = 0, 2147 HTT_PEER_DETAILS_TLV = 1, 2148 HTT_TX_PEER_RATE_STATS_TLV = 2, 2149 HTT_RX_PEER_RATE_STATS_TLV = 3, 2150 HTT_TX_TID_STATS_TLV = 4, 2151 HTT_RX_TID_STATS_TLV = 5, 2152 HTT_MSDU_FLOW_STATS_TLV = 6, 2153 HTT_PEER_SCHED_STATS_TLV = 7, 2154 HTT_PEER_AX_OFDMA_STATS_TLV = 8, 2155 HTT_PEER_BE_OFDMA_STATS_TLV = 9, 2156 2157 HTT_PEER_STATS_MAX_TLV = 31, 2158 } htt_peer_stats_tlv_enum; 2159 2160 typedef struct { 2161 htt_tlv_hdr_t tlv_hdr; 2162 A_UINT32 peer_id; 2163 /** Num of DL schedules for peer */ 2164 A_UINT32 num_sched_dl; 2165 /** Num od UL schedules for peer */ 2166 A_UINT32 num_sched_ul; 2167 /** Peer TX time */ 2168 A_UINT32 peer_tx_active_dur_us_low; 2169 A_UINT32 peer_tx_active_dur_us_high; 2170 /** Peer RX time */ 2171 A_UINT32 peer_rx_active_dur_us_low; 2172 A_UINT32 peer_rx_active_dur_us_high; 2173 A_UINT32 peer_curr_rate_kbps; 2174 } htt_stats_peer_sched_stats_tlv; 2175 /* preserve old name alias for new name consistent with the tag name */ 2176 typedef htt_stats_peer_sched_stats_tlv htt_peer_sched_stats_tlv; 2177 2178 typedef struct { 2179 htt_tlv_hdr_t tlv_hdr; 2180 A_UINT32 peer_id; 2181 A_UINT32 ax_basic_trig_count; 2182 A_UINT32 ax_basic_trig_err; 2183 A_UINT32 ax_bsr_trig_count; 2184 A_UINT32 ax_bsr_trig_err; 2185 A_UINT32 ax_mu_bar_trig_count; 2186 A_UINT32 ax_mu_bar_trig_err; 2187 A_UINT32 ax_basic_trig_with_per; 2188 A_UINT32 ax_bsr_trig_with_per; 2189 A_UINT32 ax_mu_bar_trig_with_per; 2190 /* is_airtime_large_for_dl_ofdma, is_airtime_large_for_ul_ofdma 2191 * These fields contain 2 counters each. The first element in each 2192 * array counts how many times the airtime is short enough to use 2193 * OFDMA, and the second element in each array counts how many times the 2194 * airtime is too large to select OFDMA for the PPDUs involving the peer. 2195 */ 2196 A_UINT32 is_airtime_large_for_dl_ofdma[2]; 2197 A_UINT32 is_airtime_large_for_ul_ofdma[2]; 2198 /* Last updated value of DL and UL queue depths for each peer per AC */ 2199 A_UINT32 last_updated_dl_qdepth[HTT_NUM_AC_WMM]; 2200 A_UINT32 last_updated_ul_qdepth[HTT_NUM_AC_WMM]; 2201 /* Per peer Manual 11ax UL OFDMA trigger and trigger error counts */ 2202 A_UINT32 ax_manual_ulofdma_trig_count; 2203 A_UINT32 ax_manual_ulofdma_trig_err_count; 2204 } htt_stats_peer_ax_ofdma_stats_tlv; 2205 /* preserve old name alias for new name consistent with the tag name */ 2206 typedef htt_stats_peer_ax_ofdma_stats_tlv htt_peer_ax_ofdma_stats_tlv; 2207 2208 typedef struct { 2209 htt_tlv_hdr_t tlv_hdr; 2210 A_UINT32 peer_id; 2211 /* Per peer Manual 11be UL OFDMA trigger and trigger error counts */ 2212 A_UINT32 be_manual_ulofdma_trig_count; 2213 A_UINT32 be_manual_ulofdma_trig_err_count; 2214 } htt_stats_peer_be_ofdma_stats_tlv; 2215 /* preserve old name alias for new name consistent with the tag name */ 2216 typedef htt_stats_peer_be_ofdma_stats_tlv htt_peer_be_ofdma_stats_tlv; 2217 2218 2219 /* config_param0 */ 2220 2221 #define HTT_DBG_EXT_PEER_CTRL_PATH_TXRX_STATS_IS_MAC_ADDR_M 0x00000001 2222 #define HTT_DBG_EXT_PEER_CTRL_PATH_TXRX_STATS_IS_MAC_ADDR_S 0 2223 2224 #define HTT_DBG_EXT_PEER_CTRL_PATH_TXRX_STATS_IS_MAC_ADDR_GET(_var) \ 2225 (((_var) & HTT_DBG_EXT_PEER_CTRL_PATH_TXRX_STATS_IS_MAC_ADDR_M) >> \ 2226 HTT_DBG_EXT_PEER_CTRL_PATH_TXRX_STATS_IS_MAC_ADDR_S) 2227 2228 #define HTT_DBG_EXT_PEER_CTRL_PATH_TXRX_STATS_IS_MAC_ADDR_SET(_var, _val) \ 2229 do { \ 2230 HTT_CHECK_SET_VAL(HTT_DBG_EXT_PEER_CTRL_PATH_TXRX_STATS_IS_MAC_ADDR, _val); \ 2231 ((_var) |= ((_val) << HTT_DBG_EXT_PEER_CTRL_PATH_TXRX_STATS_IS_MAC_ADDR_S)); \ 2232 } while (0) 2233 /* DEPRECATED 2234 * The old IS_peer_MAC_ADDR_SET macro name is being retained for now, 2235 * as an alias for the corrected macro name. 2236 * If/when all references to the old name are removed, the definition of 2237 * the old name will also be removed. 2238 */ 2239 #define HTT_DBG_EXT_PEER_CTRL_PATH_TXRX_STATS_IS_peer_MAC_ADDR_SET HTT_DBG_EXT_PEER_CTRL_PATH_TXRX_STATS_IS_MAC_ADDR_SET 2240 2241 #define HTT_DBG_EXT_STATS_PEER_INFO_IS_MAC_ADDR_M 0x00000001 2242 #define HTT_DBG_EXT_STATS_PEER_INFO_IS_MAC_ADDR_S 0 2243 2244 #define HTT_DBG_EXT_STATS_PEER_REQ_MODE_M 0x0000FFFE 2245 #define HTT_DBG_EXT_STATS_PEER_REQ_MODE_S 1 2246 2247 #define HTT_DBG_EXT_STATS_PEER_INFO_SW_PEER_ID_M 0xFFFF0000 2248 #define HTT_DBG_EXT_STATS_PEER_INFO_SW_PEER_ID_S 16 2249 2250 #define HTT_DBG_EXT_STATS_PEER_INFO_IS_MAC_ADDR_SET(_var, _val) \ 2251 do { \ 2252 HTT_CHECK_SET_VAL(HTT_DBG_EXT_STATS_PEER_INFO_IS_MAC_ADDR, _val); \ 2253 ((_var) |= ((_val) << HTT_DBG_EXT_STATS_PEER_INFO_IS_MAC_ADDR_S)); \ 2254 } while (0) 2255 2256 #define HTT_DBG_EXT_STATS_PEER_INFO_IS_MAC_ADDR_GET(_var) \ 2257 (((_var) & HTT_DBG_EXT_STATS_PEER_INFO_IS_MAC_ADDR_M) >> \ 2258 HTT_DBG_EXT_STATS_PEER_INFO_IS_MAC_ADDR_S) 2259 2260 #define HTT_DBG_EXT_STATS_PEER_REQ_MODE_GET(_var) \ 2261 (((_var) & HTT_DBG_EXT_STATS_PEER_REQ_MODE_M) >> \ 2262 HTT_DBG_EXT_STATS_PEER_REQ_MODE_S) 2263 2264 #define HTT_DBG_EXT_STATS_PEER_REQ_MODE_SET(_var, _val) \ 2265 do { \ 2266 ((_var) |= ((_val) << HTT_DBG_EXT_STATS_PEER_REQ_MODE_S)); \ 2267 } while (0) 2268 2269 #define HTT_DBG_EXT_STATS_PEER_INFO_SW_PEER_ID_GET(_var) \ 2270 (((_var) & HTT_DBG_EXT_STATS_PEER_INFO_SW_PEER_ID_M) >> \ 2271 HTT_DBG_EXT_STATS_PEER_INFO_SW_PEER_ID_S) 2272 2273 #define HTT_DBG_EXT_STATS_PEER_INFO_SW_PEER_ID_SET(_var, _val) \ 2274 do { \ 2275 ((_var) |= ((_val) << HTT_DBG_EXT_STATS_PEER_INFO_SW_PEER_ID_S)); \ 2276 } while (0) 2277 2278 /* STATS_TYPE : HTT_DBG_EXT_STATS_PEER_INFO 2279 * TLV_TAGS: 2280 * - HTT_STATS_PEER_STATS_CMN_TAG 2281 * - HTT_STATS_PEER_DETAILS_TAG 2282 * - HTT_STATS_PEER_TX_RATE_STATS_TAG 2283 * - HTT_STATS_PEER_RX_RATE_STATS_TAG 2284 * - HTT_STATS_TX_TID_DETAILS_TAG (multiple) (deprecated, so 0 elements in updated systems) 2285 * - HTT_STATS_RX_TID_DETAILS_TAG (multiple) 2286 * - HTT_STATS_PEER_MSDU_FLOWQ_TAG (multiple) 2287 * - HTT_STATS_TX_TID_DETAILS_V1_TAG (multiple) 2288 * - HTT_STATS_PEER_SCHED_STATS_TAG 2289 * - HTT_STATS_PEER_AX_OFDMA_STATS_TAG 2290 */ 2291 /* NOTE: 2292 * This structure is for documentation, and cannot be safely used directly. 2293 * Instead, use the constituent TLV structures to fill/parse. 2294 */ 2295 #ifdef ATH_TARGET 2296 typedef struct _htt_peer_stats { 2297 htt_stats_peer_stats_cmn_tlv cmn_tlv; 2298 2299 htt_stats_peer_details_tlv peer_details; 2300 /* from g_rate_info_stats */ 2301 htt_stats_peer_tx_rate_stats_tlv tx_rate; 2302 htt_stats_peer_rx_rate_stats_tlv rx_rate; 2303 htt_stats_tx_tid_details_tlv tx_tid_stats[1]; 2304 htt_stats_rx_tid_details_tlv rx_tid_stats[1]; 2305 htt_stats_peer_msdu_flowq_tlv msdu_flowq[1]; 2306 htt_stats_tx_tid_details_v1_tlv tx_tid_stats_v1[1]; 2307 htt_stats_peer_sched_stats_tlv peer_sched_stats; 2308 htt_stats_peer_ax_ofdma_stats_tlv ax_ofdma_stats; 2309 htt_stats_peer_be_ofdma_stats_tlv be_ofdma_stats; 2310 } htt_peer_stats_t; 2311 #endif /* ATH_TARGET */ 2312 2313 /* =========== ACTIVE PEER LIST ========== */ 2314 2315 /* STATS_TYPE: HTT_DBG_EXT_STATS_ACTIVE_PEERS_LIST 2316 * TLV_TAGS: 2317 * - HTT_STATS_PEER_DETAILS_TAG 2318 */ 2319 /* NOTE: 2320 * This structure is for documentation, and cannot be safely used directly. 2321 * Instead, use the constituent TLV structures to fill/parse. 2322 */ 2323 #ifdef ATH_TARGET 2324 typedef struct { 2325 htt_stats_peer_details_tlv peer_details[1]; 2326 } htt_active_peer_details_list_t; 2327 #endif /* ATH_TARGET */ 2328 2329 /* =========== MUMIMO HWQ stats =========== */ 2330 2331 /* MU MIMO stats per hwQ */ 2332 typedef struct { 2333 htt_tlv_hdr_t tlv_hdr; 2334 /** number of MU MIMO schedules posted to HW */ 2335 A_UINT32 mu_mimo_sch_posted; 2336 /** number of MU MIMO schedules failed to post */ 2337 A_UINT32 mu_mimo_sch_failed; 2338 /** number of MU MIMO PPDUs posted to HW */ 2339 A_UINT32 mu_mimo_ppdu_posted; 2340 } htt_stats_tx_hwq_mumimo_sch_stats_tlv; 2341 /* preserve old name alias for new name consistent with the tag name */ 2342 typedef htt_stats_tx_hwq_mumimo_sch_stats_tlv htt_tx_hwq_mu_mimo_sch_stats_tlv; 2343 2344 typedef struct { 2345 htt_tlv_hdr_t tlv_hdr; 2346 /** 11AC DL MU MIMO number of mpdus queued to HW, per user */ 2347 A_UINT32 mu_mimo_mpdus_queued_usr; 2348 /** 11AC DL MU MIMO number of mpdus tried over the air, per user */ 2349 A_UINT32 mu_mimo_mpdus_tried_usr; 2350 /** 11AC DL MU MIMO number of mpdus failed acknowledgement, per user */ 2351 A_UINT32 mu_mimo_mpdus_failed_usr; 2352 /** 11AC DL MU MIMO number of mpdus re-queued to HW, per user */ 2353 A_UINT32 mu_mimo_mpdus_requeued_usr; 2354 /** 11AC DL MU MIMO BA not received, per user */ 2355 A_UINT32 mu_mimo_err_no_ba_usr; 2356 /** 11AC DL MU MIMO mpdu underrun encountered, per user */ 2357 A_UINT32 mu_mimo_mpdu_underrun_usr; 2358 /** 11AC DL MU MIMO ampdu underrun encountered, per user */ 2359 A_UINT32 mu_mimo_ampdu_underrun_usr; 2360 } htt_stats_tx_hwq_mumimo_mpdu_stats_tlv; 2361 /* preserve old name alias for new name consistent with the tag name */ 2362 typedef htt_stats_tx_hwq_mumimo_mpdu_stats_tlv 2363 htt_tx_hwq_mu_mimo_mpdu_stats_tlv; 2364 2365 #define HTT_TX_HWQ_MU_MIMO_CMN_STATS_MAC_ID_M 0x000000ff 2366 #define HTT_TX_HWQ_MU_MIMO_CMN_STATS_MAC_ID_S 0 2367 2368 #define HTT_TX_HWQ_MU_MIMO_CMN_STATS_HWQ_ID_M 0x0000ff00 2369 #define HTT_TX_HWQ_MU_MIMO_CMN_STATS_HWQ_ID_S 8 2370 2371 #define HTT_TX_HWQ_MU_MIMO_CMN_STATS_MAC_ID_GET(_var) \ 2372 (((_var) & HTT_TX_HWQ_MU_MIMO_CMN_STATS_MAC_ID_M) >> \ 2373 HTT_TX_HWQ_MU_MIMO_CMN_STATS_MAC_ID_S) 2374 2375 #define HTT_TX_HWQ_MU_MIMO_CMN_STATS_MAC_ID_SET(_var, _val) \ 2376 do { \ 2377 HTT_CHECK_SET_VAL(HTT_TX_HWQ_MU_MIMO_CMN_STATS_MAC_ID, _val); \ 2378 ((_var) |= ((_val) << HTT_TX_HWQ_MU_MIMO_CMN_STATS_MAC_ID_S)); \ 2379 } while (0) 2380 2381 #define HTT_TX_HWQ_MU_MIMO_CMN_STATS_HWQ_ID_GET(_var) \ 2382 (((_var) & HTT_TX_HWQ_MU_MIMO_CMN_STATS_HWQ_ID_M) >> \ 2383 HTT_TX_HWQ_MU_MIMO_CMN_STATS_HWQ_ID_S) 2384 2385 #define HTT_TX_HWQ_MU_MIMO_CMN_STATS_HWQ_ID_SET(_var, _val) \ 2386 do { \ 2387 HTT_CHECK_SET_VAL(HTT_TX_HWQ_MU_MIMO_CMN_STATS_HWQ_ID, _val); \ 2388 ((_var) |= ((_val) << HTT_TX_HWQ_MU_MIMO_CMN_STATS_HWQ_ID_S)); \ 2389 } while (0) 2390 2391 typedef struct { 2392 htt_tlv_hdr_t tlv_hdr; 2393 2394 /** 2395 * BIT [ 7 : 0] :- mac_id 2396 * BIT [15 : 8] :- hwq_id 2397 * BIT [31 : 16] :- reserved 2398 */ 2399 A_UINT32 mac_id__hwq_id__word; 2400 } htt_stats_tx_hwq_mumimo_cmn_stats_tlv; 2401 /* preserve old name alias for new name consistent with the tag name */ 2402 typedef htt_stats_tx_hwq_mumimo_cmn_stats_tlv htt_tx_hwq_mu_mimo_cmn_stats_tlv; 2403 2404 /* NOTE: 2405 * This structure is for documentation, and cannot be safely used directly. 2406 * Instead, use the constituent TLV structures to fill/parse. 2407 */ 2408 #ifdef ATH_TARGET 2409 typedef struct { 2410 struct { 2411 htt_stats_tx_hwq_mumimo_cmn_stats_tlv cmn_tlv; 2412 /** WAL_TX_STATS_MAX_GROUP_SIZE */ 2413 htt_stats_tx_hwq_mumimo_sch_stats_tlv mu_mimo_sch_stats_tlv[1]; 2414 /** WAL_TX_STATS_TX_MAX_NUM_USERS */ 2415 htt_stats_tx_hwq_mumimo_mpdu_stats_tlv mu_mimo_mpdu_stats_tlv[1]; 2416 } hwq[1]; 2417 } htt_tx_hwq_mu_mimo_stats_t; 2418 #endif /* ATH_TARGET */ 2419 2420 /* == TX HWQ STATS == */ 2421 #define HTT_TX_HWQ_STATS_CMN_MAC_ID_M 0x000000ff 2422 #define HTT_TX_HWQ_STATS_CMN_MAC_ID_S 0 2423 2424 #define HTT_TX_HWQ_STATS_CMN_HWQ_ID_M 0x0000ff00 2425 #define HTT_TX_HWQ_STATS_CMN_HWQ_ID_S 8 2426 2427 #define HTT_TX_HWQ_STATS_CMN_MAC_ID_GET(_var) \ 2428 (((_var) & HTT_TX_HWQ_STATS_CMN_MAC_ID_M) >> \ 2429 HTT_TX_HWQ_STATS_CMN_MAC_ID_S) 2430 2431 #define HTT_TX_HWQ_STATS_CMN_MAC_ID_SET(_var, _val) \ 2432 do { \ 2433 HTT_CHECK_SET_VAL(HTT_TX_HWQ_STATS_CMN_MAC_ID, _val); \ 2434 ((_var) |= ((_val) << HTT_TX_HWQ_STATS_CMN_MAC_ID_S)); \ 2435 } while (0) 2436 2437 #define HTT_TX_HWQ_STATS_CMN_HWQ_ID_GET(_var) \ 2438 (((_var) & HTT_TX_HWQ_STATS_CMN_HWQ_ID_M) >> \ 2439 HTT_TX_HWQ_STATS_CMN_HWQ_ID_S) 2440 2441 #define HTT_TX_HWQ_STATS_CMN_HWQ_ID_SET(_var, _val) \ 2442 do { \ 2443 HTT_CHECK_SET_VAL(HTT_TX_HWQ_STATS_CMN_HWQ_ID, _val); \ 2444 ((_var) |= ((_val) << HTT_TX_HWQ_STATS_CMN_HWQ_ID_S)); \ 2445 } while (0) 2446 2447 typedef struct { 2448 htt_tlv_hdr_t tlv_hdr; 2449 2450 /** 2451 * BIT [ 7 : 0] :- mac_id 2452 * BIT [15 : 8] :- hwq_id 2453 * BIT [31 : 16] :- reserved 2454 */ 2455 A_UINT32 mac_id__hwq_id__word; 2456 2457 /*--- PPDU level stats */ 2458 /** Number of times ack is failed for the PPDU scheduled on this txQ */ 2459 A_UINT32 xretry; 2460 /** Number of times sched cmd status reported mpdu underrun */ 2461 A_UINT32 underrun_cnt; 2462 /** Number of times sched cmd is flushed */ 2463 A_UINT32 flush_cnt; 2464 /** Number of times sched cmd is filtered */ 2465 A_UINT32 filt_cnt; 2466 /** Number of times HWSCH uploaded null mpdu bitmap */ 2467 A_UINT32 null_mpdu_bmap; 2468 /** 2469 * Number of times user ack or BA TLV is not seen on FES ring 2470 * where it is expected to be 2471 */ 2472 A_UINT32 user_ack_failure; 2473 /** Number of times TQM processed ack TLV received from HWSCH */ 2474 A_UINT32 ack_tlv_proc; 2475 /** Cache latest processed scheduler ID received from ack BA TLV */ 2476 A_UINT32 sched_id_proc; 2477 /** Number of times TxPCU reported MPDUs transmitted for a user is zero */ 2478 A_UINT32 null_mpdu_tx_count; 2479 /** 2480 * Number of times SW did not see any MPDU info bitmap TLV 2481 * on FES status ring 2482 */ 2483 A_UINT32 mpdu_bmap_not_recvd; 2484 2485 /*--- Selfgen stats per hwQ */ 2486 /** Number of SU/MU BAR frames posted to hwQ */ 2487 A_UINT32 num_bar; 2488 /** Number of RTS frames posted to hwQ */ 2489 A_UINT32 rts; 2490 /** Number of cts2self frames posted to hwQ */ 2491 A_UINT32 cts2self; 2492 /** Number of qos null frames posted to hwQ */ 2493 A_UINT32 qos_null; 2494 2495 /*--- MPDU level stats */ 2496 /** mpdus tried Tx by HWSCH/TQM */ 2497 A_UINT32 mpdu_tried_cnt; 2498 /** mpdus queued to HWSCH */ 2499 A_UINT32 mpdu_queued_cnt; 2500 /** mpdus tried but ack was not received */ 2501 A_UINT32 mpdu_ack_fail_cnt; 2502 /** This will include sched cmd flush and time based discard */ 2503 A_UINT32 mpdu_filt_cnt; 2504 /** Number of MPDUs for which ACK was successful but no Tx happened */ 2505 A_UINT32 false_mpdu_ack_count; 2506 2507 /** Number of times txq timeout happened */ 2508 A_UINT32 txq_timeout; 2509 } htt_stats_tx_hwq_cmn_tlv; 2510 /* preserve old name alias for new name consistent with the tag name */ 2511 typedef htt_stats_tx_hwq_cmn_tlv htt_tx_hwq_stats_cmn_tlv; 2512 2513 #define HTT_TX_HWQ_DIFS_LATENCY_STATS_TLV_SZ(_num_elems) (sizeof(A_UINT32) + /* hist_intvl */ \ 2514 (sizeof(A_UINT32) * (_num_elems))) 2515 /* NOTE: Variable length TLV, use length spec to infer array size */ 2516 typedef struct { 2517 htt_tlv_hdr_t tlv_hdr; 2518 A_UINT32 hist_intvl; 2519 /** difs_latency_hist: 2520 * histogram of ppdu post to hwsch - > cmd status receive, 2521 * HTT_TX_HWQ_MAX_DIFS_LATENCY_BINS 2522 */ 2523 HTT_STATS_VAR_LEN_ARRAY1(A_UINT32, difs_latency_hist); 2524 } htt_stats_tx_hwq_difs_latency_tlv; 2525 /* preserve old name alias for new name consistent with the tag name */ 2526 typedef htt_stats_tx_hwq_difs_latency_tlv htt_tx_hwq_difs_latency_stats_tlv_v; 2527 2528 #define HTT_TX_HWQ_CMD_RESULT_STATS_TLV_SZ(_num_elems) (sizeof(A_UINT32) * (_num_elems)) 2529 2530 /* NOTE: Variable length TLV, use length spec to infer array size */ 2531 typedef struct { 2532 htt_tlv_hdr_t tlv_hdr; 2533 /** cmd_result: 2534 * Histogram of sched cmd result, 2535 * HTT_TX_HWQ_MAX_CMD_RESULT_STATS 2536 */ 2537 HTT_STATS_VAR_LEN_ARRAY1(A_UINT32, cmd_result); 2538 } htt_stats_tx_hwq_cmd_result_tlv; 2539 /* preserve old name alias for new name consistent with the tag name */ 2540 typedef htt_stats_tx_hwq_cmd_result_tlv htt_tx_hwq_cmd_result_stats_tlv_v; 2541 2542 #define HTT_TX_HWQ_CMD_STALL_STATS_TLV_SZ(_num_elems) (sizeof(A_UINT32) * (_num_elems)) 2543 2544 /* NOTE: Variable length TLV, use length spec to infer array size */ 2545 typedef struct { 2546 htt_tlv_hdr_t tlv_hdr; 2547 /** cmd_stall_status: 2548 * Histogram of various pause conitions 2549 * HTT_TX_HWQ_MAX_CMD_STALL_STATS 2550 */ 2551 HTT_STATS_VAR_LEN_ARRAY1(A_UINT32, cmd_stall_status); 2552 } htt_stats_tx_hwq_cmd_stall_tlv; 2553 /* preserve old name alias for new name consistent with the tag name */ 2554 typedef htt_stats_tx_hwq_cmd_stall_tlv htt_tx_hwq_cmd_stall_stats_tlv_v; 2555 2556 #define HTT_TX_HWQ_FES_RESULT_STATS_TLV_SZ(_num_elems) (sizeof(A_UINT32) * (_num_elems)) 2557 2558 /* NOTE: Variable length TLV, use length spec to infer array size */ 2559 typedef struct { 2560 htt_tlv_hdr_t tlv_hdr; 2561 /** fes_result: 2562 * Histogram of number of user fes result, 2563 * HTT_TX_HWQ_MAX_FES_RESULT_STATS 2564 */ 2565 HTT_STATS_VAR_LEN_ARRAY1(A_UINT32, fes_result); 2566 } htt_stats_tx_hwq_fes_status_tlv; 2567 /* preserve old name alias for new name consistent with the tag name */ 2568 typedef htt_stats_tx_hwq_fes_status_tlv htt_tx_hwq_fes_result_stats_tlv_v; 2569 2570 #define HTT_TX_HWQ_TRIED_MPDU_CNT_HIST_TLV_SZ(_num_elems) (sizeof(A_UINT32) * (_num_elems)) 2571 /* NOTE: Variable length TLV, use length spec to infer array size 2572 * 2573 * The hwq_tried_mpdu_cnt_hist is a histogram of MPDUs tries per HWQ. 2574 * The tries here is the count of the MPDUS within a PPDU that the HW 2575 * had attempted to transmit on air, for the HWSCH Schedule command 2576 * submitted by FW in this HWQ .It is not the retry attempts. The 2577 * histogram bins are 0-29, 30-59, 60-89 and so on. The are 10 bins 2578 * in this histogram. 2579 * they are defined in FW using the following macros 2580 * #define WAL_MAX_TRIED_MPDU_CNT_HISTOGRAM 9 2581 * #define WAL_TRIED_MPDU_CNT_HISTOGRAM_INTERVAL 30 2582 * 2583 * */ 2584 typedef struct { 2585 htt_tlv_hdr_t tlv_hdr; 2586 A_UINT32 hist_bin_size; 2587 /** tried_mpdu_cnt_hist: 2588 * Histogram of number of mpdus on tried mpdu, 2589 * HTT_TX_HWQ_TRIED_MPDU_CNT_HIST 2590 */ 2591 HTT_STATS_VAR_LEN_ARRAY1(A_UINT32, tried_mpdu_cnt_hist); 2592 } htt_stats_tx_hwq_tried_mpdu_cnt_hist_tlv; 2593 /* preserve old name alias for new name consistent with the tag name */ 2594 typedef htt_stats_tx_hwq_tried_mpdu_cnt_hist_tlv 2595 htt_tx_hwq_tried_mpdu_cnt_hist_tlv_v; 2596 2597 #define HTT_TX_HWQ_TXOP_USED_CNT_HIST_TLV_SZ(_num_elems) (sizeof(A_UINT32) * (_num_elems)) 2598 /* NOTE: Variable length TLV, use length spec to infer array size 2599 * 2600 * The txop_used_cnt_hist is the histogram of txop per burst. After 2601 * completing the burst, we identify the txop used in the burst and 2602 * incr the corresponding bin. 2603 * Each bin represents 1ms & we have 10 bins in this histogram. 2604 * they are defined in FW using the following macros 2605 * #define WAL_MAX_TXOP_USED_CNT_HISTOGRAM 10 2606 * #define WAL_TXOP_USED_HISTOGRAM_INTERVAL 1000 ( 1 ms ) 2607 * 2608 * */ 2609 typedef struct { 2610 htt_tlv_hdr_t tlv_hdr; 2611 /** txop_used_cnt_hist: 2612 * Histogram of txop used cnt, 2613 * HTT_TX_HWQ_TXOP_USED_CNT_HIST 2614 */ 2615 HTT_STATS_VAR_LEN_ARRAY1(A_UINT32, txop_used_cnt_hist); 2616 } htt_stats_tx_hwq_txop_used_cnt_hist_tlv; 2617 /* preserve old name alias for new name consistent with the tag name */ 2618 typedef htt_stats_tx_hwq_txop_used_cnt_hist_tlv 2619 htt_tx_hwq_txop_used_cnt_hist_tlv_v; 2620 2621 /* STATS_TYPE : HTT_DBG_EXT_STATS_PDEV_TX_HWQ 2622 * TLV_TAGS: 2623 * - HTT_STATS_STRING_TAG 2624 * - HTT_STATS_TX_HWQ_CMN_TAG 2625 * - HTT_STATS_TX_HWQ_DIFS_LATENCY_TAG 2626 * - HTT_STATS_TX_HWQ_CMD_RESULT_TAG 2627 * - HTT_STATS_TX_HWQ_CMD_STALL_TAG 2628 * - HTT_STATS_TX_HWQ_FES_STATUS_TAG 2629 * - HTT_STATS_TX_HWQ_TRIED_MPDU_CNT_HIST_TAG 2630 * - HTT_STATS_TX_HWQ_TXOP_USED_CNT_HIST_TAG 2631 */ 2632 /* NOTE: 2633 * This structure is for documentation, and cannot be safely used directly. 2634 * Instead, use the constituent TLV structures to fill/parse. 2635 * General HWQ stats Mechanism: 2636 * Once the host request for the stats, FW fill all the HWQ TAGS in a buffer 2637 * for all the HWQ requested. & the FW send the buffer to host. In the 2638 * buffer the HWQ ID is filled in mac_id__hwq_id, thus identifying each 2639 * HWQ distinctly. 2640 */ 2641 #ifdef ATH_TARGET 2642 typedef struct _htt_tx_hwq_stats { 2643 htt_stats_string_tlv hwq_str_tlv; 2644 htt_stats_tx_hwq_cmn_tlv cmn_tlv; 2645 htt_stats_tx_hwq_difs_latency_tlv difs_tlv; 2646 htt_stats_tx_hwq_cmd_result_tlv cmd_result_tlv; 2647 htt_stats_tx_hwq_cmd_stall_tlv cmd_stall_tlv; 2648 htt_stats_tx_hwq_fes_status_tlv fes_stats_tlv; 2649 htt_stats_tx_hwq_tried_mpdu_cnt_hist_tlv tried_mpdu_tlv; 2650 htt_stats_tx_hwq_txop_used_cnt_hist_tlv txop_used_tlv; 2651 } htt_tx_hwq_stats_t; 2652 #endif /* ATH_TARGET */ 2653 2654 /* == TX SELFGEN STATS == */ 2655 2656 #define HTT_TX_SELFGEN_CMN_STATS_MAC_ID_M 0x000000ff 2657 #define HTT_TX_SELFGEN_CMN_STATS_MAC_ID_S 0 2658 2659 #define HTT_TX_SELFGEN_CMN_STATS_MAC_ID_GET(_var) \ 2660 (((_var) & HTT_TX_SELFGEN_CMN_STATS_MAC_ID_M) >> \ 2661 HTT_TX_SELFGEN_CMN_STATS_MAC_ID_S) 2662 2663 #define HTT_TX_SELFGEN_CMN_STATS_MAC_ID_SET(_var, _val) \ 2664 do { \ 2665 HTT_CHECK_SET_VAL(HTT_TX_SELFGEN_CMN_STATS_MAC_ID, _val); \ 2666 ((_var) |= ((_val) << HTT_TX_SELFGEN_CMN_STATS_MAC_ID_S)); \ 2667 } while (0) 2668 2669 typedef enum { 2670 HTT_TXERR_NONE, 2671 HTT_TXERR_RESP, /* response timeout, mismatch, 2672 * BW mismatch, mimo ctrl mismatch, 2673 * CRC error.. */ 2674 HTT_TXERR_FILT, /* blocked by tx filtering */ 2675 HTT_TXERR_FIFO, /* fifo, misc errors in HW */ 2676 HTT_TXERR_SWABORT, /* software initialted abort (TX_ABORT) */ 2677 2678 HTT_TXERR_RESERVED1, 2679 HTT_TXERR_RESERVED2, 2680 HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS = 7, 2681 2682 HTT_TXERR_INVALID = 0xff, 2683 } htt_tx_err_status_t; 2684 2685 2686 /* Matching enum for htt_tx_selfgen_sch_tsflag_error_stats */ 2687 typedef enum { 2688 HTT_TX_SELFGEN_SCH_TSFLAG_FLUSH_RCVD_ERR, 2689 HTT_TX_SELFGEN_SCH_TSFLAG_FILT_SCHED_CMD_ERR, 2690 HTT_TX_SELFGEN_SCH_TSFLAG_RESP_MISMATCH_ERR, 2691 HTT_TX_SELFGEN_SCH_TSFLAG_RESP_CBF_MIMO_CTRL_MISMATCH_ERR, 2692 HTT_TX_SELFGEN_SCH_TSFLAG_RESP_CBF_BW_MISMATCH_ERR, 2693 HTT_TX_SELFGEN_SCH_TSFLAG_RETRY_COUNT_FAIL_ERR, 2694 HTT_TX_SELFGEN_SCH_TSFLAG_RESP_TOO_LATE_RECEIVED_ERR, 2695 HTT_TX_SELFGEN_SCH_TSFLAG_SIFS_STALL_NO_NEXT_CMD_ERR, 2696 2697 HTT_TX_SELFGEN_NUM_SCH_TSFLAG_ERROR_STATS = 8, 2698 HTT_TX_SELFGEN_SCH_TSFLAG_ERROR_STATS_VALID = 8 2699 } htt_tx_selfgen_sch_tsflag_error_stats; 2700 2701 typedef enum { 2702 HTT_TX_MUMIMO_GRP_VALID, 2703 HTT_TX_MUMIMO_GRP_INVALID_NUM_MU_USERS_EXCEEDED_MU_MAX_USERS, 2704 HTT_TX_MUMIMO_GRP_INVALID_SCHED_ALGO_NOT_MU_COMPATIBLE_GID, 2705 HTT_TX_MUMIMO_GRP_INVALID_NON_PRIMARY_GRP, 2706 HTT_TX_MUMIMO_GRP_INVALID_ZERO_CANDIDATES, 2707 HTT_TX_MUMIMO_GRP_INVALID_MORE_CANDIDATES, 2708 HTT_TX_MUMIMO_GRP_INVALID_GROUP_SIZE_EXCEED_NSS, 2709 HTT_TX_MUMIMO_GRP_INVALID_GROUP_INELIGIBLE, 2710 HTT_TX_MUMIMO_GRP_INVALID, 2711 HTT_TX_MUMIMO_GRP_INVALID_GROUP_EFF_MU_TPUT_OMBPS, 2712 HTT_TX_MUMIMO_GRP_INVALID_MAX_REASON_CODE, 2713 } htt_tx_mumimo_grp_invalid_reason_code_stats; 2714 2715 #define HTT_TX_PDEV_STATS_NUM_AC_MUMIMO_USER_STATS 4 2716 #define HTT_TX_PDEV_STATS_NUM_AX_MUMIMO_USER_STATS 8 2717 #define HTT_TX_PDEV_STATS_NUM_BE_MUMIMO_USER_STATS 8 2718 #define HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS 74 2719 #define HTT_TX_PDEV_STATS_NUM_UL_MUMIMO_USER_STATS 8 2720 #define HTT_STATS_MAX_MUMIMO_GRP_SZ 8 2721 /* 2722 * Each bin represents a 300 mbps throughput 2723 * [0] - 0-300mbps; [1] - 300-600mbps [2] - 600-900mbps; [3] - 900-1200mbps; [4] - 1200-1500mbps 2724 * [5] - 1500-1800mbps; [6] - 1800-2100mbps; [7] - 2100-2400mbps; [8] - 2400-2700mbps; [9] - >=2700mbps 2725 */ 2726 #define HTT_STATS_MUMIMO_TPUT_NUM_BINS 10 2727 #define HTT_STATS_MAX_INVALID_REASON_CODE \ 2728 HTT_TX_MUMIMO_GRP_INVALID_MAX_REASON_CODE 2729 /* Reasons stated in htt_tx_mumimo_grp_invalid_reason_code_stats */ 2730 #define HTT_TX_NUM_MUMIMO_GRP_INVALID_WORDS \ 2731 (HTT_STATS_MAX_MUMIMO_GRP_SZ * HTT_STATS_MAX_INVALID_REASON_CODE) 2732 2733 #define HTT_MAX_NUM_SBT_INTR 4 2734 2735 typedef struct { 2736 htt_tlv_hdr_t tlv_hdr; 2737 2738 /* 2739 * BIT [ 7 : 0] :- mac_id 2740 * BIT [31 : 8] :- reserved 2741 */ 2742 A_UINT32 mac_id__word; 2743 /** BAR sent out for SU transmission */ 2744 A_UINT32 su_bar; 2745 /** SW generated RTS frame sent */ 2746 A_UINT32 rts; 2747 /** SW generated CTS-to-self frame sent */ 2748 A_UINT32 cts2self; 2749 /** SW generated QOS NULL frame sent */ 2750 A_UINT32 qos_null; 2751 /** BAR sent for MU user 1 */ 2752 A_UINT32 delayed_bar_1; 2753 /** BAR sent for MU user 2 */ 2754 A_UINT32 delayed_bar_2; 2755 /** BAR sent for MU user 3 */ 2756 A_UINT32 delayed_bar_3; 2757 /** BAR sent for MU user 4 */ 2758 A_UINT32 delayed_bar_4; 2759 /** BAR sent for MU user 5 */ 2760 A_UINT32 delayed_bar_5; 2761 /** BAR sent for MU user 6 */ 2762 A_UINT32 delayed_bar_6; 2763 /** BAR sent for MU user 7 */ 2764 A_UINT32 delayed_bar_7; 2765 A_UINT32 bar_with_tqm_head_seq_num; 2766 A_UINT32 bar_with_tid_seq_num; 2767 /** SW generated RTS frame queued to the HW */ 2768 A_UINT32 su_sw_rts_queued; 2769 /** SW generated RTS frame sent over the air */ 2770 A_UINT32 su_sw_rts_tried; 2771 /** SW generated RTS frame completed with error */ 2772 A_UINT32 su_sw_rts_err; 2773 /** SW generated RTS frame flushed */ 2774 A_UINT32 su_sw_rts_flushed; 2775 /** CTS (RTS response) received in different BW */ 2776 A_UINT32 su_sw_rts_rcvd_cts_diff_bw; 2777 /* START DEPRECATED FIELDS */ 2778 /** 11AX HE MU Combined Freq. BSRP Trigger frame sent over the air */ 2779 A_UINT32 combined_ax_bsr_trigger_tried[HTT_NUM_AC_WMM]; 2780 /** 11AX HE MU Combined Freq. BSRP Trigger completed with error(s) */ 2781 A_UINT32 combined_ax_bsr_trigger_err[HTT_NUM_AC_WMM]; 2782 /** 11AX HE MU Standalone Freq. BSRP Trigger frame sent over the air */ 2783 A_UINT32 standalone_ax_bsr_trigger_tried[HTT_NUM_AC_WMM]; 2784 /** 11AX HE MU Standalone Freq. BSRP Trigger completed with error(s) */ 2785 A_UINT32 standalone_ax_bsr_trigger_err[HTT_NUM_AC_WMM]; 2786 /* END DEPRECATED FIELDS */ 2787 /** smart_basic_trig_sch_histogram: 2788 * Count how many times the interval between predictive basic triggers 2789 * sent to a given STA based on analysis of that STA's traffic patterns 2790 * is within a given range: 2791 * 2792 * smart_basic_trig_sch_histogram[0]: SBT interval <= 10 ms 2793 * smart_basic_trig_sch_histogram[1]: 10 ms < SBT interval <= 20 ms 2794 * smart_basic_trig_sch_histogram[2]: 20 ms < SBT interval <= 30 ms 2795 * smart_basic_trig_sch_histogram[3]: 30 ms < SBT interval <= 40 ms 2796 * 2797 * (Smart basic triggers are only used with intervals <= 40 ms.) 2798 */ 2799 A_UINT32 smart_basic_trig_sch_histogram[HTT_MAX_NUM_SBT_INTR]; 2800 } htt_stats_tx_selfgen_cmn_stats_tlv; 2801 /* preserve old name alias for new name consistent with the tag name */ 2802 typedef htt_stats_tx_selfgen_cmn_stats_tlv htt_tx_selfgen_cmn_stats_tlv; 2803 2804 typedef struct { 2805 htt_tlv_hdr_t tlv_hdr; 2806 /** 11AC VHT SU NDPA frame sent over the air */ 2807 A_UINT32 ac_su_ndpa; 2808 /** 11AC VHT SU NDP frame sent over the air */ 2809 A_UINT32 ac_su_ndp; 2810 /** 11AC VHT MU MIMO NDPA frame sent over the air */ 2811 A_UINT32 ac_mu_mimo_ndpa; 2812 /** 11AC VHT MU MIMO NDP frame sent over the air */ 2813 A_UINT32 ac_mu_mimo_ndp; 2814 /** 11AC VHT MU MIMO BR-POLL for user 1 sent over the air */ 2815 A_UINT32 ac_mu_mimo_brpoll_1; 2816 /** 11AC VHT MU MIMO BR-POLL for user 2 sent over the air */ 2817 A_UINT32 ac_mu_mimo_brpoll_2; 2818 /** 11AC VHT MU MIMO BR-POLL for user 3 sent over the air */ 2819 A_UINT32 ac_mu_mimo_brpoll_3; 2820 /** 11AC VHT SU NDPA frame queued to the HW */ 2821 A_UINT32 ac_su_ndpa_queued; 2822 /** 11AC VHT SU NDP frame queued to the HW */ 2823 A_UINT32 ac_su_ndp_queued; 2824 /** 11AC VHT MU MIMO NDPA frame queued to the HW */ 2825 A_UINT32 ac_mu_mimo_ndpa_queued; 2826 /** 11AC VHT MU MIMO NDP frame queued to the HW */ 2827 A_UINT32 ac_mu_mimo_ndp_queued; 2828 /** 11AC VHT MU MIMO BR-POLL for user 1 frame queued to the HW */ 2829 A_UINT32 ac_mu_mimo_brpoll_1_queued; 2830 /** 11AC VHT MU MIMO BR-POLL for user 2 frame queued to the HW */ 2831 A_UINT32 ac_mu_mimo_brpoll_2_queued; 2832 /** 11AC VHT MU MIMO BR-POLL for user 3 frame queued to the HW */ 2833 A_UINT32 ac_mu_mimo_brpoll_3_queued; 2834 } htt_stats_tx_selfgen_ac_stats_tlv; 2835 /* preserve old name alias for new name consistent with the tag name */ 2836 typedef htt_stats_tx_selfgen_ac_stats_tlv htt_tx_selfgen_ac_stats_tlv; 2837 2838 typedef struct { 2839 htt_tlv_hdr_t tlv_hdr; 2840 /** 11AX HE SU NDPA frame sent over the air */ 2841 A_UINT32 ax_su_ndpa; 2842 /** 11AX HE NDP frame sent over the air */ 2843 A_UINT32 ax_su_ndp; 2844 /** 11AX HE MU MIMO NDPA frame sent over the air */ 2845 A_UINT32 ax_mu_mimo_ndpa; 2846 /** 11AX HE MU MIMO NDP frame sent over the air */ 2847 A_UINT32 ax_mu_mimo_ndp; 2848 union { 2849 struct { 2850 /* deprecated old names */ 2851 A_UINT32 ax_mu_mimo_brpoll_1; 2852 A_UINT32 ax_mu_mimo_brpoll_2; 2853 A_UINT32 ax_mu_mimo_brpoll_3; 2854 A_UINT32 ax_mu_mimo_brpoll_4; 2855 A_UINT32 ax_mu_mimo_brpoll_5; 2856 A_UINT32 ax_mu_mimo_brpoll_6; 2857 A_UINT32 ax_mu_mimo_brpoll_7; 2858 }; 2859 /** 11AX HE MU BR-POLL frame for users 1 - 7 sent over the air */ 2860 A_UINT32 ax_mu_mimo_brpoll[HTT_TX_PDEV_STATS_NUM_AX_MUMIMO_USER_STATS - 1]; 2861 }; 2862 /** 11AX HE MU Basic Trigger frame sent over the air */ 2863 A_UINT32 ax_basic_trigger; 2864 /** 11AX HE MU BSRP Trigger frame sent over the air */ 2865 A_UINT32 ax_bsr_trigger; 2866 /** 11AX HE MU BAR Trigger frame sent over the air */ 2867 A_UINT32 ax_mu_bar_trigger; 2868 /** 11AX HE MU RTS Trigger frame sent over the air */ 2869 A_UINT32 ax_mu_rts_trigger; 2870 /** 11AX HE MU UL-MUMIMO Trigger frame sent over the air */ 2871 A_UINT32 ax_ulmumimo_trigger; 2872 /** 11AX HE SU NDPA frame queued to the HW */ 2873 A_UINT32 ax_su_ndpa_queued; 2874 /** 11AX HE SU NDP frame queued to the HW */ 2875 A_UINT32 ax_su_ndp_queued; 2876 /** 11AX HE MU MIMO NDPA frame queued to the HW */ 2877 A_UINT32 ax_mu_mimo_ndpa_queued; 2878 /** 11AX HE MU MIMO NDP frame queued to the HW */ 2879 A_UINT32 ax_mu_mimo_ndp_queued; 2880 /** 11AX HE MU BR-POLL frame for users 1 - 7 queued to the HW */ 2881 A_UINT32 ax_mu_mimo_brpoll_queued[HTT_TX_PDEV_STATS_NUM_AX_MUMIMO_USER_STATS - 1]; 2882 /** 2883 * 11AX HE UL-MUMIMO Trigger frame for users 0 - 7 2884 * successfully sent over the air 2885 */ 2886 A_UINT32 ax_ul_mumimo_trigger[HTT_TX_PDEV_STATS_NUM_AX_MUMIMO_USER_STATS]; 2887 /** 11AX HE MU Combined Freq. BSRP Trigger frame sent over the air */ 2888 A_UINT32 combined_ax_bsr_trigger_tried[HTT_NUM_AC_WMM]; 2889 /** 11AX HE MU Combined Freq. BSRP Trigger completed with error(s) */ 2890 A_UINT32 combined_ax_bsr_trigger_err[HTT_NUM_AC_WMM]; 2891 /** 11AX HE MU Standalone Freq. BSRP Trigger frame sent over the air */ 2892 A_UINT32 standalone_ax_bsr_trigger_tried[HTT_NUM_AC_WMM]; 2893 /** 11AX HE MU Standalone Freq. BSRP Trigger completed with error(s) */ 2894 A_UINT32 standalone_ax_bsr_trigger_err[HTT_NUM_AC_WMM]; 2895 /** 11AX HE Manual Single-User UL OFDMA Trigger frame sent over the air */ 2896 A_UINT32 manual_ax_su_ulofdma_basic_trigger[HTT_NUM_AC_WMM]; 2897 /** 11AX HE Manual Single-User UL OFDMA Trigger completed with error(s) */ 2898 A_UINT32 manual_ax_su_ulofdma_basic_trigger_err[HTT_NUM_AC_WMM]; 2899 /** 11AX HE Manual Multi-User UL OFDMA Trigger frame sent over the air */ 2900 A_UINT32 manual_ax_mu_ulofdma_basic_trigger[HTT_NUM_AC_WMM]; 2901 /** 11AX HE Manual Multi-User UL OFDMA Trigger completed with error(s) */ 2902 A_UINT32 manual_ax_mu_ulofdma_basic_trigger_err[HTT_NUM_AC_WMM]; 2903 /** 11AX HE UL OFDMA Basic Trigger frames per AC */ 2904 A_UINT32 ax_basic_trigger_per_ac[HTT_NUM_AC_WMM]; 2905 /** 11AX HE UL OFDMA Basic Trigger frames per AC completed with error(s) */ 2906 A_UINT32 ax_basic_trigger_errors_per_ac[HTT_NUM_AC_WMM]; 2907 /** 11AX HE MU-BAR Trigger frames per AC */ 2908 A_UINT32 ax_mu_bar_trigger_per_ac[HTT_NUM_AC_WMM]; 2909 /** 11AX HE MU-BAR Trigger frames per AC completed with error(s) */ 2910 A_UINT32 ax_mu_bar_trigger_errors_per_ac[HTT_NUM_AC_WMM]; 2911 } htt_stats_tx_selfgen_ax_stats_tlv; 2912 /* preserve old name alias for new name consistent with the tag name */ 2913 typedef htt_stats_tx_selfgen_ax_stats_tlv htt_tx_selfgen_ax_stats_tlv; 2914 2915 typedef struct { 2916 htt_tlv_hdr_t tlv_hdr; 2917 /** 11be EHT SU NDPA frame sent over the air */ 2918 A_UINT32 be_su_ndpa; 2919 /** 11be EHT NDP frame sent over the air */ 2920 A_UINT32 be_su_ndp; 2921 /** 11be EHT MU MIMO NDPA frame sent over the air */ 2922 A_UINT32 be_mu_mimo_ndpa; 2923 /** 11be EHT MU MIMO NDP frame sent over theT air */ 2924 A_UINT32 be_mu_mimo_ndp; 2925 /** 11be EHT MU BR-POLL frame for users 1 - 7 sent over the air */ 2926 A_UINT32 be_mu_mimo_brpoll[HTT_TX_PDEV_STATS_NUM_BE_MUMIMO_USER_STATS - 1]; 2927 /** 11be EHT MU Basic Trigger frame sent over the air */ 2928 A_UINT32 be_basic_trigger; 2929 /** 11be EHT MU BSRP Trigger frame sent over the air */ 2930 A_UINT32 be_bsr_trigger; 2931 /** 11be EHT MU BAR Trigger frame sent over the air */ 2932 A_UINT32 be_mu_bar_trigger; 2933 /** 11be EHT MU RTS Trigger frame sent over the air */ 2934 A_UINT32 be_mu_rts_trigger; 2935 /** 11be EHT MU UL-MUMIMO Trigger frame sent over the air */ 2936 A_UINT32 be_ulmumimo_trigger; 2937 /** 11be EHT SU NDPA frame queued to the HW */ 2938 A_UINT32 be_su_ndpa_queued; 2939 /** 11be EHT SU NDP frame queued to the HW */ 2940 A_UINT32 be_su_ndp_queued; 2941 /** 11be EHT MU MIMO NDPA frame queued to the HW */ 2942 A_UINT32 be_mu_mimo_ndpa_queued; 2943 /** 11be EHT MU MIMO NDP frame queued to the HW */ 2944 A_UINT32 be_mu_mimo_ndp_queued; 2945 /** 11be EHT MU BR-POLL frame for users 1 - 7 queued to the HW */ 2946 A_UINT32 be_mu_mimo_brpoll_queued[HTT_TX_PDEV_STATS_NUM_BE_MUMIMO_USER_STATS - 1]; 2947 /** 2948 * 11be EHT UL-MUMIMO Trigger frame for users 0 - 7 2949 * successfully sent over the air 2950 */ 2951 A_UINT32 be_ul_mumimo_trigger[HTT_TX_PDEV_STATS_NUM_BE_MUMIMO_USER_STATS]; 2952 /** 11BE EHT MU Combined Freq. BSRP Trigger frame sent over the air */ 2953 A_UINT32 combined_be_bsr_trigger_tried[HTT_NUM_AC_WMM]; 2954 /** 11BE EHT MU Combined Freq. BSRP Trigger completed with error(s) */ 2955 A_UINT32 combined_be_bsr_trigger_err[HTT_NUM_AC_WMM]; 2956 /** 11BE EHT MU Standalone Freq. BSRP Trigger frame sent over the air */ 2957 A_UINT32 standalone_be_bsr_trigger_tried[HTT_NUM_AC_WMM]; 2958 /** 11BE EHT MU Standalone Freq. BSRP Trigger completed with error(s) */ 2959 A_UINT32 standalone_be_bsr_trigger_err[HTT_NUM_AC_WMM]; 2960 /** 11BE EHT Manual Single-User UL OFDMA Trigger frame sent over the air */ 2961 A_UINT32 manual_be_su_ulofdma_basic_trigger[HTT_NUM_AC_WMM]; 2962 /** 11BE EHT Manual Single-User UL OFDMA Trigger completed with error(s) */ 2963 A_UINT32 manual_be_su_ulofdma_basic_trigger_err[HTT_NUM_AC_WMM]; 2964 /** 11BE EHT Manual Multi-User UL OFDMA Trigger frame sent over the air */ 2965 A_UINT32 manual_be_mu_ulofdma_basic_trigger[HTT_NUM_AC_WMM]; 2966 /** 11BE EHT Manual Multi-User UL OFDMA Trigger completed with error(s) */ 2967 A_UINT32 manual_be_mu_ulofdma_basic_trigger_err[HTT_NUM_AC_WMM]; 2968 /** 11BE EHT UL OFDMA Basic Trigger frames per AC */ 2969 A_UINT32 be_basic_trigger_per_ac[HTT_NUM_AC_WMM]; 2970 /** 11BE EHT UL OFDMA Basic Trigger frames per AC completed with error(s) */ 2971 A_UINT32 be_basic_trigger_errors_per_ac[HTT_NUM_AC_WMM]; 2972 /** 11BE EHT MU-BAR Trigger frames per AC */ 2973 A_UINT32 be_mu_bar_trigger_per_ac[HTT_NUM_AC_WMM]; 2974 /** 11BE EHT MU-BAR Trigger frames per AC completed with error(s) */ 2975 A_UINT32 be_mu_bar_trigger_errors_per_ac[HTT_NUM_AC_WMM]; 2976 } htt_stats_tx_selfgen_be_stats_tlv; 2977 /* preserve old name alias for new name consistent with the tag name */ 2978 typedef htt_stats_tx_selfgen_be_stats_tlv htt_tx_selfgen_be_stats_tlv; 2979 2980 typedef struct { /* DEPRECATED */ 2981 htt_tlv_hdr_t tlv_hdr; 2982 /** 11AX HE OFDMA NDPA frame queued to the HW */ 2983 A_UINT32 ax_ofdma_ndpa_queued[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; 2984 /** 11AX HE OFDMA NDPA frame sent over the air */ 2985 A_UINT32 ax_ofdma_ndpa_tried[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; 2986 /** 11AX HE OFDMA NDPA frame flushed by HW */ 2987 A_UINT32 ax_ofdma_ndpa_flushed[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; 2988 /** 11AX HE OFDMA NDPA frame completed with error(s) */ 2989 A_UINT32 ax_ofdma_ndpa_err[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; 2990 } htt_stats_txbf_ofdma_ndpa_stats_tlv; 2991 /* preserve old name alias for new name consistent with the tag name */ 2992 typedef htt_stats_txbf_ofdma_ndpa_stats_tlv htt_txbf_ofdma_ndpa_stats_tlv; 2993 2994 typedef struct { /* DEPRECATED */ 2995 htt_tlv_hdr_t tlv_hdr; 2996 /** 11AX HE OFDMA NDP frame queued to the HW */ 2997 A_UINT32 ax_ofdma_ndp_queued[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; 2998 /** 11AX HE OFDMA NDPA frame sent over the air */ 2999 A_UINT32 ax_ofdma_ndp_tried[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; 3000 /** 11AX HE OFDMA NDPA frame flushed by HW */ 3001 A_UINT32 ax_ofdma_ndp_flushed[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; 3002 /** 11AX HE OFDMA NDPA frame completed with error(s) */ 3003 A_UINT32 ax_ofdma_ndp_err[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; 3004 } htt_stats_txbf_ofdma_ndp_stats_tlv; 3005 /* preserve old name alias for new name consistent with the tag name */ 3006 typedef htt_stats_txbf_ofdma_ndp_stats_tlv htt_txbf_ofdma_ndp_stats_tlv; 3007 3008 typedef struct { /* DEPRECATED */ 3009 htt_tlv_hdr_t tlv_hdr; 3010 /** 11AX HE OFDMA MU BRPOLL frame queued to the HW */ 3011 A_UINT32 ax_ofdma_brpoll_queued[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; 3012 /** 11AX HE OFDMA MU BRPOLL frame sent over the air */ 3013 A_UINT32 ax_ofdma_brpoll_tried[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; 3014 /** 11AX HE OFDMA MU BRPOLL frame flushed by HW */ 3015 A_UINT32 ax_ofdma_brpoll_flushed[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; 3016 /** 11AX HE OFDMA MU BRPOLL frame completed with error(s) */ 3017 A_UINT32 ax_ofdma_brp_err[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; 3018 /** 3019 * Number of CBF(s) received when 11AX HE OFDMA MU BRPOLL frame 3020 * completed with error(s) 3021 */ 3022 A_UINT32 ax_ofdma_brp_err_num_cbf_rcvd[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS+1]; 3023 } htt_stats_txbf_ofdma_brp_stats_tlv; 3024 /* preserve old name alias for new name consistent with the tag name */ 3025 typedef htt_stats_txbf_ofdma_brp_stats_tlv htt_txbf_ofdma_brp_stats_tlv; 3026 3027 typedef struct { /* DEPRECATED */ 3028 htt_tlv_hdr_t tlv_hdr; 3029 /** 3030 * 11AX HE OFDMA PPDUs that were sent over the air with steering 3031 * (TXBF + OFDMA) 3032 */ 3033 A_UINT32 ax_ofdma_num_ppdu_steer[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; 3034 /** 11AX HE OFDMA PPDUs that were sent over the air in open loop */ 3035 A_UINT32 ax_ofdma_num_ppdu_ol[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; 3036 /** 3037 * 11AX HE OFDMA number of users for which CBF prefetch was initiated 3038 * to PHY HW during TX 3039 */ 3040 A_UINT32 ax_ofdma_num_usrs_prefetch[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; 3041 /** 3042 * 11AX HE OFDMA number of users for which sounding was initiated 3043 * during TX 3044 */ 3045 A_UINT32 ax_ofdma_num_usrs_sound[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; 3046 /** 11AX HE OFDMA number of users for which sounding was forced during TX */ 3047 A_UINT32 ax_ofdma_num_usrs_force_sound[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; 3048 } htt_stats_txbf_ofdma_steer_stats_tlv; 3049 /* preserve old name alias for new name consistent with the tag name */ 3050 typedef htt_stats_txbf_ofdma_steer_stats_tlv htt_txbf_ofdma_steer_stats_tlv; 3051 3052 /* Note: 3053 * This struct htt_tx_pdev_txbf_ofdma_stats_t and all its constituent 3054 * struct TLVs are deprecated, due to the need for restructuring these 3055 * stats into a variable length array 3056 */ 3057 #ifdef ATH_TARGET 3058 typedef struct { /* DEPRECATED */ 3059 htt_stats_txbf_ofdma_ndpa_stats_tlv ofdma_ndpa_tlv; 3060 htt_stats_txbf_ofdma_ndp_stats_tlv ofdma_ndp_tlv; 3061 htt_stats_txbf_ofdma_brp_stats_tlv ofdma_brp_tlv; 3062 htt_stats_txbf_ofdma_steer_stats_tlv ofdma_steer_tlv; 3063 } htt_tx_pdev_txbf_ofdma_stats_t; 3064 #endif /* ATH_TARGET */ 3065 3066 typedef struct { 3067 /** 11AX HE OFDMA NDPA frame queued to the HW */ 3068 A_UINT32 ax_ofdma_ndpa_queued; 3069 /** 11AX HE OFDMA NDPA frame sent over the air */ 3070 A_UINT32 ax_ofdma_ndpa_tried; 3071 /** 11AX HE OFDMA NDPA frame flushed by HW */ 3072 A_UINT32 ax_ofdma_ndpa_flushed; 3073 /** 11AX HE OFDMA NDPA frame completed with error(s) */ 3074 A_UINT32 ax_ofdma_ndpa_err; 3075 } htt_txbf_ofdma_ax_ndpa_stats_elem_t; 3076 3077 typedef struct { 3078 htt_tlv_hdr_t tlv_hdr; 3079 /** 3080 * This field is populated with the num of elems in the ax_ndpa[] 3081 * variable length array. 3082 */ 3083 A_UINT32 num_elems_ax_ndpa_arr; 3084 /** 3085 * This field will be filled by target with value of 3086 * sizeof(htt_txbf_ofdma_ax_ndpa_stats_elem_t). 3087 * This is for allowing host to infer how much data target has provided, 3088 * even if it using different version of the struct def than what target 3089 * had used. 3090 */ 3091 A_UINT32 arr_elem_size_ax_ndpa; 3092 HTT_STATS_VAR_LEN_ARRAY1(htt_txbf_ofdma_ax_ndpa_stats_elem_t, ax_ndpa); 3093 } htt_stats_txbf_ofdma_ax_ndpa_stats_tlv; 3094 /* preserve old name alias for new name consistent with the tag name */ 3095 typedef htt_stats_txbf_ofdma_ax_ndpa_stats_tlv htt_txbf_ofdma_ax_ndpa_stats_tlv; 3096 3097 typedef struct { 3098 /** 11AX HE OFDMA NDP frame queued to the HW */ 3099 A_UINT32 ax_ofdma_ndp_queued; 3100 /** 11AX HE OFDMA NDPA frame sent over the air */ 3101 A_UINT32 ax_ofdma_ndp_tried; 3102 /** 11AX HE OFDMA NDPA frame flushed by HW */ 3103 A_UINT32 ax_ofdma_ndp_flushed; 3104 /** 11AX HE OFDMA NDPA frame completed with error(s) */ 3105 A_UINT32 ax_ofdma_ndp_err; 3106 } htt_txbf_ofdma_ax_ndp_stats_elem_t; 3107 3108 typedef struct { 3109 htt_tlv_hdr_t tlv_hdr; 3110 /** 3111 * This field is populated with the num of elems in the the ax_ndp[] 3112 * variable length array. 3113 */ 3114 A_UINT32 num_elems_ax_ndp_arr; 3115 /** 3116 * This field will be filled by target with value of 3117 * sizeof(htt_txbf_ofdma_ax_ndp_stats_elem_t). 3118 * This is for allowing host to infer how much data target has provided, 3119 * even if it using different version of the struct def than what target 3120 * had used. 3121 */ 3122 A_UINT32 arr_elem_size_ax_ndp; 3123 HTT_STATS_VAR_LEN_ARRAY1(htt_txbf_ofdma_ax_ndp_stats_elem_t, ax_ndp); 3124 } htt_stats_txbf_ofdma_ax_ndp_stats_tlv; 3125 /* preserve old name alias for new name consistent with the tag name */ 3126 typedef htt_stats_txbf_ofdma_ax_ndp_stats_tlv htt_txbf_ofdma_ax_ndp_stats_tlv; 3127 3128 typedef struct { 3129 /** 11AX HE OFDMA MU BRPOLL frame queued to the HW */ 3130 A_UINT32 ax_ofdma_brpoll_queued; 3131 /** 11AX HE OFDMA MU BRPOLL frame sent over the air */ 3132 A_UINT32 ax_ofdma_brpoll_tried; 3133 /** 11AX HE OFDMA MU BRPOLL frame flushed by HW */ 3134 A_UINT32 ax_ofdma_brpoll_flushed; 3135 /** 11AX HE OFDMA MU BRPOLL frame completed with error(s) */ 3136 A_UINT32 ax_ofdma_brp_err; 3137 /** 3138 * Number of CBF(s) received when 11AX HE OFDMA MU BRPOLL frame 3139 * completed with error(s) 3140 */ 3141 A_UINT32 ax_ofdma_brp_err_num_cbf_rcvd; 3142 } htt_txbf_ofdma_ax_brp_stats_elem_t; 3143 3144 typedef struct { 3145 htt_tlv_hdr_t tlv_hdr; 3146 /** 3147 * This field is populated with the num of elems in the the ax_brp[] 3148 * variable length array. 3149 */ 3150 A_UINT32 num_elems_ax_brp_arr; 3151 /** 3152 * This field will be filled by target with value of 3153 * sizeof(htt_txbf_ofdma_ax_brp_stats_elem_t). 3154 * This is for allowing host to infer how much data target has provided, 3155 * even if it using different version of the struct than what target 3156 * had used. 3157 */ 3158 A_UINT32 arr_elem_size_ax_brp; 3159 HTT_STATS_VAR_LEN_ARRAY1(htt_txbf_ofdma_ax_brp_stats_elem_t, ax_brp); 3160 } htt_stats_txbf_ofdma_ax_brp_stats_tlv; 3161 /* preserve old name alias for new name consistent with the tag name */ 3162 typedef htt_stats_txbf_ofdma_ax_brp_stats_tlv htt_txbf_ofdma_ax_brp_stats_tlv; 3163 3164 typedef struct { 3165 /** 3166 * 11AX HE OFDMA PPDUs that were sent over the air with steering 3167 * (TXBF + OFDMA) 3168 */ 3169 A_UINT32 ax_ofdma_num_ppdu_steer; 3170 /** 11AX HE OFDMA PPDUs that were sent over the air in open loop */ 3171 A_UINT32 ax_ofdma_num_ppdu_ol; 3172 /** 3173 * 11AX HE OFDMA number of users for which CBF prefetch was initiated 3174 * to PHY HW during TX 3175 */ 3176 A_UINT32 ax_ofdma_num_usrs_prefetch; 3177 /** 3178 * 11AX HE OFDMA number of users for which sounding was initiated 3179 * during TX 3180 */ 3181 A_UINT32 ax_ofdma_num_usrs_sound; 3182 /** 11AX HE OFDMA number of users for which sounding was forced during TX */ 3183 A_UINT32 ax_ofdma_num_usrs_force_sound; 3184 } htt_txbf_ofdma_ax_steer_stats_elem_t; 3185 3186 typedef struct { 3187 htt_tlv_hdr_t tlv_hdr; 3188 /** 3189 * This field is populated with the num of elems in the ax_steer[] 3190 * variable length array. 3191 */ 3192 A_UINT32 num_elems_ax_steer_arr; 3193 /** 3194 * This field will be filled by target with value of 3195 * sizeof(htt_txbf_ofdma_ax_steer_stats_elem_t). 3196 * This is for allowing host to infer how much data target has provided, 3197 * even if it using different version of the struct than what target 3198 * had used. 3199 */ 3200 A_UINT32 arr_elem_size_ax_steer; 3201 HTT_STATS_VAR_LEN_ARRAY1(htt_txbf_ofdma_ax_steer_stats_elem_t, ax_steer); 3202 } htt_stats_txbf_ofdma_ax_steer_stats_tlv; 3203 /* preserve old name alias for new name consistent with the tag name */ 3204 typedef htt_stats_txbf_ofdma_ax_steer_stats_tlv 3205 htt_txbf_ofdma_ax_steer_stats_tlv; 3206 3207 typedef struct { 3208 htt_tlv_hdr_t tlv_hdr; 3209 /* 11AX HE OFDMA MPDUs tried in rbo steering */ 3210 A_UINT32 ax_ofdma_rbo_steer_mpdus_tried; 3211 /* 11AX HE OFDMA MPDUs failed in rbo steering */ 3212 A_UINT32 ax_ofdma_rbo_steer_mpdus_failed; 3213 /* 11AX HE OFDMA MPDUs tried in sifs steering */ 3214 A_UINT32 ax_ofdma_sifs_steer_mpdus_tried; 3215 /* 11AX HE OFDMA MPDUs failed in sifs steering */ 3216 A_UINT32 ax_ofdma_sifs_steer_mpdus_failed; 3217 } htt_stats_txbf_ofdma_ax_steer_mpdu_stats_tlv; 3218 /* preserve old name alias for new name consistent with the tag name */ 3219 typedef htt_stats_txbf_ofdma_ax_steer_mpdu_stats_tlv 3220 htt_txbf_ofdma_ax_steer_mpdu_stats_tlv; 3221 3222 typedef struct { 3223 /** 11BE EHT OFDMA NDPA frame queued to the HW */ 3224 A_UINT32 be_ofdma_ndpa_queued; 3225 /** 11BE EHT OFDMA NDPA frame sent over the air */ 3226 A_UINT32 be_ofdma_ndpa_tried; 3227 /** 11BE EHT OFDMA NDPA frame flushed by HW */ 3228 A_UINT32 be_ofdma_ndpa_flushed; 3229 /** 11BE EHT OFDMA NDPA frame completed with error(s) */ 3230 A_UINT32 be_ofdma_ndpa_err; 3231 } htt_txbf_ofdma_be_ndpa_stats_elem_t; 3232 3233 typedef struct { 3234 htt_tlv_hdr_t tlv_hdr; 3235 /** 3236 * This field is populated with the num of elems in the be_ndpa[] 3237 * variable length array. 3238 */ 3239 A_UINT32 num_elems_be_ndpa_arr; 3240 /** 3241 * This field will be filled by target with value of 3242 * sizeof(htt_txbf_ofdma_be_ndpa_stats_elem_t). 3243 * This is for allowing host to infer how much data target has provided, 3244 * even if it using different version of the struct than what target 3245 * had used. 3246 */ 3247 A_UINT32 arr_elem_size_be_ndpa; 3248 HTT_STATS_VAR_LEN_ARRAY1(htt_txbf_ofdma_be_ndpa_stats_elem_t, be_ndpa); 3249 } htt_stats_txbf_ofdma_be_ndpa_stats_tlv; 3250 /* preserve old name alias for new name consistent with the tag name */ 3251 typedef htt_stats_txbf_ofdma_be_ndpa_stats_tlv htt_txbf_ofdma_be_ndpa_stats_tlv; 3252 3253 typedef struct { 3254 /** 11BE EHT OFDMA NDP frame queued to the HW */ 3255 A_UINT32 be_ofdma_ndp_queued; 3256 /** 11BE EHT OFDMA NDPA frame sent over the air */ 3257 A_UINT32 be_ofdma_ndp_tried; 3258 /** 11BE EHT OFDMA NDPA frame flushed by HW */ 3259 A_UINT32 be_ofdma_ndp_flushed; 3260 /** 11BE EHT OFDMA NDPA frame completed with error(s) */ 3261 A_UINT32 be_ofdma_ndp_err; 3262 } htt_txbf_ofdma_be_ndp_stats_elem_t; 3263 3264 typedef struct { 3265 htt_tlv_hdr_t tlv_hdr; 3266 /** 3267 * This field is populated with the num of elems in the be_ndp[] 3268 * variable length array. 3269 */ 3270 A_UINT32 num_elems_be_ndp_arr; 3271 /** 3272 * This field will be filled by target with value of 3273 * sizeof(htt_txbf_ofdma_be_ndp_stats_elem_t). 3274 * This is for allowing host to infer how much data target has provided, 3275 * even if it using different version of the struct than what target 3276 * had used. 3277 */ 3278 A_UINT32 arr_elem_size_be_ndp; 3279 HTT_STATS_VAR_LEN_ARRAY1(htt_txbf_ofdma_be_ndp_stats_elem_t, be_ndp); 3280 } htt_stats_txbf_ofdma_be_ndp_stats_tlv; 3281 /* preserve old name alias for new name consistent with the tag name */ 3282 typedef htt_stats_txbf_ofdma_be_ndp_stats_tlv htt_txbf_ofdma_be_ndp_stats_tlv; 3283 3284 typedef struct { 3285 /** 11BE EHT OFDMA MU BRPOLL frame queued to the HW */ 3286 A_UINT32 be_ofdma_brpoll_queued; 3287 /** 11BE EHT OFDMA MU BRPOLL frame sent over the air */ 3288 A_UINT32 be_ofdma_brpoll_tried; 3289 /** 11BE EHT OFDMA MU BRPOLL frame flushed by HW */ 3290 A_UINT32 be_ofdma_brpoll_flushed; 3291 /** 11BE EHT OFDMA MU BRPOLL frame completed with error(s) */ 3292 A_UINT32 be_ofdma_brp_err; 3293 /** 3294 * Number of CBF(s) received when 11BE EHT OFDMA MU BRPOLL frame 3295 * completed with error(s) 3296 */ 3297 A_UINT32 be_ofdma_brp_err_num_cbf_rcvd; 3298 } htt_txbf_ofdma_be_brp_stats_elem_t; 3299 3300 typedef struct { 3301 htt_tlv_hdr_t tlv_hdr; 3302 /** 3303 * This field is populated with the num of elems in the be_brp[] 3304 * variable length array. 3305 */ 3306 A_UINT32 num_elems_be_brp_arr; 3307 /** 3308 * This field will be filled by target with value of 3309 * sizeof(htt_txbf_ofdma_be_brp_stats_elem_t). 3310 * This is for allowing host to infer how much data target has provided, 3311 * even if it using different version of the struct than what target 3312 * had used 3313 */ 3314 A_UINT32 arr_elem_size_be_brp; 3315 HTT_STATS_VAR_LEN_ARRAY1(htt_txbf_ofdma_be_brp_stats_elem_t, be_brp); 3316 } htt_stats_txbf_ofdma_be_brp_stats_tlv; 3317 /* preserve old name alias for new name consistent with the tag name */ 3318 typedef htt_stats_txbf_ofdma_be_brp_stats_tlv htt_txbf_ofdma_be_brp_stats_tlv; 3319 3320 typedef struct { 3321 /** 3322 * 11BE EHT OFDMA PPDUs that were sent over the air with steering 3323 * (TXBF + OFDMA) 3324 */ 3325 A_UINT32 be_ofdma_num_ppdu_steer; 3326 /** 11BE EHT OFDMA PPDUs that were sent over the air in open loop */ 3327 A_UINT32 be_ofdma_num_ppdu_ol; 3328 /** 3329 * 11BE EHT OFDMA number of users for which CBF prefetch was initiated 3330 * to PHY HW during TX 3331 */ 3332 A_UINT32 be_ofdma_num_usrs_prefetch; 3333 /** 3334 * 11BE EHT OFDMA number of users for which sounding was initiated 3335 * during TX 3336 */ 3337 A_UINT32 be_ofdma_num_usrs_sound; 3338 /** 3339 * 11BE EHT OFDMA number of users for which sounding was forced during TX 3340 */ 3341 A_UINT32 be_ofdma_num_usrs_force_sound; 3342 } htt_txbf_ofdma_be_steer_stats_elem_t; 3343 3344 typedef struct { 3345 htt_tlv_hdr_t tlv_hdr; 3346 /** 3347 * This field is populated with the num of elems in the be_steer[] 3348 * variable length array. 3349 */ 3350 A_UINT32 num_elems_be_steer_arr; 3351 /** 3352 * This field will be filled by target with value of 3353 * sizeof(htt_txbf_ofdma_be_steer_stats_elem_t). 3354 * This is for allowing host to infer how much data target has provided, 3355 * even if it using different version of the struct than what target 3356 * had used. 3357 */ 3358 A_UINT32 arr_elem_size_be_steer; 3359 HTT_STATS_VAR_LEN_ARRAY1(htt_txbf_ofdma_be_steer_stats_elem_t, be_steer); 3360 } htt_stats_txbf_ofdma_be_steer_stats_tlv; 3361 /* preserve old name alias for new name consistent with the tag name */ 3362 typedef htt_stats_txbf_ofdma_be_steer_stats_tlv 3363 htt_txbf_ofdma_be_steer_stats_tlv; 3364 3365 typedef struct { 3366 htt_tlv_hdr_t tlv_hdr; 3367 /* 11BE EHT OFDMA MPDUs tried in rbo steering */ 3368 A_UINT32 be_ofdma_rbo_steer_mpdus_tried; 3369 /* 11BE EHT OFDMA MPDUs failed in rbo steering */ 3370 A_UINT32 be_ofdma_rbo_steer_mpdus_failed; 3371 /* 11BE EHT OFDMA MPDUs tried in sifs steering */ 3372 A_UINT32 be_ofdma_sifs_steer_mpdus_tried; 3373 /* 11BE EHT OFDMA MPDUs failed in sifs steering */ 3374 A_UINT32 be_ofdma_sifs_steer_mpdus_failed; 3375 } htt_stats_txbf_ofdma_be_steer_mpdu_stats_tlv; 3376 /* preserve old name alias for new name consistent with the tag name */ 3377 typedef htt_stats_txbf_ofdma_be_steer_mpdu_stats_tlv 3378 htt_txbf_ofdma_be_steer_mpdu_stats_tlv; 3379 3380 /* HTT_STATS_TXBF_OFDMA_BE_PARBW_TAG stats TLV: 3381 * Sent by target in response to HTT_DBG_EXT_STATS_TXBF_OFDMA stats ID request. 3382 */ 3383 typedef struct { 3384 htt_tlv_hdr_t tlv_hdr; 3385 /* Num of EHT TxBF Partial Bandwidth soundings */ 3386 A_UINT32 be_ofdma_parbw_user_snd; 3387 /* Num of EHT Partial Bandwidth Sounded CVs received */ 3388 A_UINT32 be_ofdma_parbw_cv; 3389 /* Num of 11BE EHT Total CVs received */ 3390 A_UINT32 be_ofdma_total_cv; 3391 } htt_stats_txbf_ofdma_be_parbw_tlv; 3392 3393 /* STATS_TYPE : HTT_DBG_EXT_STATS_TXBF_OFDMA 3394 * TLV_TAGS: 3395 * - HTT_STATS_TXBF_OFDMA_NDPA_STATS_TAG 3396 * - HTT_STATS_TXBF_OFDMA_NDP_STATS_TAG 3397 * - HTT_STATS_TXBF_OFDMA_BRP_STATS_TAG 3398 * - HTT_STATS_TXBF_OFDMA_STEER_STATS_TAG 3399 * - HTT_STATS_TXBF_OFDMA_AX_STEER_MPDU_STATS_TAG 3400 * - HTT_STATS_TXBF_OFDMA_BE_NDPA_STATS_TAG 3401 * - HTT_STATS_TXBF_OFDMA_BE_NDP_STATS_TAG 3402 * - HTT_STATS_TXBF_OFDMA_BE_BRP_STATS_TAG 3403 * - HTT_STATS_TXBF_OFDMA_BE_STEER_STATS_TAG 3404 * - HTT_STATS_TXBF_OFDMA_BE_STEER_MPDU_STATS_TAG 3405 */ 3406 3407 typedef struct { 3408 htt_tlv_hdr_t tlv_hdr; 3409 /** 11AC VHT SU NDP frame completed with error(s) */ 3410 A_UINT32 ac_su_ndp_err; 3411 /** 11AC VHT SU NDPA frame completed with error(s) */ 3412 A_UINT32 ac_su_ndpa_err; 3413 /** 11AC VHT MU MIMO NDPA frame completed with error(s) */ 3414 A_UINT32 ac_mu_mimo_ndpa_err; 3415 /** 11AC VHT MU MIMO NDP frame completed with error(s) */ 3416 A_UINT32 ac_mu_mimo_ndp_err; 3417 /** 11AC VHT MU MIMO BRPOLL for user 1 frame completed with error(s) */ 3418 A_UINT32 ac_mu_mimo_brp1_err; 3419 /** 11AC VHT MU MIMO BRPOLL for user 2 frame completed with error(s) */ 3420 A_UINT32 ac_mu_mimo_brp2_err; 3421 /** 11AC VHT MU MIMO BRPOLL for user 3 frame completed with error(s) */ 3422 A_UINT32 ac_mu_mimo_brp3_err; 3423 /** 11AC VHT SU NDPA frame flushed by HW */ 3424 A_UINT32 ac_su_ndpa_flushed; 3425 /** 11AC VHT SU NDP frame flushed by HW */ 3426 A_UINT32 ac_su_ndp_flushed; 3427 /** 11AC VHT MU MIMO NDPA frame flushed by HW */ 3428 A_UINT32 ac_mu_mimo_ndpa_flushed; 3429 /** 11AC VHT MU MIMO NDP frame flushed by HW */ 3430 A_UINT32 ac_mu_mimo_ndp_flushed; 3431 /** 11AC VHT MU MIMO BRPOLL for user 1 frame flushed by HW */ 3432 A_UINT32 ac_mu_mimo_brpoll1_flushed; 3433 /** 11AC VHT MU MIMO BRPOLL for user 2 frame flushed by HW */ 3434 A_UINT32 ac_mu_mimo_brpoll2_flushed; 3435 /** 11AC VHT MU MIMO BRPOLL for user 3 frame flushed by HW */ 3436 A_UINT32 ac_mu_mimo_brpoll3_flushed; 3437 } htt_stats_tx_selfgen_ac_err_stats_tlv; 3438 /* preserve old name alias for new name consistent with the tag name */ 3439 typedef htt_stats_tx_selfgen_ac_err_stats_tlv htt_tx_selfgen_ac_err_stats_tlv; 3440 3441 typedef struct { 3442 htt_tlv_hdr_t tlv_hdr; 3443 /** 11AX HE SU NDP frame completed with error(s) */ 3444 A_UINT32 ax_su_ndp_err; 3445 /** 11AX HE SU NDPA frame completed with error(s) */ 3446 A_UINT32 ax_su_ndpa_err; 3447 /** 11AX HE MU MIMO NDPA frame completed with error(s) */ 3448 A_UINT32 ax_mu_mimo_ndpa_err; 3449 /** 11AX HE MU MIMO NDP frame completed with error(s) */ 3450 A_UINT32 ax_mu_mimo_ndp_err; 3451 union { 3452 struct { 3453 /* deprecated old names */ 3454 A_UINT32 ax_mu_mimo_brp1_err; 3455 A_UINT32 ax_mu_mimo_brp2_err; 3456 A_UINT32 ax_mu_mimo_brp3_err; 3457 A_UINT32 ax_mu_mimo_brp4_err; 3458 A_UINT32 ax_mu_mimo_brp5_err; 3459 A_UINT32 ax_mu_mimo_brp6_err; 3460 A_UINT32 ax_mu_mimo_brp7_err; 3461 }; 3462 /** 11AX HE MU BR-POLL frame for 1 - 7 users completed with error(s) */ 3463 A_UINT32 ax_mu_mimo_brp_err[HTT_TX_PDEV_STATS_NUM_AX_MUMIMO_USER_STATS - 1]; 3464 }; 3465 /** 11AX HE MU Basic Trigger frame completed with error(s) */ 3466 A_UINT32 ax_basic_trigger_err; 3467 /** 11AX HE MU BSRP Trigger frame completed with error(s) */ 3468 A_UINT32 ax_bsr_trigger_err; 3469 /** 11AX HE MU BAR Trigger frame completed with error(s) */ 3470 A_UINT32 ax_mu_bar_trigger_err; 3471 /** 11AX HE MU RTS Trigger frame completed with error(s) */ 3472 A_UINT32 ax_mu_rts_trigger_err; 3473 /** 11AX HE MU ULMUMIMO Trigger frame completed with error(s) */ 3474 A_UINT32 ax_ulmumimo_trigger_err; 3475 /** 3476 * Number of CBF(s) received when 11AX HE MU MIMO BRPOLL 3477 * frame completed with error(s) 3478 */ 3479 A_UINT32 ax_mu_mimo_brp_err_num_cbf_received[HTT_TX_PDEV_STATS_NUM_AX_MUMIMO_USER_STATS]; 3480 /** 11AX HE SU NDPA frame flushed by HW */ 3481 A_UINT32 ax_su_ndpa_flushed; 3482 /** 11AX HE SU NDP frame flushed by HW */ 3483 A_UINT32 ax_su_ndp_flushed; 3484 /** 11AX HE MU MIMO NDPA frame flushed by HW */ 3485 A_UINT32 ax_mu_mimo_ndpa_flushed; 3486 /** 11AX HE MU MIMO NDP frame flushed by HW */ 3487 A_UINT32 ax_mu_mimo_ndp_flushed; 3488 /** 11AX HE MU BR-POLL frame for users 1 - 7 flushed by HW */ 3489 A_UINT32 ax_mu_mimo_brpoll_flushed[HTT_TX_PDEV_STATS_NUM_AX_MUMIMO_USER_STATS - 1]; 3490 /** 3491 * 11AX HE UL-MUMIMO Trigger frame for users 0 - 7 completed with error(s) 3492 */ 3493 A_UINT32 ax_ul_mumimo_trigger_err[HTT_TX_PDEV_STATS_NUM_AX_MUMIMO_USER_STATS]; 3494 3495 /** 11AX HE MU OFDMA Basic Trigger frame completed with partial user response */ 3496 A_UINT32 ax_basic_trigger_partial_resp; 3497 /** 11AX HE MU BSRP Trigger frame completed with partial user response */ 3498 A_UINT32 ax_bsr_trigger_partial_resp; 3499 /** 11AX HE MU BAR Trigger frame completed with partial user response */ 3500 A_UINT32 ax_mu_bar_trigger_partial_resp; 3501 } htt_stats_tx_selfgen_ax_err_stats_tlv; 3502 /* preserve old name alias for new name consistent with the tag name */ 3503 typedef htt_stats_tx_selfgen_ax_err_stats_tlv htt_tx_selfgen_ax_err_stats_tlv; 3504 3505 typedef struct { 3506 htt_tlv_hdr_t tlv_hdr; 3507 /** 11BE EHT SU NDP frame completed with error(s) */ 3508 A_UINT32 be_su_ndp_err; 3509 /** 11BE EHT SU NDPA frame completed with error(s) */ 3510 A_UINT32 be_su_ndpa_err; 3511 /** 11BE EHT MU MIMO NDPA frame completed with error(s) */ 3512 A_UINT32 be_mu_mimo_ndpa_err; 3513 /** 11BE EHT MU MIMO NDP frame completed with error(s) */ 3514 A_UINT32 be_mu_mimo_ndp_err; 3515 /** 11BE EHT MU BR-POLL frame for 1 - 7 users completed with error(s) */ 3516 A_UINT32 be_mu_mimo_brp_err[HTT_TX_PDEV_STATS_NUM_BE_MUMIMO_USER_STATS - 1]; 3517 /** 11BE EHT MU Basic Trigger frame completed with error(s) */ 3518 A_UINT32 be_basic_trigger_err; 3519 /** 11BE EHT MU BSRP Trigger frame completed with error(s) */ 3520 A_UINT32 be_bsr_trigger_err; 3521 /** 11BE EHT MU BAR Trigger frame completed with error(s) */ 3522 A_UINT32 be_mu_bar_trigger_err; 3523 /** 11BE EHT MU RTS Trigger frame completed with error(s) */ 3524 A_UINT32 be_mu_rts_trigger_err; 3525 /** 11BE EHT MU ULMUMIMO Trigger frame completed with error(s) */ 3526 A_UINT32 be_ulmumimo_trigger_err; 3527 /** 3528 * Number of CBF(s) received when 11BE EHT MU MIMO BRPOLL frame 3529 * completed with error(s) 3530 */ 3531 A_UINT32 be_mu_mimo_brp_err_num_cbf_received[HTT_TX_PDEV_STATS_NUM_BE_MUMIMO_USER_STATS]; 3532 /** 11BE EHT SU NDPA frame flushed by HW */ 3533 A_UINT32 be_su_ndpa_flushed; 3534 /** 11BE EHT SU NDP frame flushed by HW */ 3535 A_UINT32 be_su_ndp_flushed; 3536 /** 11BE EHT MU MIMO NDPA frame flushed by HW */ 3537 A_UINT32 be_mu_mimo_ndpa_flushed; 3538 /** 11BE HT MU MIMO NDP frame flushed by HW */ 3539 A_UINT32 be_mu_mimo_ndp_flushed; 3540 /** 11BE EHT MU BR-POLL frame for users 1 - 7 flushed by HW */ 3541 A_UINT32 be_mu_mimo_brpoll_flushed[HTT_TX_PDEV_STATS_NUM_BE_MUMIMO_USER_STATS - 1]; 3542 /** 3543 * 11BE EHT UL-MUMIMO Trigger frame for users 0 - 7 completed with error(s) 3544 */ 3545 A_UINT32 be_ul_mumimo_trigger_err[HTT_TX_PDEV_STATS_NUM_BE_MUMIMO_USER_STATS]; 3546 3547 /** 11BE EHT MU OFDMA Basic Trigger frame completed with partial user response */ 3548 A_UINT32 be_basic_trigger_partial_resp; 3549 /** 11BE EHT MU BSRP Trigger frame completed with partial user response */ 3550 A_UINT32 be_bsr_trigger_partial_resp; 3551 /** 11BE EHT MU BAR Trigger frame completed with partial user response */ 3552 A_UINT32 be_mu_bar_trigger_partial_resp; 3553 /** 11BE EHT MU RTS Trigger frame blocked due to partner link TX/RX(eMLSR) */ 3554 A_UINT32 be_mu_rts_trigger_blocked; 3555 /** 11BE EHT MU BSR Trigger frame blocked due to partner link TX/RX(eMLSR) */ 3556 A_UINT32 be_bsr_trigger_blocked; 3557 } htt_stats_tx_selfgen_be_err_stats_tlv; 3558 /* preserve old name alias for new name consistent with the tag name */ 3559 typedef htt_stats_tx_selfgen_be_err_stats_tlv htt_tx_selfgen_be_err_stats_tlv; 3560 3561 /* 3562 * Scheduler completion status reason code. 3563 * (0) HTT_TXERR_NONE - No error (Success). 3564 * (1) HTT_TXERR_RESP - Response timeout, response mismatch, BW mismatch, 3565 * MIMO control mismatch, CRC error etc. 3566 * (2) HTT_TXERR_FILT - Blocked by HW tx filtering. 3567 * (3) HTT_TXERR_FIFO - FIFO, misc. errors in HW. 3568 * (4) HTT_TXERR_SWABORT - Software initialted abort (TX_ABORT). 3569 * (5) HTT_TXERR_RESERVED1 - Currently reserved. 3570 * (6) HTT_TXERR_RESERVED2 - Currently reserved. 3571 */ 3572 3573 /* Scheduler error code. 3574 * (0) HTT_TX_SELFGEN_SCH_TSFLAG_FLUSH_RCVD_ERR - Flush received from HW. 3575 * (1) HTT_TX_SELFGEN_SCH_TSFLAG_FILT_SCHED_CMD_ERR - Scheduler command was 3576 * filtered by HW. 3577 * (2) HTT_TX_SELFGEN_SCH_TSFLAG_RESP_MISMATCH_ERR - Response frame mismatch 3578 * error. 3579 * (3) HTT_TX_SELFGEN_SCH_TSFLAG_RESP_CBF_MIMO_CTRL_MISMATCH_ERR - CBF 3580 * received with MIMO control mismatch. 3581 * (4) HTT_TX_SELFGEN_SCH_TSFLAG_RESP_CBF_BW_MISMATCH_ERR - CBF received with 3582 * BW mismatch. 3583 * (5) HTT_TX_SELFGEN_SCH_TSFLAG_RETRY_COUNT_FAIL_ERR - Error in transmitting 3584 * frame even after maximum retries. 3585 * (6) HTT_TX_SELFGEN_SCH_TSFLAG_RESP_TOO_LATE_RECEIVED_ERR - Response frame 3586 * received outside RX window. 3587 * (7) HTT_TX_SELFGEN_SCH_TSFLAG_SIFS_STALL_NO_NEXT_CMD_ERR - No frame 3588 * received by HW for queuing within SIFS interval. 3589 */ 3590 3591 typedef struct { 3592 htt_tlv_hdr_t tlv_hdr; 3593 /** 11AC VHT SU NDPA scheduler completion status reason code */ 3594 A_UINT32 ac_su_ndpa_sch_status[HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 3595 /** 11AC VHT SU NDP scheduler completion status reason code */ 3596 A_UINT32 ac_su_ndp_sch_status[HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 3597 /** 11AC VHT SU NDP scheduler error code */ 3598 A_UINT32 ac_su_ndp_sch_flag_err[HTT_TX_SELFGEN_NUM_SCH_TSFLAG_ERROR_STATS]; 3599 /** 11AC VHT MU MIMO NDPA scheduler completion status reason code */ 3600 A_UINT32 ac_mu_mimo_ndpa_sch_status[HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 3601 /** 11AC VHT MU MIMO NDP scheduler completion status reason code */ 3602 A_UINT32 ac_mu_mimo_ndp_sch_status[HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 3603 /** 11AC VHT MU MIMO NDP scheduler error code */ 3604 A_UINT32 ac_mu_mimo_ndp_sch_flag_err[HTT_TX_SELFGEN_NUM_SCH_TSFLAG_ERROR_STATS]; 3605 /** 11AC VHT MU MIMO BRPOLL scheduler completion status reason code */ 3606 A_UINT32 ac_mu_mimo_brp_sch_status[HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 3607 /** 11AC VHT MU MIMO BRPOLL scheduler error code */ 3608 A_UINT32 ac_mu_mimo_brp_sch_flag_err[HTT_TX_SELFGEN_NUM_SCH_TSFLAG_ERROR_STATS]; 3609 } htt_stats_tx_selfgen_ac_sched_status_stats_tlv; 3610 /* preserve old name alias for new name consistent with the tag name */ 3611 typedef htt_stats_tx_selfgen_ac_sched_status_stats_tlv 3612 htt_tx_selfgen_ac_sched_status_stats_tlv; 3613 3614 typedef struct { 3615 htt_tlv_hdr_t tlv_hdr; 3616 /** 11AX HE SU NDPA scheduler completion status reason code */ 3617 A_UINT32 ax_su_ndpa_sch_status[HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 3618 /** 11AX SU NDP scheduler completion status reason code */ 3619 A_UINT32 ax_su_ndp_sch_status[HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 3620 /** 11AX HE SU NDP scheduler error code */ 3621 A_UINT32 ax_su_ndp_sch_flag_err[HTT_TX_SELFGEN_NUM_SCH_TSFLAG_ERROR_STATS]; 3622 /** 11AX HE MU MIMO NDPA scheduler completion status reason code */ 3623 A_UINT32 ax_mu_mimo_ndpa_sch_status[HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 3624 /** 11AX HE MU MIMO NDP scheduler completion status reason code */ 3625 A_UINT32 ax_mu_mimo_ndp_sch_status[HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 3626 /** 11AX HE MU MIMO NDP scheduler error code */ 3627 A_UINT32 ax_mu_mimo_ndp_sch_flag_err[HTT_TX_SELFGEN_NUM_SCH_TSFLAG_ERROR_STATS]; 3628 /** 11AX HE MU MIMO MU BRPOLL scheduler completion status reason code */ 3629 A_UINT32 ax_mu_brp_sch_status[HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 3630 /** 11AX HE MU MIMO MU BRPOLL scheduler error code */ 3631 A_UINT32 ax_mu_brp_sch_flag_err[HTT_TX_SELFGEN_NUM_SCH_TSFLAG_ERROR_STATS]; 3632 /** 11AX HE MU BAR scheduler completion status reason code */ 3633 A_UINT32 ax_mu_bar_sch_status[HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 3634 /** 11AX HE MU BAR scheduler error code */ 3635 A_UINT32 ax_mu_bar_sch_flag_err[HTT_TX_SELFGEN_NUM_SCH_TSFLAG_ERROR_STATS]; 3636 /** 3637 * 11AX HE UL OFDMA Basic Trigger scheduler completion status reason code 3638 */ 3639 A_UINT32 ax_basic_trig_sch_status[HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 3640 /** 11AX HE UL OFDMA Basic Trigger scheduler error code */ 3641 A_UINT32 ax_basic_trig_sch_flag_err[HTT_TX_SELFGEN_NUM_SCH_TSFLAG_ERROR_STATS]; 3642 /** 3643 * 11AX HE UL MUMIMO Basic Trigger scheduler completion status reason code 3644 */ 3645 A_UINT32 ax_ulmumimo_trig_sch_status[HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 3646 /** 11AX HE UL MUMIMO Basic Trigger scheduler error code */ 3647 A_UINT32 ax_ulmumimo_trig_sch_flag_err[HTT_TX_SELFGEN_NUM_SCH_TSFLAG_ERROR_STATS]; 3648 } htt_stats_tx_selfgen_ax_sched_status_stats_tlv; 3649 /* preserve old name alias for new name consistent with the tag name */ 3650 typedef htt_stats_tx_selfgen_ax_sched_status_stats_tlv 3651 htt_tx_selfgen_ax_sched_status_stats_tlv; 3652 3653 typedef struct { 3654 htt_tlv_hdr_t tlv_hdr; 3655 /** 11BE EHT SU NDPA scheduler completion status reason code */ 3656 A_UINT32 be_su_ndpa_sch_status[HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 3657 /** 11BE SU NDP scheduler completion status reason code */ 3658 A_UINT32 be_su_ndp_sch_status[HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 3659 /** 11BE EHT SU NDP scheduler error code */ 3660 A_UINT32 be_su_ndp_sch_flag_err[HTT_TX_SELFGEN_NUM_SCH_TSFLAG_ERROR_STATS]; 3661 /** 11BE EHT MU MIMO NDPA scheduler completion status reason code */ 3662 A_UINT32 be_mu_mimo_ndpa_sch_status[HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 3663 /** 11BE EHT MU MIMO NDP scheduler completion status reason code */ 3664 A_UINT32 be_mu_mimo_ndp_sch_status[HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 3665 /** 11BE EHT MU MIMO NDP scheduler error code */ 3666 A_UINT32 be_mu_mimo_ndp_sch_flag_err[HTT_TX_SELFGEN_NUM_SCH_TSFLAG_ERROR_STATS]; 3667 /** 11BE EHT MU MIMO MU BRPOLL scheduler completion status reason code */ 3668 A_UINT32 be_mu_brp_sch_status[HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 3669 /** 11BE EHT MU MIMO MU BRPOLL scheduler error code */ 3670 A_UINT32 be_mu_brp_sch_flag_err[HTT_TX_SELFGEN_NUM_SCH_TSFLAG_ERROR_STATS]; 3671 /** 11BE EHT MU BAR scheduler completion status reason code */ 3672 A_UINT32 be_mu_bar_sch_status[HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 3673 /** 11BE EHT MU BAR scheduler error code */ 3674 A_UINT32 be_mu_bar_sch_flag_err[HTT_TX_SELFGEN_NUM_SCH_TSFLAG_ERROR_STATS]; 3675 /** 3676 * 11BE EHT UL OFDMA Basic Trigger scheduler completion status reason code 3677 */ 3678 A_UINT32 be_basic_trig_sch_status[HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 3679 /** 11BE EHT UL OFDMA Basic Trigger scheduler error code */ 3680 A_UINT32 be_basic_trig_sch_flag_err[HTT_TX_SELFGEN_NUM_SCH_TSFLAG_ERROR_STATS]; 3681 /** 3682 * 11BE EHT UL MUMIMO Basic Trigger scheduler completion status reason code 3683 */ 3684 A_UINT32 be_ulmumimo_trig_sch_status[HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 3685 /** 11BE EHT UL MUMIMO Basic Trigger scheduler error code */ 3686 A_UINT32 be_ulmumimo_trig_sch_flag_err[HTT_TX_SELFGEN_NUM_SCH_TSFLAG_ERROR_STATS]; 3687 } htt_stats_tx_selfgen_be_sched_status_stats_tlv; 3688 /* preserve old name alias for new name consistent with the tag name */ 3689 typedef htt_stats_tx_selfgen_be_sched_status_stats_tlv 3690 htt_tx_selfgen_be_sched_status_stats_tlv; 3691 3692 /* STATS_TYPE : HTT_DBG_EXT_STATS_TX_SELFGEN_INFO 3693 * TLV_TAGS: 3694 * - HTT_STATS_TX_SELFGEN_CMN_STATS_TAG 3695 * - HTT_STATS_TX_SELFGEN_AC_STATS_TAG 3696 * - HTT_STATS_TX_SELFGEN_AX_STATS_TAG 3697 * - HTT_STATS_TX_SELFGEN_AC_ERR_STATS_TAG 3698 * - HTT_STATS_TX_SELFGEN_AX_ERR_STATS_TAG 3699 * - HTT_STATS_TX_SELFGEN_AC_SCHED_STATUS_STATS_TAG 3700 * - HTT_STATS_TX_SELFGEN_AX_SCHED_STATUS_STATS_TAG 3701 * - HTT_STATS_TX_SELFGEN_BE_STATS_TAG 3702 * - HTT_STATS_TX_SELFGEN_BE_ERR_STATS_TAG 3703 * - HTT_STATS_TX_SELFGEN_BE_SCHED_STATUS_STATS_TAG 3704 */ 3705 /* NOTE: 3706 * This structure is for documentation, and cannot be safely used directly. 3707 * Instead, use the constituent TLV structures to fill/parse. 3708 */ 3709 #ifdef ATH_TARGET 3710 typedef struct { 3711 htt_stats_tx_selfgen_cmn_stats_tlv cmn_tlv; 3712 htt_stats_tx_selfgen_ac_stats_tlv ac_tlv; 3713 htt_stats_tx_selfgen_ax_stats_tlv ax_tlv; 3714 htt_stats_tx_selfgen_ac_err_stats_tlv ac_err_tlv; 3715 htt_stats_tx_selfgen_ax_err_stats_tlv ax_err_tlv; 3716 htt_stats_tx_selfgen_ac_sched_status_stats_tlv ac_sched_status_tlv; 3717 htt_stats_tx_selfgen_ax_sched_status_stats_tlv ax_sched_status_tlv; 3718 htt_stats_tx_selfgen_be_stats_tlv be_tlv; 3719 htt_stats_tx_selfgen_be_err_stats_tlv be_err_tlv; 3720 htt_stats_tx_selfgen_be_sched_status_stats_tlv be_sched_status_tlv; 3721 } htt_tx_pdev_selfgen_stats_t; 3722 #endif /* ATH_TARGET */ 3723 3724 /* == TX MU STATS == */ 3725 3726 typedef struct { 3727 htt_tlv_hdr_t tlv_hdr; 3728 /** Number of MU MIMO schedules posted to HW */ 3729 A_UINT32 mu_mimo_sch_posted; 3730 /** Number of MU MIMO schedules failed to post */ 3731 A_UINT32 mu_mimo_sch_failed; 3732 /** Number of MU MIMO PPDUs posted to HW */ 3733 A_UINT32 mu_mimo_ppdu_posted; 3734 /* 3735 * This is the common description for the below sch stats. 3736 * Counts the number of transmissions of each number of MU users 3737 * in each TX mode. 3738 * The array index is the "number of users - 1". 3739 * For example, ac_mu_mimo_sch_nusers[1] counts the number of 11AC MU2 3740 * TX PPDUs, ac_mu_mimo_sch_nusers[2] counts the number of 11AC MU3 3741 * TX PPDUs and so on. 3742 * The same is applicable for the other TX mode stats. 3743 */ 3744 /** Represents the count for 11AC DL MU MIMO sequences */ 3745 A_UINT32 ac_mu_mimo_sch_nusers[HTT_TX_PDEV_STATS_NUM_AC_MUMIMO_USER_STATS]; 3746 /** Represents the count for 11AX DL MU MIMO sequences */ 3747 A_UINT32 ax_mu_mimo_sch_nusers[HTT_TX_PDEV_STATS_NUM_AX_MUMIMO_USER_STATS]; 3748 /** Represents the count for 11AX DL MU OFDMA sequences */ 3749 A_UINT32 ax_ofdma_sch_nusers[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; 3750 /** 3751 * Represents the count for 11AX UL MU OFDMA sequences with Basic Triggers 3752 */ 3753 A_UINT32 ax_ul_ofdma_basic_sch_nusers[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; 3754 /** Represents the count for 11AX UL MU OFDMA sequences with BSRP Triggers */ 3755 A_UINT32 ax_ul_ofdma_bsr_sch_nusers[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; 3756 /** Represents the count for 11AX UL MU OFDMA sequences with BAR Triggers */ 3757 A_UINT32 ax_ul_ofdma_bar_sch_nusers[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; 3758 /** Represents the count for 11AX UL MU OFDMA sequences with BRP Triggers */ 3759 A_UINT32 ax_ul_ofdma_brp_sch_nusers[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; 3760 /** 3761 * Represents the count for 11AX UL MU MIMO sequences with Basic Triggers 3762 */ 3763 A_UINT32 ax_ul_mumimo_basic_sch_nusers[HTT_TX_PDEV_STATS_NUM_UL_MUMIMO_USER_STATS]; 3764 /** Represents the count for 11AX UL MU MIMO sequences with BRP Triggers */ 3765 A_UINT32 ax_ul_mumimo_brp_sch_nusers[HTT_TX_PDEV_STATS_NUM_UL_MUMIMO_USER_STATS]; 3766 /** Number of 11AC DL MU MIMO schedules posted per group size (0-3) */ 3767 A_UINT32 ac_mu_mimo_sch_posted_per_grp_sz[HTT_TX_PDEV_STATS_NUM_AC_MUMIMO_USER_STATS]; 3768 /** Number of 11AX DL MU MIMO schedules posted per group size */ 3769 A_UINT32 ax_mu_mimo_sch_posted_per_grp_sz[HTT_TX_PDEV_STATS_NUM_AX_MUMIMO_USER_STATS]; 3770 /** Represents the count for 11BE DL MU MIMO sequences */ 3771 A_UINT32 be_mu_mimo_sch_nusers[HTT_TX_PDEV_STATS_NUM_BE_MUMIMO_USER_STATS]; 3772 /** Number of 11BE DL MU MIMO schedules posted per group size */ 3773 A_UINT32 be_mu_mimo_sch_posted_per_grp_sz[HTT_TX_PDEV_STATS_NUM_BE_MUMIMO_USER_STATS]; 3774 /** Number of 11AC DL MU MIMO schedules posted per group size (4-7) */ 3775 A_UINT32 ac_mu_mimo_sch_posted_per_grp_sz_ext[HTT_TX_PDEV_STATS_NUM_AC_MUMIMO_USER_STATS]; 3776 } htt_stats_tx_pdev_mu_mimo_stats_tlv; 3777 /* preserve old name alias for new name consistent with the tag name */ 3778 typedef htt_stats_tx_pdev_mu_mimo_stats_tlv htt_tx_pdev_mu_mimo_sch_stats_tlv; 3779 3780 typedef struct { 3781 htt_tlv_hdr_t tlv_hdr; 3782 A_UINT32 dl_mumimo_grp_best_grp_size[HTT_STATS_MAX_MUMIMO_GRP_SZ]; 3783 3784 A_UINT32 dl_mumimo_grp_best_num_usrs[HTT_TX_PDEV_STATS_NUM_AX_MUMIMO_USER_STATS]; 3785 3786 A_UINT32 dl_mumimo_grp_eligible[HTT_STATS_MAX_MUMIMO_GRP_SZ]; 3787 3788 A_UINT32 dl_mumimo_grp_ineligible[HTT_STATS_MAX_MUMIMO_GRP_SZ]; 3789 3790 A_UINT32 dl_mumimo_grp_invalid[HTT_TX_NUM_MUMIMO_GRP_INVALID_WORDS]; 3791 3792 A_UINT32 dl_mumimo_grp_tputs[HTT_STATS_MUMIMO_TPUT_NUM_BINS]; 3793 3794 A_UINT32 ul_mumimo_grp_best_grp_size[HTT_STATS_MAX_MUMIMO_GRP_SZ]; 3795 3796 A_UINT32 ul_mumimo_grp_best_num_usrs[HTT_TX_PDEV_STATS_NUM_AX_MUMIMO_USER_STATS]; 3797 3798 A_UINT32 ul_mumimo_grp_tputs[HTT_STATS_MUMIMO_TPUT_NUM_BINS]; 3799 } htt_stats_tx_pdev_mumimo_grp_stats_tlv; 3800 /* preserve old name alias for new name consistent with the tag name */ 3801 typedef htt_stats_tx_pdev_mumimo_grp_stats_tlv htt_tx_pdev_mumimo_grp_stats_tlv; 3802 3803 typedef struct { 3804 htt_tlv_hdr_t tlv_hdr; 3805 /** Number of MU MIMO schedules posted to HW */ 3806 A_UINT32 mu_mimo_sch_posted; 3807 /** Number of MU MIMO schedules failed to post */ 3808 A_UINT32 mu_mimo_sch_failed; 3809 /** Number of MU MIMO PPDUs posted to HW */ 3810 A_UINT32 mu_mimo_ppdu_posted; 3811 /* 3812 * This is the common description for the below sch stats. 3813 * Counts the number of transmissions of each number of MU users 3814 * in each TX mode. 3815 * The array index is the "number of users - 1". 3816 * For example, ac_mu_mimo_sch_nusers[1] counts the number of 11AC MU2 3817 * TX PPDUs, ac_mu_mimo_sch_nusers[2] counts the number of 11AC MU3 3818 * TX PPDUs and so on. 3819 * The same is applicable for the other TX mode stats. 3820 */ 3821 /** Represents the count for 11AC DL MU MIMO sequences */ 3822 A_UINT32 ac_mu_mimo_sch_nusers[HTT_TX_PDEV_STATS_NUM_AC_MUMIMO_USER_STATS]; 3823 /** Represents the count for 11AX DL MU MIMO sequences */ 3824 A_UINT32 ax_mu_mimo_sch_nusers[HTT_TX_PDEV_STATS_NUM_AX_MUMIMO_USER_STATS]; 3825 /** Number of 11AC DL MU MIMO schedules posted per group size (0-3) */ 3826 A_UINT32 ac_mu_mimo_sch_posted_per_grp_sz[HTT_TX_PDEV_STATS_NUM_AC_MUMIMO_USER_STATS]; 3827 /** Number of 11AX DL MU MIMO schedules posted per group size */ 3828 A_UINT32 ax_mu_mimo_sch_posted_per_grp_sz[HTT_TX_PDEV_STATS_NUM_AX_MUMIMO_USER_STATS]; 3829 /** Represents the count for 11BE DL MU MIMO sequences */ 3830 A_UINT32 be_mu_mimo_sch_nusers[HTT_TX_PDEV_STATS_NUM_BE_MUMIMO_USER_STATS]; 3831 /** Number of 11BE DL MU MIMO schedules posted per group size */ 3832 A_UINT32 be_mu_mimo_sch_posted_per_grp_sz[HTT_TX_PDEV_STATS_NUM_BE_MUMIMO_USER_STATS]; 3833 /** Number of 11AC DL MU MIMO schedules posted per group size (4 - 7)*/ 3834 A_UINT32 ac_mu_mimo_sch_posted_per_grp_sz_ext[HTT_TX_PDEV_STATS_NUM_AC_MUMIMO_USER_STATS]; 3835 } htt_stats_tx_pdev_dl_mu_mimo_stats_tlv; 3836 /* preserve old name alias for new name consistent with the tag name */ 3837 typedef htt_stats_tx_pdev_dl_mu_mimo_stats_tlv 3838 htt_tx_pdev_dl_mu_mimo_sch_stats_tlv; 3839 3840 typedef struct { 3841 htt_tlv_hdr_t tlv_hdr; 3842 /** Represents the count for 11AX DL MU OFDMA sequences */ 3843 A_UINT32 ax_mu_ofdma_sch_nusers[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; 3844 } htt_stats_tx_pdev_dl_mu_ofdma_stats_tlv; 3845 /* preserve old name alias for new name consistent with the tag name */ 3846 typedef htt_stats_tx_pdev_dl_mu_ofdma_stats_tlv 3847 htt_tx_pdev_dl_mu_ofdma_sch_stats_tlv; 3848 3849 typedef struct { 3850 htt_tlv_hdr_t tlv_hdr; 3851 /** Represents the count for 11BE DL MU OFDMA sequences */ 3852 A_UINT32 be_mu_ofdma_sch_nusers[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; 3853 } htt_stats_tx_pdev_be_dl_mu_ofdma_stats_tlv; 3854 /* preserve old name alias for new name consistent with the tag name */ 3855 typedef htt_stats_tx_pdev_be_dl_mu_ofdma_stats_tlv 3856 htt_tx_pdev_be_dl_mu_ofdma_sch_stats_tlv; 3857 3858 typedef struct { 3859 htt_tlv_hdr_t tlv_hdr; 3860 /** 3861 * Represents the count for 11AX UL MU OFDMA sequences with Basic Triggers 3862 */ 3863 A_UINT32 ax_ul_mu_ofdma_basic_sch_nusers[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; 3864 /** 3865 * Represents the count for 11AX UL MU OFDMA sequences with BSRP Triggers 3866 */ 3867 A_UINT32 ax_ul_mu_ofdma_bsr_sch_nusers[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; 3868 /** 3869 * Represents the count for 11AX UL MU OFDMA sequences with BAR Triggers 3870 */ 3871 A_UINT32 ax_ul_mu_ofdma_bar_sch_nusers[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; 3872 /** 3873 * Represents the count for 11AX UL MU OFDMA sequences with BRP Triggers 3874 */ 3875 A_UINT32 ax_ul_mu_ofdma_brp_sch_nusers[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; 3876 } htt_stats_tx_pdev_ul_mu_ofdma_stats_tlv; 3877 /* preserve old name alias for new name consistent with the tag name */ 3878 typedef htt_stats_tx_pdev_ul_mu_ofdma_stats_tlv 3879 htt_tx_pdev_ul_mu_ofdma_sch_stats_tlv; 3880 3881 typedef struct { 3882 htt_tlv_hdr_t tlv_hdr; 3883 /** 3884 * Represents the count for 11BE UL MU OFDMA sequences with Basic Triggers 3885 */ 3886 A_UINT32 be_ul_mu_ofdma_basic_sch_nusers[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; 3887 /** 3888 * Represents the count for 11BE UL MU OFDMA sequences with BSRP Triggers 3889 */ 3890 A_UINT32 be_ul_mu_ofdma_bsr_sch_nusers[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; 3891 /** 3892 * Represents the count for 11BE UL MU OFDMA sequences with BAR Triggers 3893 */ 3894 A_UINT32 be_ul_mu_ofdma_bar_sch_nusers[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; 3895 /** 3896 * Represents the count for 11BE UL MU OFDMA sequences with BRP Triggers 3897 */ 3898 A_UINT32 be_ul_mu_ofdma_brp_sch_nusers[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; 3899 } htt_stats_tx_pdev_be_ul_mu_ofdma_stats_tlv; 3900 /* preserve old name alias for new name consistent with the tag name */ 3901 typedef htt_stats_tx_pdev_be_ul_mu_ofdma_stats_tlv 3902 htt_tx_pdev_be_ul_mu_ofdma_sch_stats_tlv; 3903 3904 typedef struct { 3905 htt_tlv_hdr_t tlv_hdr; 3906 /** 3907 * Represents the count for 11AX UL MU MIMO sequences with Basic Triggers 3908 */ 3909 A_UINT32 ax_ul_mu_mimo_basic_sch_nusers[HTT_TX_PDEV_STATS_NUM_UL_MUMIMO_USER_STATS]; 3910 /** 3911 * Represents the count for 11AX UL MU MIMO sequences with BRP Triggers 3912 */ 3913 A_UINT32 ax_ul_mu_mimo_brp_sch_nusers[HTT_TX_PDEV_STATS_NUM_UL_MUMIMO_USER_STATS]; 3914 } htt_stats_tx_pdev_ul_mu_mimo_stats_tlv; 3915 /* preserve old name alias for new name consistent with the tag name */ 3916 typedef htt_stats_tx_pdev_ul_mu_mimo_stats_tlv 3917 htt_tx_pdev_ul_mu_mimo_sch_stats_tlv; 3918 3919 typedef struct { 3920 htt_tlv_hdr_t tlv_hdr; 3921 /** 3922 * Represents the count for 11BE UL MU MIMO sequences with Basic Triggers 3923 */ 3924 A_UINT32 be_ul_mu_mimo_basic_sch_nusers[HTT_TX_PDEV_STATS_NUM_UL_MUMIMO_USER_STATS]; 3925 /** 3926 * Represents the count for 11BE UL MU MIMO sequences with BRP Triggers 3927 */ 3928 A_UINT32 be_ul_mu_mimo_brp_sch_nusers[HTT_TX_PDEV_STATS_NUM_UL_MUMIMO_USER_STATS]; 3929 } htt_stats_tx_pdev_be_ul_mu_mimo_stats_tlv; 3930 /* preserve old name alias for new name consistent with the tag name */ 3931 typedef htt_stats_tx_pdev_be_ul_mu_mimo_stats_tlv 3932 htt_tx_pdev_be_ul_mu_mimo_sch_stats_tlv; 3933 3934 typedef struct { 3935 htt_tlv_hdr_t tlv_hdr; 3936 /** 11AC DL MU MIMO number of mpdus queued to HW, per user */ 3937 A_UINT32 mu_mimo_mpdus_queued_usr; 3938 /** 11AC DL MU MIMO number of mpdus tried over the air, per user */ 3939 A_UINT32 mu_mimo_mpdus_tried_usr; 3940 /** 11AC DL MU MIMO number of mpdus failed acknowledgement, per user */ 3941 A_UINT32 mu_mimo_mpdus_failed_usr; 3942 /** 11AC DL MU MIMO number of mpdus re-queued to HW, per user */ 3943 A_UINT32 mu_mimo_mpdus_requeued_usr; 3944 /** 11AC DL MU MIMO BA not received, per user */ 3945 A_UINT32 mu_mimo_err_no_ba_usr; 3946 /** 11AC DL MU MIMO mpdu underrun encountered, per user */ 3947 A_UINT32 mu_mimo_mpdu_underrun_usr; 3948 /** 11AC DL MU MIMO ampdu underrun encountered, per user */ 3949 A_UINT32 mu_mimo_ampdu_underrun_usr; 3950 3951 /** 11AX MU MIMO number of mpdus queued to HW, per user */ 3952 A_UINT32 ax_mu_mimo_mpdus_queued_usr; 3953 /** 11AX MU MIMO number of mpdus tried over the air, per user */ 3954 A_UINT32 ax_mu_mimo_mpdus_tried_usr; 3955 /** 11AX DL MU MIMO number of mpdus failed acknowledgement, per user */ 3956 A_UINT32 ax_mu_mimo_mpdus_failed_usr; 3957 /** 11AX DL MU MIMO number of mpdus re-queued to HW, per user */ 3958 A_UINT32 ax_mu_mimo_mpdus_requeued_usr; 3959 /** 11AX DL MU MIMO BA not received, per user */ 3960 A_UINT32 ax_mu_mimo_err_no_ba_usr; 3961 /** 11AX DL MU MIMO mpdu underrun encountered, per user */ 3962 A_UINT32 ax_mu_mimo_mpdu_underrun_usr; 3963 /** 11AX DL MU MIMO ampdu underrun encountered, per user */ 3964 A_UINT32 ax_mu_mimo_ampdu_underrun_usr; 3965 3966 /** 11AX MU OFDMA number of mpdus queued to HW, per user */ 3967 A_UINT32 ax_ofdma_mpdus_queued_usr; 3968 /** 11AX MU OFDMA number of mpdus tried over the air, per user */ 3969 A_UINT32 ax_ofdma_mpdus_tried_usr; 3970 /** 11AX MU OFDMA number of mpdus failed acknowledgement, per user */ 3971 A_UINT32 ax_ofdma_mpdus_failed_usr; 3972 /** 11AX MU OFDMA number of mpdus re-queued to HW, per user */ 3973 A_UINT32 ax_ofdma_mpdus_requeued_usr; 3974 /** 11AX MU OFDMA BA not received, per user */ 3975 A_UINT32 ax_ofdma_err_no_ba_usr; 3976 /** 11AX MU OFDMA mpdu underrun encountered, per user */ 3977 A_UINT32 ax_ofdma_mpdu_underrun_usr; 3978 /** 11AX MU OFDMA ampdu underrun encountered, per user */ 3979 A_UINT32 ax_ofdma_ampdu_underrun_usr; 3980 } htt_stats_tx_pdev_mumimo_mpdu_stats_tlv; 3981 /* preserve old name alias for new name consistent with the tag name */ 3982 typedef htt_stats_tx_pdev_mumimo_mpdu_stats_tlv 3983 htt_tx_pdev_mu_mimo_mpdu_stats_tlv; 3984 3985 #define HTT_STATS_TX_SCHED_MODE_MU_MIMO_AC 1 /* SCHED_TX_MODE_MU_MIMO_AC */ 3986 #define HTT_STATS_TX_SCHED_MODE_MU_MIMO_AX 2 /* SCHED_TX_MODE_MU_MIMO_AX */ 3987 #define HTT_STATS_TX_SCHED_MODE_MU_OFDMA_AX 3 /* SCHED_TX_MODE_MU_OFDMA_AX */ 3988 #define HTT_STATS_TX_SCHED_MODE_MU_OFDMA_BE 4 /* SCHED_TX_MODE_MU_OFDMA_BE */ 3989 #define HTT_STATS_TX_SCHED_MODE_MU_MIMO_BE 5 /* SCHED_TX_MODE_MU_MIMO_BE */ 3990 3991 typedef struct { 3992 htt_tlv_hdr_t tlv_hdr; 3993 /* mpdu level stats */ 3994 A_UINT32 mpdus_queued_usr; 3995 A_UINT32 mpdus_tried_usr; 3996 A_UINT32 mpdus_failed_usr; 3997 A_UINT32 mpdus_requeued_usr; 3998 A_UINT32 err_no_ba_usr; 3999 A_UINT32 mpdu_underrun_usr; 4000 A_UINT32 ampdu_underrun_usr; 4001 A_UINT32 user_index; 4002 /** HTT_STATS_TX_SCHED_MODE_xxx */ 4003 A_UINT32 tx_sched_mode; 4004 } htt_stats_tx_pdev_mpdu_stats_tlv; 4005 /* preserve old name alias for new name consistent with the tag name */ 4006 typedef htt_stats_tx_pdev_mpdu_stats_tlv htt_tx_pdev_mpdu_stats_tlv; 4007 4008 /* STATS_TYPE : HTT_DBG_EXT_STATS_PDEV_TX_MU 4009 * TLV_TAGS: 4010 * - HTT_STATS_TX_PDEV_MU_MIMO_STATS_TAG (multiple) 4011 * - HTT_STATS_TX_PDEV_MPDU_STATS_TAG (multiple) 4012 */ 4013 /* NOTE: 4014 * This structure is for documentation, and cannot be safely used directly. 4015 * Instead, use the constituent TLV structures to fill/parse. 4016 */ 4017 #ifdef ATH_TARGET 4018 typedef struct { 4019 htt_stats_tx_pdev_mu_mimo_stats_tlv mu_mimo_sch_stats_tlv[1]; /* WAL_TX_STATS_MAX_GROUP_SIZE */ 4020 htt_stats_tx_pdev_dl_mu_mimo_stats_tlv dl_mu_mimo_sch_stats_tlv[1]; 4021 htt_stats_tx_pdev_ul_mu_mimo_stats_tlv ul_mu_mimo_sch_stats_tlv[1]; 4022 htt_stats_tx_pdev_dl_mu_ofdma_stats_tlv dl_mu_ofdma_sch_stats_tlv[1]; 4023 htt_stats_tx_pdev_ul_mu_ofdma_stats_tlv ul_mu_ofdma_sch_stats_tlv[1]; 4024 /* 4025 * Note that though mu_mimo_mpdu_stats_tlv is named MU-MIMO, 4026 * it can also hold MU-OFDMA stats. 4027 */ 4028 htt_stats_tx_pdev_mpdu_stats_tlv mu_mimo_mpdu_stats_tlv[1]; /* WAL_TX_STATS_MAX_NUM_USERS */ 4029 htt_stats_tx_pdev_mumimo_grp_stats_tlv mumimo_grp_stats_tlv; 4030 } htt_tx_pdev_mu_mimo_stats_t; 4031 #endif /* ATH_TARGET */ 4032 4033 /* == TX SCHED STATS == */ 4034 4035 #define HTT_SCHED_TXQ_CMD_POSTED_TLV_SZ(_num_elems) (sizeof(A_UINT32) * (_num_elems)) 4036 4037 /* NOTE: Variable length TLV, use length spec to infer array size */ 4038 typedef struct { 4039 htt_tlv_hdr_t tlv_hdr; 4040 /** Scheduler command posted per tx_mode */ 4041 A_UINT32 sched_cmd_posted[1/* length = num tx modes */]; 4042 } htt_stats_sched_txq_cmd_posted_tlv; 4043 /* preserve old name alias for new name consistent with the tag name */ 4044 typedef htt_stats_sched_txq_cmd_posted_tlv htt_sched_txq_cmd_posted_tlv_v; 4045 4046 #define HTT_SCHED_TXQ_CMD_REAPED_TLV_SZ(_num_elems) (sizeof(A_UINT32) * (_num_elems)) 4047 4048 /* NOTE: Variable length TLV, use length spec to infer array size */ 4049 typedef struct { 4050 htt_tlv_hdr_t tlv_hdr; 4051 /** Scheduler command reaped per tx_mode */ 4052 A_UINT32 sched_cmd_reaped[1/* length = num tx modes */]; 4053 } htt_stats_sched_txq_cmd_reaped_tlv; 4054 /* preserve old name alias for new name consistent with the tag name */ 4055 typedef htt_stats_sched_txq_cmd_reaped_tlv htt_sched_txq_cmd_reaped_tlv_v; 4056 4057 #define HTT_SCHED_TXQ_SCHED_ORDER_SU_TLV_SZ(_num_elems) (sizeof(A_UINT32) * (_num_elems)) 4058 4059 /* NOTE: Variable length TLV, use length spec to infer array size */ 4060 typedef struct { 4061 htt_tlv_hdr_t tlv_hdr; 4062 /** 4063 * sched_order_su contains the peer IDs of peers chosen in the last 4064 * NUM_SCHED_ORDER_LOG scheduler instances. 4065 * The array is circular; it's unspecified which array element corresponds 4066 * to the most recent scheduler invocation, and which corresponds to 4067 * the (NUM_SCHED_ORDER_LOG-1) most recent scheduler invocation. 4068 * 4069 * HTT_TX_PDEV_NUM_SCHED_ORDER_LOG 4070 */ 4071 HTT_STATS_VAR_LEN_ARRAY1(A_UINT32, sched_order_su); 4072 } htt_stats_sched_txq_sched_order_su_tlv; 4073 /* preserve old name alias for new name consistent with the tag name */ 4074 typedef htt_stats_sched_txq_sched_order_su_tlv htt_sched_txq_sched_order_su_tlv_v; 4075 4076 typedef struct { 4077 htt_tlv_hdr_t tlv_hdr; 4078 A_UINT32 htt_stats_type; 4079 } htt_stats_error_tlv_v; 4080 4081 typedef enum { 4082 HTT_SCHED_TID_SKIP_SCHED_MASK_DISABLED = 0, /* Skip the tid when WAL_TID_DISABLE_TX_SCHED_MASK is true */ 4083 HTT_SCHED_TID_SKIP_NOTIFY_MPDU, /* Skip the tid's 2nd sched_cmd when 1st cmd is ongoing */ 4084 HTT_SCHED_TID_SKIP_MPDU_STATE_INVALID, /* Skip the tid when MPDU state is invalid */ 4085 HTT_SCHED_TID_SKIP_SCHED_DISABLED, /* Skip the tid when scheduling is disabled for that tid */ 4086 HTT_SCHED_TID_SKIP_TQM_BYPASS_CMD_PENDING, /* Skip the TQM bypass tid when it has pending sched_cmd */ 4087 HTT_SCHED_TID_SKIP_SECOND_SU_SCHEDULE, /* Skip tid from 2nd SU schedule when any of the following flag is set 4088 WAL_TX_TID(SEND_BAR | TQM_MPDU_STATE_VALID | SEND_QOS_NULL | TQM_NOTIFY_MPDU | SENDN_PENDING) */ 4089 HTT_SCHED_TID_SKIP_CMD_SLOT_NOT_AVAIL, /* Skip the tid when command slot is not available */ 4090 HTT_SCHED_TID_SKIP_NO_DATA, /* Skip tid without data */ 4091 HTT_SCHED_TID_SKIP_NO_ENQ = HTT_SCHED_TID_SKIP_NO_DATA, /* deprecated old name */ 4092 HTT_SCHED_TID_SKIP_LOW_ENQ, /* Skip the tid when enqueue is low */ 4093 HTT_SCHED_TID_SKIP_PAUSED, /* Skipping the paused tid(sendn-frames) */ 4094 HTT_SCHED_TID_SKIP_UL_RESP, /* skip UL response tid */ 4095 HTT_SCHED_TID_SKIP_UL = HTT_SCHED_TID_SKIP_UL_RESP, /* deprecated old name */ 4096 HTT_SCHED_TID_REMOVE_PAUSED, /* Removing the paused tid when number of sendn frames is zero */ 4097 HTT_SCHED_TID_REMOVE_NO_ENQ, /* Remove tid with zero queue depth */ 4098 HTT_SCHED_TID_REMOVE_UL_RESP, /* Remove tid UL response */ 4099 HTT_SCHED_TID_REMOVE_UL = HTT_SCHED_TID_REMOVE_UL_RESP, /* deprecated old name */ 4100 HTT_SCHED_TID_QUERY, /* Moving to next user and adding tid in prepend list when qstats update is pending */ 4101 HTT_SCHED_TID_SU_ONLY, /* Tid is eligible and TX_SCHED_SU_ONLY is true */ 4102 HTT_SCHED_TID_ELIGIBLE, /* Tid is eligible for scheduling */ 4103 HTT_SCHED_TID_SKIP_EXCEPT_EAPOL, /* skip tid except eapol */ 4104 HTT_SCHED_TID_SU_LOW_PRI_ONLY, /* su low priority tid only */ 4105 HTT_SCHED_TID_SKIP_SOUND_IN_PROGRESS, /* skip tid sound in progress */ 4106 HTT_SCHED_TID_SKIP_NO_UL_DATA, /* skip ul tid when no ul data */ 4107 HTT_SCHED_TID_REMOVE_UL_NOT_CAPABLE, /* Remove tid that are not UL capable */ 4108 HTT_SCHED_TID_UL_ELIGIBLE, /* Tid is eligible for UL scheduling */ 4109 HTT_SCHED_TID_FALLBACK_TO_PREV_DECISION, /* Fall back to previous decision */ 4110 HTT_SCHED_TID_SKIP_PEER_ALREADY_IN_TXQ, /* skip tid, peer is already available in the txq */ 4111 HTT_SCHED_TID_SKIP_DELAY_UL_SCHED, /* skip tid delay UL schedule */ 4112 HTT_SCHED_TID_SKIP_PWR_SAVE_STATE_OFF, /* Limit UL scheduling to primary link if not in power save state */ 4113 HTT_SCHED_TID_SKIP_TWT_SUSPEND, /* Skip UL trigger for certain cases ex TWT suspend */ 4114 HTT_SCHED_TID_SKIP_DISABLE_160MHZ_OFDMA, /* Skip ul tid if peer supports 160MHZ */ 4115 HTT_SCHED_TID_SKIP_ULMU_DISABLE_FROM_OMI, /* Skip ul tid if sta send omi to indicate to disable UL mu data */ 4116 HTT_SCHED_TID_SKIP_UL_MAX_SCHED_CMD_EXCEEDED,/* skip ul tid if max sched cmd is exceeded */ 4117 HTT_SCHED_TID_SKIP_UL_SMALL_QDEPTH, /* Skip ul tid for small qdepth */ 4118 HTT_SCHED_TID_SKIP_UL_TWT_PAUSED, /* Skip ul tid if twt txq is paused */ 4119 HTT_SCHED_TID_SKIP_PEER_UL_RX_NOT_ACTIVE, /* Skip ul tid if peer ul rx is not active */ 4120 HTT_SCHED_TID_SKIP_NO_FORCE_TRIGGER, /* Skip ul tid if there is no force triggers */ 4121 HTT_SCHED_TID_SKIP_SMART_BASIC_TRIGGER, /* Skip ul tid if smart basic trigger doesn't have enough data */ 4122 4123 4124 HTT_SCHED_INELIGIBILITY_MAX, 4125 } htt_sched_txq_sched_ineligibility_tlv_enum; 4126 4127 #define HTT_SCHED_TXQ_SCHED_INELIGIBILITY_TLV_SZ(_num_elems) (sizeof(A_UINT32) * (_num_elems)) 4128 4129 /* NOTE: Variable length TLV, use length spec to infer array size */ 4130 typedef struct { 4131 htt_tlv_hdr_t tlv_hdr; 4132 /** 4133 * sched_ineligibility counts the number of occurrences of different 4134 * reasons for tid ineligibility during eligibility checks per txq 4135 * in scheduling 4136 * 4137 * Indexed by htt_sched_txq_sched_ineligibility_tlv_enum. 4138 */ 4139 HTT_STATS_VAR_LEN_ARRAY1(A_UINT32, sched_ineligibility); 4140 } htt_stats_sched_txq_sched_ineligibility_tlv; 4141 /* preserve old name alias for new name consistent with the tag name */ 4142 typedef htt_stats_sched_txq_sched_ineligibility_tlv 4143 htt_sched_txq_sched_ineligibility_tlv_v; 4144 4145 typedef enum { 4146 HTT_SCHED_SUPERCYCLE_TRIGGER_NONE = 0, /* Supercycle not triggered */ 4147 HTT_SCHED_SUPERCYCLE_TRIGGER_FORCED, /* forced supercycle trigger */ 4148 HTT_SCHED_SUPERCYCLE_TRIGGER_LESS_NUM_TIDQ_ENTRIES, /* Num tidq entries is less than max_client threshold */ 4149 HTT_SCHED_SUPERCYCLE_TRIGGER_LESS_NUM_ACTIVE_TIDS, /* Num active tids is less than max_client threshold */ 4150 HTT_SCHED_SUPERCYCLE_TRIGGER_MAX_ITR_REACHED, /* max sched iteration reached */ 4151 HTT_SCHED_SUPERCYCLE_TRIGGER_DUR_THRESHOLD_REACHED, /* duration threshold reached */ 4152 HTT_SCHED_SUPERCYCLE_TRIGGER_TWT_TRIGGER, /* TWT supercycle trigger */ 4153 HTT_SCHED_SUPERCYCLE_TRIGGER_MAX, 4154 } htt_sched_txq_supercycle_triggers_tlv_enum; 4155 4156 #define HTT_SCHED_TXQ_SUPERCYCLE_TRIGGERS_TLV_SZ(_num_elems) (sizeof(A_UINT32) * (_num_elems)) 4157 4158 /* NOTE: Variable length TLV, use length spec to infer array size */ 4159 typedef struct { 4160 htt_tlv_hdr_t tlv_hdr; 4161 /** 4162 * supercycle_triggers[] is a histogram that counts the number of 4163 * occurrences of each different reason for a transmit scheduler 4164 * supercycle to be triggered. 4165 * The htt_sched_txq_supercycle_triggers_tlv_enum is used to index 4166 * supercycle_triggers[], e.g. supercycle_triggers[1] holds the number 4167 * of times a supercycle has been forced. 4168 * These supercycle trigger counts are not automatically reset, but 4169 * are reset upon request. 4170 */ 4171 A_UINT32 supercycle_triggers[1/*HTT_SCHED_SUPERCYCLE_TRIGGER_MAX*/]; 4172 } htt_stats_sched_txq_supercycle_trigger_tlv; 4173 /* preserve old name alias for new name consistent with the tag name */ 4174 typedef htt_stats_sched_txq_supercycle_trigger_tlv 4175 htt_sched_txq_supercycle_triggers_tlv_v; 4176 4177 #define HTT_TX_PDEV_STATS_SCHED_PER_TXQ_MAC_ID_M 0x000000ff 4178 #define HTT_TX_PDEV_STATS_SCHED_PER_TXQ_MAC_ID_S 0 4179 4180 #define HTT_TX_PDEV_STATS_SCHED_PER_TXQ_TXQUEUE_ID_M 0x0000ff00 4181 #define HTT_TX_PDEV_STATS_SCHED_PER_TXQ_TXQUEUE_ID_S 8 4182 4183 #define HTT_TX_PDEV_STATS_SCHED_PER_TXQ_MAC_ID_GET(_var) \ 4184 (((_var) & HTT_TX_PDEV_STATS_SCHED_PER_TXQ_MAC_ID_M) >> \ 4185 HTT_TX_PDEV_STATS_SCHED_PER_TXQ_MAC_ID_S) 4186 4187 #define HTT_TX_PDEV_STATS_SCHED_PER_TXQ_MAC_ID_SET(_var, _val) \ 4188 do { \ 4189 HTT_CHECK_SET_VAL(HTT_TX_PDEV_STATS_SCHED_PER_TXQ_MAC_ID, _val); \ 4190 ((_var) |= ((_val) << HTT_TX_PDEV_STATS_SCHED_PER_TXQ_MAC_ID_S)); \ 4191 } while (0) 4192 4193 #define HTT_TX_PDEV_STATS_SCHED_PER_TXQ_TXQUEUE_ID_GET(_var) \ 4194 (((_var) & HTT_TX_PDEV_STATS_SCHED_PER_TXQ_TXQUEUE_ID_M) >> \ 4195 HTT_TX_PDEV_STATS_SCHED_PER_TXQ_TXQUEUE_ID_S) 4196 4197 #define HTT_TX_PDEV_STATS_SCHED_PER_TXQ_TXQUEUE_ID_SET(_var, _val) \ 4198 do { \ 4199 HTT_CHECK_SET_VAL(HTT_TX_PDEV_STATS_SCHED_PER_TXQ_TXQUEUE_ID, _val); \ 4200 ((_var) |= ((_val) << HTT_TX_PDEV_STATS_SCHED_PER_TXQ_TXQUEUE_ID_S)); \ 4201 } while (0) 4202 4203 typedef struct { 4204 htt_tlv_hdr_t tlv_hdr; 4205 4206 /** 4207 * BIT [ 7 : 0] :- mac_id 4208 * BIT [15 : 8] :- txq_id 4209 * BIT [31 : 16] :- reserved 4210 */ 4211 A_UINT32 mac_id__txq_id__word; 4212 /** Scheduler policy ised for this TxQ */ 4213 A_UINT32 sched_policy; 4214 /** Timestamp of last scheduler command posted */ 4215 A_UINT32 last_sched_cmd_posted_timestamp; 4216 /** Timestamp of last scheduler command completed */ 4217 A_UINT32 last_sched_cmd_compl_timestamp; 4218 /** Num of Sched2TAC ring hit Low Water Mark condition */ 4219 A_UINT32 sched_2_tac_lwm_count; 4220 /** Num of Sched2TAC ring full condition */ 4221 A_UINT32 sched_2_tac_ring_full; 4222 /** 4223 * Num of scheduler command post failures that includes SU/MU-MIMO/MU-OFDMA 4224 * sequence type 4225 */ 4226 A_UINT32 sched_cmd_post_failure; 4227 /** Num of active tids for this TxQ at current instance */ 4228 A_UINT32 num_active_tids; 4229 /** Num of powersave schedules */ 4230 A_UINT32 num_ps_schedules; 4231 /** Num of scheduler commands pending for this TxQ */ 4232 A_UINT32 sched_cmds_pending; 4233 /** Num of tidq registration for this TxQ */ 4234 A_UINT32 num_tid_register; 4235 /** Num of tidq de-registration for this TxQ */ 4236 A_UINT32 num_tid_unregister; 4237 /** Num of iterations msduq stats was updated */ 4238 A_UINT32 num_qstats_queried; 4239 /** qstats query update status */ 4240 A_UINT32 qstats_update_pending; 4241 /** Timestamp of Last query stats made */ 4242 A_UINT32 last_qstats_query_timestamp; 4243 /** Num of sched2tqm command queue full condition */ 4244 A_UINT32 num_tqm_cmdq_full; 4245 /** Num of scheduler trigger from DE Module */ 4246 A_UINT32 num_de_sched_algo_trigger; 4247 /** Num of scheduler trigger from RT Module */ 4248 A_UINT32 num_rt_sched_algo_trigger; 4249 /** Num of scheduler trigger from TQM Module */ 4250 A_UINT32 num_tqm_sched_algo_trigger; 4251 /** Num of schedules for notify frame */ 4252 A_UINT32 notify_sched; 4253 /** Duration based sendn termination */ 4254 A_UINT32 dur_based_sendn_term; 4255 /** scheduled via NOTIFY2 */ 4256 A_UINT32 su_notify2_sched; 4257 /** schedule if queued packets are greater than avg MSDUs in PPDU */ 4258 A_UINT32 su_optimal_queued_msdus_sched; 4259 /** schedule due to timeout */ 4260 A_UINT32 su_delay_timeout_sched; 4261 /** delay if txtime is less than 500us */ 4262 A_UINT32 su_min_txtime_sched_delay; 4263 /** scheduled via no delay */ 4264 A_UINT32 su_no_delay; 4265 /** Num of supercycles for this TxQ */ 4266 A_UINT32 num_supercycles; 4267 /** Num of subcycles with sort for this TxQ */ 4268 A_UINT32 num_subcycles_with_sort; 4269 /** Num of subcycles without sort for this Txq */ 4270 A_UINT32 num_subcycles_no_sort; 4271 } htt_stats_tx_pdev_scheduler_txq_stats_tlv; 4272 /* preserve old name alias for new name consistent with the tag name */ 4273 typedef htt_stats_tx_pdev_scheduler_txq_stats_tlv 4274 htt_tx_pdev_stats_sched_per_txq_tlv; 4275 4276 #define HTT_STATS_TX_SCHED_CMN_MAC_ID_M 0x000000ff 4277 #define HTT_STATS_TX_SCHED_CMN_MAC_ID_S 0 4278 4279 #define HTT_STATS_TX_SCHED_CMN_MAC_ID_GET(_var) \ 4280 (((_var) & HTT_STATS_TX_SCHED_CMN_MAC_ID_M) >> \ 4281 HTT_STATS_TX_SCHED_CMN_MAC_ID_S) 4282 4283 #define HTT_STATS_TX_SCHED_CMN_MAC_ID_SET(_var, _val) \ 4284 do { \ 4285 HTT_CHECK_SET_VAL(HTT_STATS_TX_SCHED_CMN_MAC_ID, _val); \ 4286 ((_var) |= ((_val) << HTT_STATS_TX_SCHED_CMN_MAC_ID_S)); \ 4287 } while (0) 4288 4289 typedef struct { 4290 htt_tlv_hdr_t tlv_hdr; 4291 4292 /** 4293 * BIT [ 7 : 0] :- mac_id 4294 * BIT [31 : 8] :- reserved 4295 */ 4296 A_UINT32 mac_id__word; 4297 /** Current timestamp */ 4298 A_UINT32 current_timestamp; 4299 } htt_stats_tx_sched_cmn_tlv; 4300 4301 /* STATS_TYPE : HTT_DBG_EXT_STATS_PDEV_TX_SCHED 4302 * TLV_TAGS: 4303 * - HTT_STATS_TX_SCHED_CMN_TAG 4304 * - HTT_STATS_TX_PDEV_SCHEDULER_TXQ_STATS_TAG 4305 * - HTT_STATS_SCHED_TXQ_CMD_POSTED_TAG 4306 * - HTT_STATS_SCHED_TXQ_CMD_REAPED_TAG 4307 * - HTT_STATS_SCHED_TXQ_SCHED_ORDER_SU_TAG 4308 * - HTT_STATS_SCHED_TXQ_SCHED_INELIGIBILITY_TAG 4309 * - HTT_STATS_SCHED_TXQ_SUPERCYCLE_TRIGGER_TAG 4310 */ 4311 /* NOTE: 4312 * This structure is for documentation, and cannot be safely used directly. 4313 * Instead, use the constituent TLV structures to fill/parse. 4314 */ 4315 typedef struct { 4316 htt_stats_tx_sched_cmn_tlv cmn_tlv; 4317 struct { 4318 htt_stats_tx_pdev_scheduler_txq_stats_tlv txq_tlv; 4319 htt_stats_sched_txq_cmd_posted_tlv cmd_posted_tlv; 4320 htt_stats_sched_txq_cmd_reaped_tlv cmd_reaped_tlv; 4321 htt_stats_sched_txq_sched_order_su_tlv sched_order_su_tlv; 4322 htt_stats_sched_txq_sched_ineligibility_tlv sched_ineligibility_tlv; 4323 htt_stats_sched_txq_supercycle_trigger_tlv htt_sched_txq_sched_ineligibility_tlv_esched_supercycle_trigger_tlv; 4324 } txq[1]; 4325 } htt_stats_tx_sched_t; 4326 4327 /* == TQM STATS == */ 4328 4329 #define HTT_TX_TQM_MAX_GEN_MPDU_END_REASON 17 4330 #define HTT_TX_TQM_MAX_LIST_MPDU_END_REASON 16 4331 #define HTT_TX_TQM_MAX_LIST_MPDU_CNT_HISTOGRAM_BINS 16 4332 4333 #define HTT_TX_TQM_GEN_MPDU_STATS_TLV_SZ(_num_elems) (sizeof(A_UINT32) * (_num_elems)) 4334 4335 /* NOTE: Variable length TLV, use length spec to infer array size */ 4336 typedef struct { 4337 htt_tlv_hdr_t tlv_hdr; 4338 4339 /* HTT_TX_TQM_MAX_GEN_MPDU_END_REASON */ 4340 HTT_STATS_VAR_LEN_ARRAY1(A_UINT32, gen_mpdu_end_reason); 4341 } htt_stats_tx_tqm_gen_mpdu_tlv; 4342 /* preserve old name alias for new name consistent with the tag name */ 4343 typedef htt_stats_tx_tqm_gen_mpdu_tlv htt_tx_tqm_gen_mpdu_stats_tlv_v; 4344 4345 #define HTT_TX_TQM_LIST_MPDU_STATS_TLV_SZ(_num_elems) (sizeof(A_UINT32) * (_num_elems)) 4346 4347 /* NOTE: Variable length TLV, use length spec to infer array size */ 4348 typedef struct { 4349 htt_tlv_hdr_t tlv_hdr; 4350 4351 /* HTT_TX_TQM_MAX_LIST_MPDU_END_REASON */ 4352 HTT_STATS_VAR_LEN_ARRAY1(A_UINT32, list_mpdu_end_reason); 4353 } htt_stats_tx_tqm_list_mpdu_tlv; 4354 /* preserve old name alias for new name consistent with the tag name */ 4355 typedef htt_stats_tx_tqm_list_mpdu_tlv htt_tx_tqm_list_mpdu_stats_tlv_v; 4356 4357 #define HTT_TX_TQM_LIST_MPDU_CNT_TLV_SZ(_num_elems) (sizeof(A_UINT32) * (_num_elems)) 4358 4359 /* NOTE: Variable length TLV, use length spec to infer array size */ 4360 typedef struct { 4361 htt_tlv_hdr_t tlv_hdr; 4362 4363 /* HTT_TX_TQM_MAX_LIST_MPDU_CNT_HISTOGRAM_BINS */ 4364 HTT_STATS_VAR_LEN_ARRAY1(A_UINT32, list_mpdu_cnt_hist); 4365 } htt_stats_tx_tqm_list_mpdu_cnt_tlv; 4366 /* preserve old name alias for new name consistent with the tag name */ 4367 typedef htt_stats_tx_tqm_list_mpdu_cnt_tlv htt_tx_tqm_list_mpdu_cnt_tlv_v; 4368 4369 typedef struct { 4370 htt_tlv_hdr_t tlv_hdr; 4371 A_UINT32 msdu_count; 4372 A_UINT32 mpdu_count; 4373 A_UINT32 remove_msdu; 4374 A_UINT32 remove_mpdu; 4375 A_UINT32 remove_msdu_ttl; 4376 A_UINT32 send_bar; 4377 A_UINT32 bar_sync; 4378 A_UINT32 notify_mpdu; 4379 A_UINT32 sync_cmd; 4380 A_UINT32 write_cmd; 4381 A_UINT32 hwsch_trigger; 4382 A_UINT32 ack_tlv_proc; 4383 A_UINT32 gen_mpdu_cmd; 4384 A_UINT32 gen_list_cmd; 4385 A_UINT32 remove_mpdu_cmd; 4386 A_UINT32 remove_mpdu_tried_cmd; 4387 A_UINT32 mpdu_queue_stats_cmd; 4388 A_UINT32 mpdu_head_info_cmd; 4389 A_UINT32 msdu_flow_stats_cmd; 4390 A_UINT32 remove_msdu_cmd; 4391 A_UINT32 remove_msdu_ttl_cmd; 4392 A_UINT32 flush_cache_cmd; 4393 A_UINT32 update_mpduq_cmd; 4394 A_UINT32 enqueue; 4395 A_UINT32 enqueue_notify; 4396 A_UINT32 notify_mpdu_at_head; 4397 A_UINT32 notify_mpdu_state_valid; 4398 /* 4399 * On receiving TQM_FLOW_NOT_EMPTY_STATUS from TQM, (on MSDUs being enqueued 4400 * the flow is non empty), if the number of MSDUs is greater than the threshold, 4401 * notify is incremented. UDP_THRESH counters are for UDP MSDUs, and NONUDP are 4402 * for non-UDP MSDUs. 4403 * MSDUQ_SWNOTIFY_UDP_THRESH1 threshold - sched_udp_notify1 is incremented 4404 * MSDUQ_SWNOTIFY_UDP_THRESH2 threshold - sched_udp_notify2 is incremented 4405 * MSDUQ_SWNOTIFY_NONUDP_THRESH1 threshold - sched_nonudp_notify1 is incremented 4406 * MSDUQ_SWNOTIFY_NONUDP_THRESH2 threshold - sched_nonudp_notify2 is incremented 4407 * 4408 * Notify signifies that we trigger the scheduler. 4409 */ 4410 A_UINT32 sched_udp_notify1; 4411 A_UINT32 sched_udp_notify2; 4412 A_UINT32 sched_nonudp_notify1; 4413 A_UINT32 sched_nonudp_notify2; 4414 A_UINT32 tqm_enqueue_msdu_count; 4415 A_UINT32 tqm_dropped_msdu_count; 4416 A_UINT32 tqm_dequeue_msdu_count; 4417 } htt_stats_tx_tqm_pdev_tlv; 4418 /* preserve old name alias for new name consistent with the tag name */ 4419 typedef htt_stats_tx_tqm_pdev_tlv htt_tx_tqm_pdev_stats_tlv_v; 4420 4421 #define HTT_TX_TQM_CMN_STATS_MAC_ID_M 0x000000ff 4422 #define HTT_TX_TQM_CMN_STATS_MAC_ID_S 0 4423 4424 #define HTT_TX_TQM_CMN_STATS_MAC_ID_GET(_var) \ 4425 (((_var) & HTT_TX_TQM_CMN_STATS_MAC_ID_M) >> \ 4426 HTT_TX_TQM_CMN_STATS_MAC_ID_S) 4427 4428 #define HTT_TX_TQM_CMN_STATS_MAC_ID_SET(_var, _val) \ 4429 do { \ 4430 HTT_CHECK_SET_VAL(HTT_TX_TQM_CMN_STATS_MAC_ID, _val); \ 4431 ((_var) |= ((_val) << HTT_TX_TQM_CMN_STATS_MAC_ID_S)); \ 4432 } while (0) 4433 4434 typedef struct { 4435 htt_tlv_hdr_t tlv_hdr; 4436 4437 /** 4438 * BIT [ 7 : 0] :- mac_id 4439 * BIT [31 : 8] :- reserved 4440 */ 4441 A_UINT32 mac_id__word; 4442 A_UINT32 max_cmdq_id; 4443 A_UINT32 list_mpdu_cnt_hist_intvl; 4444 4445 /* Global stats */ 4446 A_UINT32 add_msdu; 4447 A_UINT32 q_empty; 4448 A_UINT32 q_not_empty; 4449 A_UINT32 drop_notification; 4450 A_UINT32 desc_threshold; 4451 A_UINT32 hwsch_tqm_invalid_status; 4452 A_UINT32 missed_tqm_gen_mpdus; 4453 A_UINT32 tqm_active_tids; 4454 A_UINT32 tqm_inactive_tids; 4455 A_UINT32 tqm_active_msduq_flows; 4456 4457 /* SAWF system delay reference timestamp updation related stats */ 4458 A_UINT32 total_msduq_timestamp_updates; 4459 A_UINT32 total_msduq_timestamp_updates_by_get_mpdu_head_info_cmd; 4460 A_UINT32 total_msduq_timestamp_updates_by_empty_to_nonempty_status; 4461 A_UINT32 total_get_mpdu_head_info_cmds_by_sched_algo_la_query; 4462 A_UINT32 total_get_mpdu_head_info_cmds_by_tac; 4463 A_UINT32 total_gen_mpdu_cmds_by_sched_algo_la_query; 4464 A_UINT32 high_prio_q_not_empty; 4465 } htt_stats_tx_tqm_cmn_tlv; 4466 /* preserve old name alias for new name consistent with the tag name */ 4467 typedef htt_stats_tx_tqm_cmn_tlv htt_tx_tqm_cmn_stats_tlv; 4468 4469 typedef struct { 4470 htt_tlv_hdr_t tlv_hdr; 4471 /* Error stats */ 4472 A_UINT32 q_empty_failure; 4473 A_UINT32 q_not_empty_failure; 4474 A_UINT32 add_msdu_failure; 4475 4476 /* TQM reset debug stats */ 4477 A_UINT32 tqm_cache_ctl_err; 4478 A_UINT32 tqm_soft_reset; 4479 A_UINT32 tqm_reset_total_num_in_use_link_descs; 4480 A_UINT32 tqm_reset_worst_case_num_lost_link_descs; 4481 A_UINT32 tqm_reset_worst_case_num_lost_host_tx_bufs_count; 4482 A_UINT32 tqm_reset_num_in_use_link_descs_internal_tqm; 4483 A_UINT32 tqm_reset_num_in_use_link_descs_wbm_idle_link_ring; 4484 A_UINT32 tqm_reset_time_to_tqm_hang_delta_ms; 4485 A_UINT32 tqm_reset_recovery_time_ms; 4486 A_UINT32 tqm_reset_num_peers_hdl; 4487 A_UINT32 tqm_reset_cumm_dirty_hw_mpduq_proc_cnt; 4488 A_UINT32 tqm_reset_cumm_dirty_hw_msduq_proc; 4489 A_UINT32 tqm_reset_flush_cache_cmd_su_cnt; 4490 A_UINT32 tqm_reset_flush_cache_cmd_other_cnt; 4491 A_UINT32 tqm_reset_flush_cache_cmd_trig_type; 4492 A_UINT32 tqm_reset_flush_cache_cmd_trig_cfg; 4493 A_UINT32 tqm_reset_flush_cache_cmd_skip_cmd_status_null; 4494 } htt_stats_tx_tqm_error_stats_tlv; 4495 /* preserve old name alias for new name consistent with the tag name */ 4496 typedef htt_stats_tx_tqm_error_stats_tlv htt_tx_tqm_error_stats_tlv; 4497 4498 /* STATS_TYPE : HTT_DBG_EXT_STATS_PDEV_TQM 4499 * TLV_TAGS: 4500 * - HTT_STATS_TX_TQM_CMN_TAG 4501 * - HTT_STATS_TX_TQM_ERROR_STATS_TAG 4502 * - HTT_STATS_TX_TQM_GEN_MPDU_TAG 4503 * - HTT_STATS_TX_TQM_LIST_MPDU_TAG 4504 * - HTT_STATS_TX_TQM_LIST_MPDU_CNT_TAG 4505 * - HTT_STATS_TX_TQM_PDEV_TAG 4506 */ 4507 /* NOTE: 4508 * This structure is for documentation, and cannot be safely used directly. 4509 * Instead, use the constituent TLV structures to fill/parse. 4510 */ 4511 #ifdef ATH_TARGET 4512 typedef struct { 4513 htt_stats_tx_tqm_cmn_tlv cmn_tlv; 4514 htt_stats_tx_tqm_error_stats_tlv err_tlv; 4515 htt_stats_tx_tqm_gen_mpdu_tlv gen_mpdu_stats_tlv; 4516 htt_stats_tx_tqm_list_mpdu_tlv list_mpdu_stats_tlv; 4517 htt_stats_tx_tqm_list_mpdu_cnt_tlv list_mpdu_cnt_tlv; 4518 htt_stats_tx_tqm_pdev_tlv tqm_pdev_stats_tlv; 4519 } htt_tx_tqm_pdev_stats_t; 4520 #endif /* ATH_TARGET */ 4521 4522 /* == TQM CMDQ stats == */ 4523 #define HTT_TX_TQM_CMDQ_STATUS_MAC_ID_M 0x000000ff 4524 #define HTT_TX_TQM_CMDQ_STATUS_MAC_ID_S 0 4525 4526 #define HTT_TX_TQM_CMDQ_STATUS_CMDQ_ID_M 0x0000ff00 4527 #define HTT_TX_TQM_CMDQ_STATUS_CMDQ_ID_S 8 4528 4529 #define HTT_TX_TQM_CMDQ_STATUS_MAC_ID_GET(_var) \ 4530 (((_var) & HTT_TX_TQM_CMDQ_STATUS_MAC_ID_M) >> \ 4531 HTT_TX_TQM_CMDQ_STATUS_MAC_ID_S) 4532 4533 #define HTT_TX_TQM_CMDQ_STATUS_MAC_ID_SET(_var, _val) \ 4534 do { \ 4535 HTT_CHECK_SET_VAL(HTT_TX_TQM_CMDQ_STATUS_MAC_ID, _val); \ 4536 ((_var) |= ((_val) << HTT_TX_TQM_CMDQ_STATUS_MAC_ID_S)); \ 4537 } while (0) 4538 4539 #define HTT_TX_TQM_CMDQ_STATUS_CMDQ_ID_GET(_var) \ 4540 (((_var) & HTT_TX_TQM_CMDQ_STATUS_CMDQ_ID_M) >> \ 4541 HTT_TX_TQM_CMDQ_STATUS_CMDQ_ID_S) 4542 4543 #define HTT_TX_TQM_CMDQ_STATUS_CMDQ_ID_SET(_var, _val) \ 4544 do { \ 4545 HTT_CHECK_SET_VAL(HTT_TX_TQM_CMDQ_STATUS_CMDQ_ID, _val); \ 4546 ((_var) |= ((_val) << HTT_TX_TQM_CMDQ_STATUS_CMDQ_ID_S)); \ 4547 } while (0) 4548 4549 typedef struct { 4550 htt_tlv_hdr_t tlv_hdr; 4551 4552 /* 4553 * BIT [ 7 : 0] :- mac_id 4554 * BIT [15 : 8] :- cmdq_id 4555 * BIT [31 : 16] :- reserved 4556 */ 4557 A_UINT32 mac_id__cmdq_id__word; 4558 A_UINT32 sync_cmd; 4559 A_UINT32 write_cmd; 4560 A_UINT32 gen_mpdu_cmd; 4561 A_UINT32 mpdu_queue_stats_cmd; 4562 A_UINT32 mpdu_head_info_cmd; 4563 A_UINT32 msdu_flow_stats_cmd; 4564 A_UINT32 remove_mpdu_cmd; 4565 A_UINT32 remove_msdu_cmd; 4566 A_UINT32 flush_cache_cmd; 4567 A_UINT32 update_mpduq_cmd; 4568 A_UINT32 update_msduq_cmd; 4569 } htt_stats_tx_tqm_cmdq_status_tlv; 4570 /* preserve old name alias for new name consistent with the tag name */ 4571 typedef htt_stats_tx_tqm_cmdq_status_tlv htt_tx_tqm_cmdq_status_tlv; 4572 4573 /* STATS_TYPE : HTT_DBG_EXT_STATS_TQM_CMDQ 4574 * TLV_TAGS: 4575 * - HTT_STATS_STRING_TAG 4576 * - HTT_STATS_TX_TQM_CMDQ_STATUS_TAG 4577 */ 4578 /* NOTE: 4579 * This structure is for documentation, and cannot be safely used directly. 4580 * Instead, use the constituent TLV structures to fill/parse. 4581 */ 4582 #ifdef ATH_TARGET 4583 typedef struct { 4584 struct { 4585 htt_stats_string_tlv cmdq_str_tlv; 4586 htt_stats_tx_tqm_cmdq_status_tlv status_tlv; 4587 } q[1]; 4588 } htt_tx_tqm_cmdq_stats_t; 4589 #endif /* ATH_TARGET */ 4590 4591 /* == TX-DE STATS == */ 4592 4593 /* Structures for tx de stats */ 4594 typedef struct { 4595 htt_tlv_hdr_t tlv_hdr; 4596 A_UINT32 m1_packets; 4597 A_UINT32 m2_packets; 4598 A_UINT32 m3_packets; 4599 A_UINT32 m4_packets; 4600 A_UINT32 g1_packets; 4601 A_UINT32 g2_packets; 4602 A_UINT32 rc4_packets; 4603 A_UINT32 eap_packets; 4604 A_UINT32 eapol_start_packets; 4605 A_UINT32 eapol_logoff_packets; 4606 A_UINT32 eapol_encap_asf_packets; 4607 A_UINT32 m1_success; 4608 A_UINT32 m1_compl_fail; 4609 A_UINT32 m2_success; 4610 A_UINT32 m2_compl_fail; 4611 A_UINT32 m3_success; 4612 A_UINT32 m3_compl_fail; 4613 A_UINT32 m4_success; 4614 A_UINT32 m4_compl_fail; 4615 A_UINT32 g1_success; 4616 A_UINT32 g1_compl_fail; 4617 A_UINT32 g2_success; 4618 A_UINT32 g2_compl_fail; 4619 } htt_stats_tx_de_eapol_packets_tlv; 4620 /* preserve old name alias for new name consistent with the tag name */ 4621 typedef htt_stats_tx_de_eapol_packets_tlv htt_tx_de_eapol_packets_stats_tlv; 4622 4623 typedef struct { 4624 htt_tlv_hdr_t tlv_hdr; 4625 A_UINT32 ap_bss_peer_not_found; 4626 A_UINT32 ap_bcast_mcast_no_peer; 4627 A_UINT32 sta_delete_in_progress; 4628 A_UINT32 ibss_no_bss_peer; 4629 A_UINT32 invaild_vdev_type; 4630 A_UINT32 invalid_ast_peer_entry; 4631 A_UINT32 peer_entry_invalid; 4632 A_UINT32 ethertype_not_ip; 4633 A_UINT32 eapol_lookup_failed; 4634 A_UINT32 qpeer_not_allow_data; 4635 A_UINT32 fse_tid_override; 4636 A_UINT32 ipv6_jumbogram_zero_length; 4637 A_UINT32 qos_to_non_qos_in_prog; 4638 A_UINT32 ap_bcast_mcast_eapol; 4639 A_UINT32 unicast_on_ap_bss_peer; 4640 A_UINT32 ap_vdev_invalid; 4641 A_UINT32 incomplete_llc; 4642 A_UINT32 eapol_duplicate_m3; 4643 A_UINT32 eapol_duplicate_m4; 4644 } htt_stats_tx_de_classify_failed_tlv; 4645 /* preserve old name alias for new name consistent with the tag name */ 4646 typedef htt_stats_tx_de_classify_failed_tlv htt_tx_de_classify_failed_stats_tlv; 4647 4648 typedef struct { 4649 htt_tlv_hdr_t tlv_hdr; 4650 A_UINT32 arp_packets; 4651 A_UINT32 igmp_packets; 4652 A_UINT32 dhcp_packets; 4653 A_UINT32 host_inspected; 4654 A_UINT32 htt_included; 4655 A_UINT32 htt_valid_mcs; 4656 A_UINT32 htt_valid_nss; 4657 A_UINT32 htt_valid_preamble_type; 4658 A_UINT32 htt_valid_chainmask; 4659 A_UINT32 htt_valid_guard_interval; 4660 A_UINT32 htt_valid_retries; 4661 A_UINT32 htt_valid_bw_info; 4662 A_UINT32 htt_valid_power; 4663 A_UINT32 htt_valid_key_flags; 4664 A_UINT32 htt_valid_no_encryption; 4665 A_UINT32 fse_entry_count; 4666 A_UINT32 fse_priority_be; 4667 A_UINT32 fse_priority_high; 4668 A_UINT32 fse_priority_low; 4669 A_UINT32 fse_traffic_ptrn_be; 4670 A_UINT32 fse_traffic_ptrn_over_sub; 4671 A_UINT32 fse_traffic_ptrn_bursty; 4672 A_UINT32 fse_traffic_ptrn_interactive; 4673 A_UINT32 fse_traffic_ptrn_periodic; 4674 A_UINT32 fse_hwqueue_alloc; 4675 A_UINT32 fse_hwqueue_created; 4676 A_UINT32 fse_hwqueue_send_to_host; 4677 A_UINT32 mcast_entry; 4678 A_UINT32 bcast_entry; 4679 A_UINT32 htt_update_peer_cache; 4680 A_UINT32 htt_learning_frame; 4681 A_UINT32 fse_invalid_peer; 4682 /** 4683 * mec_notify is HTT TX WBM multicast echo check notification 4684 * from firmware to host. FW sends SA addresses to host for all 4685 * multicast/broadcast packets received on STA side. 4686 */ 4687 A_UINT32 mec_notify; 4688 A_UINT32 arp_response; 4689 A_UINT32 arp_request; 4690 } htt_stats_tx_de_classify_stats_tlv; 4691 /* preserve old name alias for new name consistent with the tag name */ 4692 typedef htt_stats_tx_de_classify_stats_tlv htt_tx_de_classify_stats_tlv; 4693 4694 typedef struct { 4695 htt_tlv_hdr_t tlv_hdr; 4696 A_UINT32 eok; 4697 A_UINT32 classify_done; 4698 A_UINT32 lookup_failed; 4699 A_UINT32 send_host_dhcp; 4700 A_UINT32 send_host_mcast; 4701 A_UINT32 send_host_unknown_dest; 4702 A_UINT32 send_host; 4703 A_UINT32 status_invalid; 4704 } htt_stats_tx_de_classify_status_tlv; 4705 /* preserve old name alias for new name consistent with the tag name */ 4706 typedef htt_stats_tx_de_classify_status_tlv htt_tx_de_classify_status_stats_tlv; 4707 4708 typedef struct { 4709 htt_tlv_hdr_t tlv_hdr; 4710 A_UINT32 enqueued_pkts; 4711 A_UINT32 to_tqm; 4712 A_UINT32 to_tqm_bypass; 4713 } htt_stats_tx_de_enqueue_packets_tlv; 4714 /* preserve old name alias for new name consistent with the tag name */ 4715 typedef htt_stats_tx_de_enqueue_packets_tlv htt_tx_de_enqueue_packets_stats_tlv; 4716 4717 typedef struct { 4718 htt_tlv_hdr_t tlv_hdr; 4719 A_UINT32 discarded_pkts; 4720 A_UINT32 local_frames; 4721 A_UINT32 is_ext_msdu; 4722 A_UINT32 mlo_invalid_routing_discard; 4723 A_UINT32 mlo_invalid_routing_dup_entry_discard; 4724 A_UINT32 discard_peer_unauthorized_pkts; 4725 } htt_stats_tx_de_enqueue_discard_tlv; 4726 /* preserve old name alias for new name consistent with the tag name */ 4727 typedef htt_stats_tx_de_enqueue_discard_tlv htt_tx_de_enqueue_discard_stats_tlv; 4728 4729 typedef struct { 4730 htt_tlv_hdr_t tlv_hdr; 4731 A_UINT32 tcl_dummy_frame; 4732 A_UINT32 tqm_dummy_frame; 4733 A_UINT32 tqm_notify_frame; 4734 A_UINT32 fw2wbm_enq; 4735 A_UINT32 tqm_bypass_frame; 4736 } htt_stats_tx_de_compl_stats_tlv; 4737 /* preserve old name alias for new name consistent with the tag name */ 4738 typedef htt_stats_tx_de_compl_stats_tlv htt_tx_de_compl_stats_tlv; 4739 4740 #define HTT_TX_DE_CMN_STATS_MAC_ID_M 0x000000ff 4741 #define HTT_TX_DE_CMN_STATS_MAC_ID_S 0 4742 4743 #define HTT_TX_DE_CMN_STATS_MAC_ID_GET(_var) \ 4744 (((_var) & HTT_TX_DE_CMN_STATS_MAC_ID_M) >> \ 4745 HTT_TX_DE_CMN_STATS_MAC_ID_S) 4746 4747 #define HTT_TX_DE_CMN_STATS_MAC_ID_SET(_var, _val) \ 4748 do { \ 4749 HTT_CHECK_SET_VAL(HTT_TX_DE_CMN_STATS_MAC_ID, _val); \ 4750 ((_var) |= ((_val) << HTT_TX_DE_CMN_STATS_MAC_ID_S)); \ 4751 } while (0) 4752 4753 /* 4754 * The htt_tx_de_fw2wbm_ring_full_hist_tlv is a histogram of time we waited 4755 * for the fw2wbm ring buffer. we are requesting a buffer in FW2WBM release 4756 * ring,which may fail, due to non availability of buffer. Hence we sleep for 4757 * 200us & again request for it. This is a histogram of time we wait, with 4758 * bin of 200ms & there are 10 bin (2 seconds max) 4759 * They are defined by the following macros in FW 4760 * #define ENTRIES_PER_BIN_COUNT 1000 // per bin 1000 * 200us = 200ms 4761 * #define RING_FULL_BIN_ENTRIES (WAL_TX_DE_FW2WBM_ALLOC_TIMEOUT_COUNT / 4762 * ENTRIES_PER_BIN_COUNT) 4763 */ 4764 typedef struct { 4765 htt_tlv_hdr_t tlv_hdr; 4766 4767 HTT_STATS_VAR_LEN_ARRAY1(A_UINT32, fw2wbm_ring_full_hist); 4768 } htt_stats_tx_de_fw2wbm_ring_full_hist_tlv; 4769 /* preserve old name alias for new name consistent with the tag name */ 4770 typedef htt_stats_tx_de_fw2wbm_ring_full_hist_tlv 4771 htt_tx_de_fw2wbm_ring_full_hist_tlv; 4772 4773 typedef struct { 4774 htt_tlv_hdr_t tlv_hdr; 4775 /** 4776 * BIT [ 7 : 0] :- mac_id 4777 * BIT [31 : 8] :- reserved 4778 */ 4779 A_UINT32 mac_id__word; 4780 4781 /* Global Stats */ 4782 A_UINT32 tcl2fw_entry_count; 4783 A_UINT32 not_to_fw; 4784 A_UINT32 invalid_pdev_vdev_peer; 4785 A_UINT32 tcl_res_invalid_addrx; 4786 A_UINT32 wbm2fw_entry_count; 4787 A_UINT32 invalid_pdev; 4788 A_UINT32 tcl_res_addrx_timeout; 4789 A_UINT32 invalid_vdev; 4790 A_UINT32 invalid_tcl_exp_frame_desc; 4791 A_UINT32 vdev_id_mismatch_cnt; 4792 } htt_stats_tx_de_cmn_tlv; 4793 /* preserve old name alias for new name consistent with the tag name */ 4794 typedef htt_stats_tx_de_cmn_tlv htt_tx_de_cmn_stats_tlv; 4795 4796 #define HTT_STATS_RX_FW_RING_SIZE_NUM_ENTRIES(dword) ((dword >> 0) & 0xffff) 4797 #define HTT_STATS_RX_FW_RING_CURR_NUM_ENTRIES(dword) ((dword >> 16) & 0xffff) 4798 4799 /* Rx debug info for status rings */ 4800 typedef struct { 4801 htt_tlv_hdr_t tlv_hdr; 4802 /** 4803 * BIT [15 : 0] :- max possible number of entries in respective ring 4804 * (size of the ring in terms of entries) 4805 * BIT [16 : 31] :- current number of entries occupied in respective ring 4806 */ 4807 A_UINT32 entry_status_sw2rxdma; 4808 A_UINT32 entry_status_rxdma2reo; 4809 A_UINT32 entry_status_reo2sw1; 4810 A_UINT32 entry_status_reo2sw4; 4811 A_UINT32 entry_status_refillringipa; 4812 A_UINT32 entry_status_refillringhost; 4813 /** datarate - Moving Average of Number of Entries */ 4814 A_UINT32 datarate_refillringipa; 4815 A_UINT32 datarate_refillringhost; 4816 /** 4817 * refillringhost_backpress_hist and refillringipa_backpress_hist are 4818 * deprecated, and will be filled with 0x0 by the target. 4819 */ 4820 A_UINT32 refillringhost_backpress_hist[3]; 4821 A_UINT32 refillringipa_backpress_hist[3]; 4822 /** 4823 * Number of times reo2sw4(IPA_DEST_RING) ring is back-pressured 4824 * in recent time periods 4825 * element 0: in last 0 to 250ms 4826 * element 1: 250ms to 500ms 4827 * element 2: above 500ms 4828 */ 4829 A_UINT32 reo2sw4ringipa_backpress_hist[3]; 4830 } htt_stats_rx_ring_stats_tlv; 4831 /* preserve old name alias for new name consistent with the tag name */ 4832 typedef htt_stats_rx_ring_stats_tlv htt_rx_fw_ring_stats_tlv_v; 4833 4834 /* STATS_TYPE : HTT_DBG_EXT_STATS_TX_DE_INFO 4835 * TLV_TAGS: 4836 * - HTT_STATS_TX_DE_CMN_TAG 4837 * - HTT_STATS_TX_DE_FW2WBM_RING_FULL_HIST_TAG 4838 * - HTT_STATS_TX_DE_EAPOL_PACKETS_TAG 4839 * - HTT_STATS_TX_DE_CLASSIFY_STATS_TAG 4840 * - HTT_STATS_TX_DE_CLASSIFY_FAILED_TAG 4841 * - HTT_STATS_TX_DE_CLASSIFY_STATUS_TAG 4842 * - HTT_STATS_TX_DE_ENQUEUE_PACKETS_TAG 4843 * - HTT_STATS_TX_DE_ENQUEUE_DISCARD_TAG 4844 * - HTT_STATS_TX_DE_COMPL_STATS_TAG 4845 */ 4846 /* NOTE: 4847 * This structure is for documentation, and cannot be safely used directly. 4848 * Instead, use the constituent TLV structures to fill/parse. 4849 */ 4850 #ifdef ATH_TARGET 4851 typedef struct { 4852 htt_stats_tx_de_cmn_tlv cmn_tlv; 4853 htt_stats_tx_de_fw2wbm_ring_full_hist_tlv fw2wbm_hist_tlv; 4854 htt_stats_tx_de_eapol_packets_tlv eapol_stats_tlv; 4855 htt_stats_tx_de_classify_stats_tlv classify_stats_tlv; 4856 htt_stats_tx_de_classify_failed_tlv classify_failed_tlv; 4857 htt_stats_tx_de_classify_status_tlv classify_status_rlv; 4858 htt_stats_tx_de_enqueue_packets_tlv enqueue_packets_tlv; 4859 htt_stats_tx_de_enqueue_discard_tlv enqueue_discard_tlv; 4860 htt_stats_tx_de_compl_stats_tlv comp_status_tlv; 4861 } htt_tx_de_stats_t; 4862 #endif /* ATH_TARGET */ 4863 4864 /* == RING-IF STATS == */ 4865 /* DWORD num_elems__prefetch_tail_idx */ 4866 #define HTT_RING_IF_STATS_NUM_ELEMS_M 0x0000ffff 4867 #define HTT_RING_IF_STATS_NUM_ELEMS_S 0 4868 4869 #define HTT_RING_IF_STATS_PREFETCH_TAIL_IDX_M 0xffff0000 4870 #define HTT_RING_IF_STATS_PREFETCH_TAIL_IDX_S 16 4871 4872 #define HTT_RING_IF_STATS_NUM_ELEMS_GET(_var) \ 4873 (((_var) & HTT_RING_IF_STATS_NUM_ELEMS_M) >> \ 4874 HTT_RING_IF_STATS_NUM_ELEMS_S) 4875 4876 #define HTT_RING_IF_STATS_NUM_ELEMS_SET(_var, _val) \ 4877 do { \ 4878 HTT_CHECK_SET_VAL(HTT_RING_IF_STATS_NUM_ELEMS, _val); \ 4879 ((_var) |= ((_val) << HTT_RING_IF_STATS_NUM_ELEMS_S)); \ 4880 } while (0) 4881 4882 #define HTT_RING_IF_STATS_PREFETCH_TAIL_IDX_GET(_var) \ 4883 (((_var) & HTT_RING_IF_STATS_PREFETCH_TAIL_IDX_M) >> \ 4884 HTT_RING_IF_STATS_PREFETCH_TAIL_IDX_S) 4885 4886 #define HTT_RING_IF_STATS_PREFETCH_TAIL_IDX_SET(_var, _val) \ 4887 do { \ 4888 HTT_CHECK_SET_VAL(HTT_RING_IF_STATS_PREFETCH_TAIL_IDX, _val); \ 4889 ((_var) |= ((_val) << HTT_RING_IF_STATS_PREFETCH_TAIL_IDX_S)); \ 4890 } while (0) 4891 4892 /* DWORD head_idx__tail_idx */ 4893 #define HTT_RING_IF_STATS_HEAD_IDX_M 0x0000ffff 4894 #define HTT_RING_IF_STATS_HEAD_IDX_S 0 4895 4896 #define HTT_RING_IF_STATS_TAIL_IDX_M 0xffff0000 4897 #define HTT_RING_IF_STATS_TAIL_IDX_S 16 4898 4899 #define HTT_RING_IF_STATS_HEAD_IDX_GET(_var) \ 4900 (((_var) & HTT_RING_IF_STATS_HEAD_IDX_M) >> \ 4901 HTT_RING_IF_STATS_HEAD_IDX_S) 4902 4903 #define HTT_RING_IF_STATS_HEAD_IDX_SET(_var, _val) \ 4904 do { \ 4905 HTT_CHECK_SET_VAL(HTT_RING_IF_STATS_HEAD_IDX, _val); \ 4906 ((_var) |= ((_val) << HTT_RING_IF_STATS_HEAD_IDX_S)); \ 4907 } while (0) 4908 4909 #define HTT_RING_IF_STATS_TAIL_IDX_GET(_var) \ 4910 (((_var) & HTT_RING_IF_STATS_TAIL_IDX_M) >> \ 4911 HTT_RING_IF_STATS_TAIL_IDX_S) 4912 4913 #define HTT_RING_IF_STATS_TAIL_IDX_SET(_var, _val) \ 4914 do { \ 4915 HTT_CHECK_SET_VAL(HTT_RING_IF_STATS_TAIL_IDX, _val); \ 4916 ((_var) |= ((_val) << HTT_RING_IF_STATS_TAIL_IDX_S)); \ 4917 } while (0) 4918 4919 /* DWORD shadow_head_idx__shadow_tail_idx */ 4920 #define HTT_RING_IF_STATS_SHADOW_HEAD_IDX_M 0x0000ffff 4921 #define HTT_RING_IF_STATS_SHADOW_HEAD_IDX_S 0 4922 4923 #define HTT_RING_IF_STATS_SHADOW_TAIL_IDX_M 0xffff0000 4924 #define HTT_RING_IF_STATS_SHADOW_TAIL_IDX_S 16 4925 4926 #define HTT_RING_IF_STATS_SHADOW_HEAD_IDX_GET(_var) \ 4927 (((_var) & HTT_RING_IF_STATS_SHADOW_HEAD_IDX_M) >> \ 4928 HTT_RING_IF_STATS_SHADOW_HEAD_IDX_S) 4929 4930 #define HTT_RING_IF_STATS_SHADOW_HEAD_IDX_SET(_var, _val) \ 4931 do { \ 4932 HTT_CHECK_SET_VAL(HTT_RING_IF_STATS_SHADOW_HEAD_IDX, _val); \ 4933 ((_var) |= ((_val) << HTT_RING_IF_STATS_SHADOW_HEAD_IDX_S)); \ 4934 } while (0) 4935 4936 #define HTT_RING_IF_STATS_SHADOW_TAIL_IDX_GET(_var) \ 4937 (((_var) & HTT_RING_IF_STATS_SHADOW_TAIL_IDX_M) >> \ 4938 HTT_RING_IF_STATS_SHADOW_TAIL_IDX_S) 4939 4940 #define HTT_RING_IF_STATS_SHADOW_TAIL_IDX_SET(_var, _val) \ 4941 do { \ 4942 HTT_CHECK_SET_VAL(HTT_RING_IF_STATS_SHADOW_TAIL_IDX, _val); \ 4943 ((_var) |= ((_val) << HTT_RING_IF_STATS_SHADOW_TAIL_IDX_S)); \ 4944 } while (0) 4945 4946 /* DWORD lwm_thresh__hwm_thresh */ 4947 #define HTT_RING_IF_STATS_LWM_THRESHOLD_M 0x0000ffff 4948 #define HTT_RING_IF_STATS_LWM_THRESHOLD_S 0 4949 4950 #define HTT_RING_IF_STATS_HWM_THRESHOLD_M 0xffff0000 4951 #define HTT_RING_IF_STATS_HWM_THRESHOLD_S 16 4952 4953 #define HTT_RING_IF_STATS_LWM_THRESHOLD_GET(_var) \ 4954 (((_var) & HTT_RING_IF_STATS_LWM_THRESHOLD_M) >> \ 4955 HTT_RING_IF_STATS_LWM_THRESHOLD_S) 4956 4957 #define HTT_RING_IF_STATS_LWM_THRESHOLD_SET(_var, _val) \ 4958 do { \ 4959 HTT_CHECK_SET_VAL(HTT_RING_IF_STATS_LWM_THRESHOLD, _val); \ 4960 ((_var) |= ((_val) << HTT_RING_IF_STATS_LWM_THRESHOLD_S)); \ 4961 } while (0) 4962 4963 #define HTT_RING_IF_STATS_HWM_THRESHOLD_GET(_var) \ 4964 (((_var) & HTT_RING_IF_STATS_HWM_THRESHOLD_M) >> \ 4965 HTT_RING_IF_STATS_HWM_THRESHOLD_S) 4966 4967 #define HTT_RING_IF_STATS_HWM_THRESHOLD_SET(_var, _val) \ 4968 do { \ 4969 HTT_CHECK_SET_VAL(HTT_RING_IF_STATS_HWM_THRESHOLD, _val); \ 4970 ((_var) |= ((_val) << HTT_RING_IF_STATS_HWM_THRESHOLD_S)); \ 4971 } while (0) 4972 4973 #define HTT_STATS_LOW_WM_BINS 5 4974 #define HTT_STATS_HIGH_WM_BINS 5 4975 4976 typedef struct { 4977 /** DWORD aligned base memory address of the ring */ 4978 A_UINT32 base_addr; 4979 4980 /** size of each ring element */ 4981 A_UINT32 elem_size; 4982 4983 /** 4984 * BIT [15 : 0] :- num_elems 4985 * BIT [31 : 16] :- prefetch_tail_idx 4986 */ 4987 A_UINT32 num_elems__prefetch_tail_idx; 4988 /** 4989 * BIT [15 : 0] :- head_idx 4990 * BIT [31 : 16] :- tail_idx 4991 */ 4992 A_UINT32 head_idx__tail_idx; 4993 /** 4994 * BIT [15 : 0] :- shadow_head_idx 4995 * BIT [31 : 16] :- shadow_tail_idx 4996 */ 4997 A_UINT32 shadow_head_idx__shadow_tail_idx; 4998 A_UINT32 num_tail_incr; 4999 /** 5000 * BIT [15 : 0] :- lwm_thresh 5001 * BIT [31 : 16] :- hwm_thresh 5002 */ 5003 A_UINT32 lwm_thresh__hwm_thresh; 5004 A_UINT32 overrun_hit_count; 5005 A_UINT32 underrun_hit_count; 5006 A_UINT32 prod_blockwait_count; 5007 A_UINT32 cons_blockwait_count; 5008 A_UINT32 low_wm_hit_count[HTT_STATS_LOW_WM_BINS]; 5009 A_UINT32 high_wm_hit_count[HTT_STATS_HIGH_WM_BINS]; 5010 } htt_stats_ring_if_tlv; 5011 /* preserve old name alias for new name consistent with the tag name */ 5012 typedef htt_stats_ring_if_tlv htt_ring_if_stats_tlv; 5013 5014 #define HTT_RING_IF_CMN_MAC_ID_M 0x000000ff 5015 #define HTT_RING_IF_CMN_MAC_ID_S 0 5016 5017 #define HTT_RING_IF_CMN_MAC_ID_GET(_var) \ 5018 (((_var) & HTT_RING_IF_CMN_MAC_ID_M) >> \ 5019 HTT_RING_IF_CMN_MAC_ID_S) 5020 5021 #define HTT_RING_IF_CMN_MAC_ID_SET(_var, _val) \ 5022 do { \ 5023 HTT_CHECK_SET_VAL(HTT_RING_IF_CMN_MAC_ID, _val); \ 5024 ((_var) |= ((_val) << HTT_RING_IF_CMN_MAC_ID_S)); \ 5025 } while (0) 5026 5027 typedef struct { 5028 htt_tlv_hdr_t tlv_hdr; 5029 5030 /** 5031 * BIT [ 7 : 0] :- mac_id 5032 * BIT [31 : 8] :- reserved 5033 */ 5034 A_UINT32 mac_id__word; 5035 A_UINT32 num_records; 5036 } htt_stats_ring_if_cmn_tlv; 5037 /* preserve old name alias for new name consistent with the tag name */ 5038 typedef htt_stats_ring_if_cmn_tlv htt_ring_if_cmn_tlv; 5039 5040 /* STATS_TYPE : HTT_DBG_EXT_STATS_RING_IF_INFO 5041 * TLV_TAGS: 5042 * - HTT_STATS_RING_IF_CMN_TAG 5043 * - HTT_STATS_STRING_TAG 5044 * - HTT_STATS_RING_IF_TAG 5045 */ 5046 /* NOTE: 5047 * This structure is for documentation, and cannot be safely used directly. 5048 * Instead, use the constituent TLV structures to fill/parse. 5049 */ 5050 #ifdef ATH_TARGET 5051 typedef struct { 5052 htt_stats_ring_if_cmn_tlv cmn_tlv; 5053 /** Variable based on the Number of records. */ 5054 struct { 5055 htt_stats_string_tlv ring_str_tlv; 5056 htt_stats_ring_if_tlv ring_tlv; 5057 } r[1]; 5058 } htt_ring_if_stats_t; 5059 #endif /* ATH_TARGET */ 5060 5061 /* == SFM STATS == */ 5062 5063 #define HTT_SFM_CLIENT_USER_TLV_SZ(_num_elems) (sizeof(A_UINT32) * (_num_elems)) 5064 5065 /* NOTE: Variable length TLV, use length spec to infer array size */ 5066 typedef struct { 5067 htt_tlv_hdr_t tlv_hdr; 5068 /** Number of DWORDS used per user and per client */ 5069 HTT_STATS_VAR_LEN_ARRAY1(A_UINT32, dwords_used_by_user_n); 5070 } htt_stats_sfm_client_user_tlv; 5071 /* preserve old name alias for new name consistent with the tag name */ 5072 typedef htt_stats_sfm_client_user_tlv htt_sfm_client_user_tlv_v; 5073 5074 typedef struct { 5075 htt_tlv_hdr_t tlv_hdr; 5076 /** Client ID */ 5077 A_UINT32 client_id; 5078 /** Minimum number of buffers */ 5079 A_UINT32 buf_min; 5080 /** Maximum number of buffers */ 5081 A_UINT32 buf_max; 5082 /** Number of Busy buffers */ 5083 A_UINT32 buf_busy; 5084 /** Number of Allocated buffers */ 5085 A_UINT32 buf_alloc; 5086 /** Number of Available/Usable buffers */ 5087 A_UINT32 buf_avail; 5088 /** Number of users */ 5089 A_UINT32 num_users; 5090 } htt_stats_sfm_client_tlv; 5091 /* preserve old name alias for new name consistent with the tag name */ 5092 typedef htt_stats_sfm_client_tlv htt_sfm_client_tlv; 5093 5094 #define HTT_SFM_CMN_MAC_ID_M 0x000000ff 5095 #define HTT_SFM_CMN_MAC_ID_S 0 5096 5097 #define HTT_SFM_CMN_MAC_ID_GET(_var) \ 5098 (((_var) & HTT_SFM_CMN_MAC_ID_M) >> \ 5099 HTT_SFM_CMN_MAC_ID_S) 5100 5101 #define HTT_SFM_CMN_MAC_ID_SET(_var, _val) \ 5102 do { \ 5103 HTT_CHECK_SET_VAL(HTT_SFM_CMN_MAC_ID, _val); \ 5104 ((_var) |= ((_val) << HTT_SFM_CMN_MAC_ID_S)); \ 5105 } while (0) 5106 5107 typedef struct { 5108 htt_tlv_hdr_t tlv_hdr; 5109 5110 /** 5111 * BIT [ 7 : 0] :- mac_id 5112 * BIT [31 : 8] :- reserved 5113 */ 5114 A_UINT32 mac_id__word; 5115 /** 5116 * Indicates the total number of 128 byte buffers in the CMEM 5117 * that are available for buffer sharing 5118 */ 5119 A_UINT32 buf_total; 5120 /** 5121 * Indicates for certain client or all the clients there is no 5122 * dword saved in SFM, refer to SFM_R1_MEM_EMPTY 5123 */ 5124 A_UINT32 mem_empty; 5125 /** DEALLOCATE_BUFFERS, refer to register SFM_R0_DEALLOCATE_BUFFERS */ 5126 A_UINT32 deallocate_bufs; 5127 /** Number of Records */ 5128 A_UINT32 num_records; 5129 } htt_stats_sfm_cmn_tlv; 5130 /* preserve old name alias for new name consistent with the tag name */ 5131 typedef htt_stats_sfm_cmn_tlv htt_sfm_cmn_tlv; 5132 5133 /* STATS_TYPE : HTT_DBG_EXT_STATS_RING_IF_INFO 5134 * TLV_TAGS: 5135 * - HTT_STATS_SFM_CMN_TAG 5136 * - HTT_STATS_STRING_TAG 5137 * - HTT_STATS_SFM_CLIENT_TAG 5138 * - HTT_STATS_SFM_CLIENT_USER_TAG 5139 */ 5140 /* NOTE: 5141 * This structure is for documentation, and cannot be safely used directly. 5142 * Instead, use the constituent TLV structures to fill/parse. 5143 */ 5144 #ifdef ATH_TARGET 5145 typedef struct { 5146 htt_stats_sfm_cmn_tlv cmn_tlv; 5147 /** Variable based on the Number of records. */ 5148 struct { 5149 htt_stats_string_tlv client_str_tlv; 5150 htt_stats_sfm_client_tlv client_tlv; 5151 htt_stats_sfm_client_user_tlv user_tlv; 5152 } r[1]; 5153 } htt_sfm_stats_t; 5154 #endif /* ATH_TARGET */ 5155 5156 /* == SRNG STATS == */ 5157 /* DWORD mac_id__ring_id__arena__ep */ 5158 #define HTT_SRING_STATS_MAC_ID_M 0x000000ff 5159 #define HTT_SRING_STATS_MAC_ID_S 0 5160 5161 #define HTT_SRING_STATS_RING_ID_M 0x0000ff00 5162 #define HTT_SRING_STATS_RING_ID_S 8 5163 5164 #define HTT_SRING_STATS_ARENA_M 0x00ff0000 5165 #define HTT_SRING_STATS_ARENA_S 16 5166 5167 #define HTT_SRING_STATS_EP_TYPE_M 0x01000000 5168 #define HTT_SRING_STATS_EP_TYPE_S 24 5169 5170 #define HTT_SRING_STATS_MAC_ID_GET(_var) \ 5171 (((_var) & HTT_SRING_STATS_MAC_ID_M) >> \ 5172 HTT_SRING_STATS_MAC_ID_S) 5173 5174 #define HTT_SRING_STATS_MAC_ID_SET(_var, _val) \ 5175 do { \ 5176 HTT_CHECK_SET_VAL(HTT_SRING_STATS_MAC_ID, _val); \ 5177 ((_var) |= ((_val) << HTT_SRING_STATS_MAC_ID_S)); \ 5178 } while (0) 5179 5180 #define HTT_SRING_STATS_RING_ID_GET(_var) \ 5181 (((_var) & HTT_SRING_STATS_RING_ID_M) >> \ 5182 HTT_SRING_STATS_RING_ID_S) 5183 5184 #define HTT_SRING_STATS_RING_ID_SET(_var, _val) \ 5185 do { \ 5186 HTT_CHECK_SET_VAL(HTT_SRING_STATS_RING_ID, _val); \ 5187 ((_var) |= ((_val) << HTT_SRING_STATS_RING_ID_S)); \ 5188 } while (0) 5189 5190 #define HTT_SRING_STATS_ARENA_GET(_var) \ 5191 (((_var) & HTT_SRING_STATS_ARENA_M) >> \ 5192 HTT_SRING_STATS_ARENA_S) 5193 5194 #define HTT_SRING_STATS_ARENA_SET(_var, _val) \ 5195 do { \ 5196 HTT_CHECK_SET_VAL(HTT_SRING_STATS_ARENA, _val); \ 5197 ((_var) |= ((_val) << HTT_SRING_STATS_ARENA_S)); \ 5198 } while (0) 5199 5200 #define HTT_SRING_STATS_EP_TYPE_GET(_var) \ 5201 (((_var) & HTT_SRING_STATS_EP_TYPE_M) >> \ 5202 HTT_SRING_STATS_EP_TYPE_S) 5203 5204 #define HTT_SRING_STATS_EP_TYPE_SET(_var, _val) \ 5205 do { \ 5206 HTT_CHECK_SET_VAL(HTT_SRING_STATS_EP_TYPE, _val); \ 5207 ((_var) |= ((_val) << HTT_SRING_STATS_EP_TYPE_S)); \ 5208 } while (0) 5209 5210 /* DWORD num_avail_words__num_valid_words */ 5211 #define HTT_SRING_STATS_NUM_AVAIL_WORDS_M 0x0000ffff 5212 #define HTT_SRING_STATS_NUM_AVAIL_WORDS_S 0 5213 5214 #define HTT_SRING_STATS_NUM_VALID_WORDS_M 0xffff0000 5215 #define HTT_SRING_STATS_NUM_VALID_WORDS_S 16 5216 5217 #define HTT_SRING_STATS_NUM_AVAIL_WORDS_GET(_var) \ 5218 (((_var) & HTT_SRING_STATS_NUM_AVAIL_WORDS_M) >> \ 5219 HTT_SRING_STATS_NUM_AVAIL_WORDS_S) 5220 5221 #define HTT_SRING_STATS_NUM_AVAIL_WORDS_SET(_var, _val) \ 5222 do { \ 5223 HTT_CHECK_SET_VAL(HTT_SRING_STATS_NUM_AVAIL_WORDS, _val); \ 5224 ((_var) |= ((_val) << HTT_SRING_STATS_NUM_AVAIL_WORDS_S)); \ 5225 } while (0) 5226 5227 #define HTT_SRING_STATS_NUM_VALID_WORDS_GET(_var) \ 5228 (((_var) & HTT_SRING_STATS_NUM_VALID_WORDS_M) >> \ 5229 HTT_SRING_STATS_NUM_VALID_WORDS_S) 5230 5231 #define HTT_SRING_STATS_NUM_VALID_WORDS_SET(_var, _val) \ 5232 do { \ 5233 HTT_CHECK_SET_VAL(HTT_SRING_STATS_NUM_VALID_WORDS, _val); \ 5234 ((_var) |= ((_val) << HTT_SRING_STATS_NUM_VALID_WORDS_S)); \ 5235 } while (0) 5236 5237 /* DWORD head_ptr__tail_ptr */ 5238 #define HTT_SRING_STATS_HEAD_PTR_M 0x0000ffff 5239 #define HTT_SRING_STATS_HEAD_PTR_S 0 5240 5241 #define HTT_SRING_STATS_TAIL_PTR_M 0xffff0000 5242 #define HTT_SRING_STATS_TAIL_PTR_S 16 5243 5244 #define HTT_SRING_STATS_HEAD_PTR_GET(_var) \ 5245 (((_var) & HTT_SRING_STATS_HEAD_PTR_M) >> \ 5246 HTT_SRING_STATS_HEAD_PTR_S) 5247 5248 #define HTT_SRING_STATS_HEAD_PTR_SET(_var, _val) \ 5249 do { \ 5250 HTT_CHECK_SET_VAL(HTT_SRING_STATS_HEAD_PTR, _val); \ 5251 ((_var) |= ((_val) << HTT_SRING_STATS_HEAD_PTR_S)); \ 5252 } while (0) 5253 5254 #define HTT_SRING_STATS_TAIL_PTR_GET(_var) \ 5255 (((_var) & HTT_SRING_STATS_TAIL_PTR_M) >> \ 5256 HTT_SRING_STATS_TAIL_PTR_S) 5257 5258 #define HTT_SRING_STATS_TAIL_PTR_SET(_var, _val) \ 5259 do { \ 5260 HTT_CHECK_SET_VAL(HTT_SRING_STATS_TAIL_PTR, _val); \ 5261 ((_var) |= ((_val) << HTT_SRING_STATS_TAIL_PTR_S)); \ 5262 } while (0) 5263 5264 /* DWORD consumer_empty__producer_full */ 5265 #define HTT_SRING_STATS_CONSUMER_EMPTY_M 0x0000ffff 5266 #define HTT_SRING_STATS_CONSUMER_EMPTY_S 0 5267 5268 #define HTT_SRING_STATS_PRODUCER_FULL_M 0xffff0000 5269 #define HTT_SRING_STATS_PRODUCER_FULL_S 16 5270 5271 #define HTT_SRING_STATS_CONSUMER_EMPTY_GET(_var) \ 5272 (((_var) & HTT_SRING_STATS_CONSUMER_EMPTY_M) >> \ 5273 HTT_SRING_STATS_CONSUMER_EMPTY_S) 5274 5275 #define HTT_SRING_STATS_CONSUMER_EMPTY_SET(_var, _val) \ 5276 do { \ 5277 HTT_CHECK_SET_VAL(HTT_SRING_STATS_CONSUMER_EMPTY, _val); \ 5278 ((_var) |= ((_val) << HTT_SRING_STATS_CONSUMER_EMPTY_S)); \ 5279 } while (0) 5280 5281 #define HTT_SRING_STATS_PRODUCER_FULL_GET(_var) \ 5282 (((_var) & HTT_SRING_STATS_PRODUCER_FULL_M) >> \ 5283 HTT_SRING_STATS_PRODUCER_FULL_S) 5284 5285 #define HTT_SRING_STATS_PRODUCER_FULL_SET(_var, _val) \ 5286 do { \ 5287 HTT_CHECK_SET_VAL(HTT_SRING_STATS_PRODUCER_FULL, _val); \ 5288 ((_var) |= ((_val) << HTT_SRING_STATS_PRODUCER_FULL_S)); \ 5289 } while (0) 5290 5291 /* DWORD prefetch_count__internal_tail_ptr */ 5292 #define HTT_SRING_STATS_PREFETCH_COUNT_M 0x0000ffff 5293 #define HTT_SRING_STATS_PREFETCH_COUNT_S 0 5294 5295 #define HTT_SRING_STATS_INTERNAL_TP_M 0xffff0000 5296 #define HTT_SRING_STATS_INTERNAL_TP_S 16 5297 5298 #define HTT_SRING_STATS_PREFETCH_COUNT_GET(_var) \ 5299 (((_var) & HTT_SRING_STATS_PREFETCH_COUNT_M) >> \ 5300 HTT_SRING_STATS_PREFETCH_COUNT_S) 5301 5302 #define HTT_SRING_STATS_PREFETCH_COUNT_SET(_var, _val) \ 5303 do { \ 5304 HTT_CHECK_SET_VAL(HTT_SRING_STATS_PREFETCH_COUNT, _val); \ 5305 ((_var) |= ((_val) << HTT_SRING_STATS_PREFETCH_COUNT_S)); \ 5306 } while (0) 5307 5308 #define HTT_SRING_STATS_INTERNAL_TP_GET(_var) \ 5309 (((_var) & HTT_SRING_STATS_INTERNAL_TP_M) >> \ 5310 HTT_SRING_STATS_INTERNAL_TP_S) 5311 5312 #define HTT_SRING_STATS_INTERNAL_TP_SET(_var, _val) \ 5313 do { \ 5314 HTT_CHECK_SET_VAL(HTT_SRING_STATS_INTERNAL_TP, _val); \ 5315 ((_var) |= ((_val) << HTT_SRING_STATS_INTERNAL_TP_S)); \ 5316 } while (0) 5317 5318 typedef struct { 5319 htt_tlv_hdr_t tlv_hdr; 5320 5321 /** 5322 * BIT [ 7 : 0] :- mac_id 5323 * BIT [15 : 8] :- ring_id 5324 * BIT [23 : 16] :- arena 0 -SRING_HRAM, 1 - SRING_HCRAM, 2 - SRING_HW2HW. 5325 * BIT [24 : 24] :- EP 0 -consumer, 1 - producer 5326 * BIT [31 : 25] :- reserved 5327 */ 5328 A_UINT32 mac_id__ring_id__arena__ep; 5329 /** DWORD aligned base memory address of the ring */ 5330 A_UINT32 base_addr_lsb; 5331 A_UINT32 base_addr_msb; 5332 /** size of ring */ 5333 A_UINT32 ring_size; 5334 /** size of each ring element */ 5335 A_UINT32 elem_size; 5336 5337 /** Ring status 5338 * 5339 * BIT [15 : 0] :- num_avail_words 5340 * BIT [31 : 16] :- num_valid_words 5341 */ 5342 A_UINT32 num_avail_words__num_valid_words; 5343 5344 /** Index of head and tail 5345 * BIT [15 : 0] :- head_ptr 5346 * BIT [31 : 16] :- tail_ptr 5347 */ 5348 A_UINT32 head_ptr__tail_ptr; 5349 5350 /** Empty or full counter of rings 5351 * BIT [15 : 0] :- consumer_empty 5352 * BIT [31 : 16] :- producer_full 5353 */ 5354 A_UINT32 consumer_empty__producer_full; 5355 5356 /** Prefetch status of consumer ring 5357 * BIT [15 : 0] :- prefetch_count 5358 * BIT [31 : 16] :- internal_tail_ptr 5359 */ 5360 A_UINT32 prefetch_count__internal_tail_ptr; 5361 } htt_stats_sring_stats_tlv; 5362 /* preserve old name alias for new name consistent with the tag name */ 5363 typedef htt_stats_sring_stats_tlv htt_sring_stats_tlv; 5364 5365 typedef struct { 5366 htt_tlv_hdr_t tlv_hdr; 5367 A_UINT32 num_records; 5368 } htt_stats_sring_cmn_tlv; 5369 /* preserve old name alias for new name consistent with the tag name */ 5370 typedef htt_stats_sring_cmn_tlv htt_sring_cmn_tlv; 5371 5372 /* STATS_TYPE : HTT_DBG_EXT_STATS_SRNG_INFO 5373 * TLV_TAGS: 5374 * - HTT_STATS_SRING_CMN_TAG 5375 * - HTT_STATS_STRING_TAG 5376 * - HTT_STATS_SRING_STATS_TAG 5377 */ 5378 /* NOTE: 5379 * This structure is for documentation, and cannot be safely used directly. 5380 * Instead, use the constituent TLV structures to fill/parse. 5381 */ 5382 #ifdef ATH_TARGET 5383 typedef struct { 5384 htt_stats_sring_cmn_tlv cmn_tlv; 5385 /** Variable based on the Number of records */ 5386 struct { 5387 htt_stats_string_tlv sring_str_tlv; 5388 htt_stats_sring_stats_tlv sring_stats_tlv; 5389 } r[1]; 5390 } htt_sring_stats_t; 5391 #endif /* ATH_TARGET */ 5392 5393 /* == PDEV TX RATE CTRL STATS == */ 5394 5395 #define HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS 12 /* 0-11 */ 5396 #define HTT_TX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS 2 /* 12, 13 */ 5397 #define HTT_TX_PDEV_STATS_NUM_EXTRA2_MCS_COUNTERS 2 /* 14, 15 */ 5398 #define HTT_TX_PDEV_STATS_NUM_GI_COUNTERS 4 5399 #define HTT_TX_PDEV_STATS_NUM_DCM_COUNTERS 5 5400 #define HTT_TX_PDEV_STATS_NUM_BW_COUNTERS 4 5401 #define HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS 8 5402 #define HTT_TX_PDEV_STATS_NUM_PREAMBLE_TYPES HTT_STATS_PREAM_COUNT 5403 #define HTT_TX_PDEV_STATS_NUM_LEGACY_CCK_STATS 4 5404 #define HTT_TX_PDEV_STATS_NUM_LEGACY_OFDM_STATS 8 5405 #define HTT_TX_PDEV_STATS_NUM_LTF 4 5406 #define HTT_TX_PDEV_STATS_NUM_11AX_TRIGGER_TYPES 6 5407 #define HTT_TX_PDEV_STATS_NUM_11BE_TRIGGER_TYPES 6 5408 #define HTT_TX_NUM_OF_SOUNDING_STATS_WORDS \ 5409 (HTT_TX_PDEV_STATS_NUM_BW_COUNTERS * \ 5410 HTT_TX_PDEV_STATS_NUM_AX_MUMIMO_USER_STATS) 5411 5412 #define HTT_TX_PDEV_RATE_STATS_MAC_ID_M 0x000000ff 5413 #define HTT_TX_PDEV_RATE_STATS_MAC_ID_S 0 5414 5415 #define HTT_TX_PDEV_RATE_STATS_MAC_ID_GET(_var) \ 5416 (((_var) & HTT_TX_PDEV_RATE_STATS_MAC_ID_M) >> \ 5417 HTT_TX_PDEV_RATE_STATS_MAC_ID_S) 5418 5419 #define HTT_TX_PDEV_RATE_STATS_MAC_ID_SET(_var, _val) \ 5420 do { \ 5421 HTT_CHECK_SET_VAL(HTT_TX_PDEV_RATE_STATS_MAC_ID, _val); \ 5422 ((_var) |= ((_val) << HTT_TX_PDEV_RATE_STATS_MAC_ID_S)); \ 5423 } while (0) 5424 5425 #define HTT_TX_PDEV_STATS_NUM_MCS_DROP_COUNTERS \ 5426 (HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS + \ 5427 HTT_TX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS + \ 5428 HTT_TX_PDEV_STATS_NUM_EXTRA2_MCS_COUNTERS) 5429 5430 #define HTT_TX_PDEV_STATS_NUM_PER_COUNTERS 101 5431 #define HTT_MAX_POWER_LEVEL 32 /* 0 to 32 dBm */ 5432 #define HTT_MAX_NEGATIVE_POWER_LEVEL 10 /* 0 to -10 dBm */ 5433 5434 /* 5435 * Introduce new TX counters to support 320MHz support and punctured modes 5436 */ 5437 typedef enum { 5438 HTT_TX_PDEV_STATS_PUNCTURED_NONE = 0, 5439 HTT_TX_PDEV_STATS_PUNCTURED_20 = 1, 5440 HTT_TX_PDEV_STATS_PUNCTURED_40 = 2, 5441 HTT_TX_PDEV_STATS_PUNCTURED_80 = 3, 5442 HTT_TX_PDEV_STATS_PUNCTURED_120 = 4, 5443 HTT_TX_PDEV_STATS_NUM_PUNCTURED_MODE_COUNTERS = 5 5444 } HTT_TX_PDEV_STATS_NUM_PUNCTURED_MODE_TYPE; 5445 5446 #define HTT_TX_PDEV_STATS_NUM_REDUCED_CHAN_TYPES 2 /* 0 - Half, 1 - Quarter */ 5447 /* 11be related updates */ 5448 #define HTT_TX_PDEV_STATS_NUM_BE_MCS_COUNTERS 16 /* 0...13,-2,-1 */ 5449 #define HTT_TX_PDEV_STATS_NUM_BE_BW_COUNTERS 5 /* 20,40,80,160,320 MHz */ 5450 5451 #define HTT_TX_PDEV_STATS_NUM_HE_SIG_B_MCS_COUNTERS 6 5452 #define HTT_TX_PDEV_STATS_NUM_EHT_SIG_MCS_COUNTERS 4 5453 5454 typedef enum { 5455 HTT_TX_PDEV_STATS_AX_RU_SIZE_26, 5456 HTT_TX_PDEV_STATS_AX_RU_SIZE_52, 5457 HTT_TX_PDEV_STATS_AX_RU_SIZE_106, 5458 HTT_TX_PDEV_STATS_AX_RU_SIZE_242, 5459 HTT_TX_PDEV_STATS_AX_RU_SIZE_484, 5460 HTT_TX_PDEV_STATS_AX_RU_SIZE_996, 5461 HTT_TX_PDEV_STATS_AX_RU_SIZE_996x2, 5462 HTT_TX_PDEV_STATS_NUM_AX_RU_SIZE_COUNTERS, 5463 } HTT_TX_PDEV_STATS_AX_RU_SIZE; 5464 5465 typedef enum { 5466 HTT_TX_PDEV_STATS_BE_RU_SIZE_26, 5467 HTT_TX_PDEV_STATS_BE_RU_SIZE_52, 5468 HTT_TX_PDEV_STATS_BE_RU_SIZE_52_26, 5469 HTT_TX_PDEV_STATS_BE_RU_SIZE_106, 5470 HTT_TX_PDEV_STATS_BE_RU_SIZE_106_26, 5471 HTT_TX_PDEV_STATS_BE_RU_SIZE_242, 5472 HTT_TX_PDEV_STATS_BE_RU_SIZE_484, 5473 HTT_TX_PDEV_STATS_BE_RU_SIZE_484_242, 5474 HTT_TX_PDEV_STATS_BE_RU_SIZE_996, 5475 HTT_TX_PDEV_STATS_BE_RU_SIZE_996_484, 5476 HTT_TX_PDEV_STATS_BE_RU_SIZE_996_484_242, 5477 HTT_TX_PDEV_STATS_BE_RU_SIZE_996x2, 5478 HTT_TX_PDEV_STATS_BE_RU_SIZE_996x2_484, 5479 HTT_TX_PDEV_STATS_BE_RU_SIZE_996x3, 5480 HTT_TX_PDEV_STATS_BE_RU_SIZE_996x3_484, 5481 HTT_TX_PDEV_STATS_BE_RU_SIZE_996x4, 5482 HTT_TX_PDEV_STATS_NUM_BE_RU_SIZE_COUNTERS, 5483 } HTT_TX_PDEV_STATS_BE_RU_SIZE; 5484 5485 typedef struct { 5486 htt_tlv_hdr_t tlv_hdr; 5487 5488 /** 5489 * BIT [ 7 : 0] :- mac_id 5490 * BIT [31 : 8] :- reserved 5491 */ 5492 A_UINT32 mac_id__word; 5493 /** Number of tx ldpc packets */ 5494 A_UINT32 tx_ldpc; 5495 /** Number of tx rts packets */ 5496 A_UINT32 rts_cnt; 5497 /** RSSI value of last ack packet (units = dB above noise floor) */ 5498 A_UINT32 ack_rssi; 5499 5500 A_UINT32 tx_mcs[HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS]; 5501 5502 /** tx_xx_mcs: currently unused */ 5503 A_UINT32 tx_su_mcs[HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS]; 5504 A_UINT32 tx_mu_mcs[HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS]; 5505 5506 /* element 0,1, ...7 -> NSS 1,2, ...8 */ 5507 A_UINT32 tx_nss[HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS]; 5508 /* element 0: 20 MHz, 1: 40 MHz, 2: 80 MHz, 3: 160 and 80+80 MHz */ 5509 A_UINT32 tx_bw[HTT_TX_PDEV_STATS_NUM_BW_COUNTERS]; 5510 A_UINT32 tx_stbc[HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS]; 5511 A_UINT32 tx_pream[HTT_TX_PDEV_STATS_NUM_PREAMBLE_TYPES]; 5512 5513 /** 5514 * Counters to track number of tx packets in each GI 5515 * (400us, 800us, 1600us & 3200us) in each mcs (0-11) 5516 */ 5517 A_UINT32 tx_gi[HTT_TX_PDEV_STATS_NUM_GI_COUNTERS][HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS]; 5518 5519 /** Counters to track packets in dcm mcs (MCS 0, 1, 3, 4) */ 5520 A_UINT32 tx_dcm[HTT_TX_PDEV_STATS_NUM_DCM_COUNTERS]; 5521 /** Number of CTS-acknowledged RTS packets */ 5522 A_UINT32 rts_success; 5523 5524 /** 5525 * Counters for legacy 11a and 11b transmissions. 5526 * 5527 * The index corresponds to: 5528 * 5529 * CCK: 0: 1 Mbps, 1: 2 Mbps, 2: 5.5 Mbps, 3: 11 Mbps 5530 * 5531 * OFDM: 0: 6 Mbps, 1: 9 Mbps, 2: 12 Mbps, 3: 18 Mbps, 5532 * 4: 24 Mbps, 5: 36 Mbps, 6: 48 Mbps, 7: 54 Mbps 5533 */ 5534 A_UINT32 tx_legacy_cck_rate[HTT_TX_PDEV_STATS_NUM_LEGACY_CCK_STATS]; 5535 A_UINT32 tx_legacy_ofdm_rate[HTT_TX_PDEV_STATS_NUM_LEGACY_OFDM_STATS]; 5536 5537 /** 11AC VHT DL MU MIMO LDPC count */ 5538 A_UINT32 ac_mu_mimo_tx_ldpc; 5539 /** 11AX HE DL MU MIMO LDPC count */ 5540 A_UINT32 ax_mu_mimo_tx_ldpc; 5541 /** 11AX HE DL MU OFDMA LDPC count */ 5542 A_UINT32 ofdma_tx_ldpc; 5543 5544 /** 5545 * Counters for 11ax HE LTF selection during TX. 5546 * 5547 * The index corresponds to: 5548 * 5549 * 0: unused, 1: 1x LTF, 2: 2x LTF, 3: 4x LTF 5550 */ 5551 A_UINT32 tx_he_ltf[HTT_TX_PDEV_STATS_NUM_LTF]; 5552 5553 /** 11AC VHT DL MU MIMO TX MCS stats */ 5554 A_UINT32 ac_mu_mimo_tx_mcs[HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS]; 5555 /** 11AX HE DL MU MIMO TX MCS stats */ 5556 A_UINT32 ax_mu_mimo_tx_mcs[HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS]; 5557 /** 11AX HE DL MU OFDMA TX MCS stats */ 5558 A_UINT32 ofdma_tx_mcs[HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS]; 5559 5560 /** 11AC VHT DL MU MIMO TX NSS stats (Indicates NSS for individual users) */ 5561 A_UINT32 ac_mu_mimo_tx_nss[HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS]; 5562 /** 11AX HE DL MU MIMO TX NSS stats (Indicates NSS for individual users) */ 5563 A_UINT32 ax_mu_mimo_tx_nss[HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS]; 5564 /** 11AX HE DL MU OFDMA TX NSS stats (Indicates NSS for individual users) */ 5565 A_UINT32 ofdma_tx_nss[HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS]; 5566 5567 /** 11AC VHT DL MU MIMO TX BW stats */ 5568 A_UINT32 ac_mu_mimo_tx_bw[HTT_TX_PDEV_STATS_NUM_BW_COUNTERS]; 5569 /** 11AX HE DL MU MIMO TX BW stats */ 5570 A_UINT32 ax_mu_mimo_tx_bw[HTT_TX_PDEV_STATS_NUM_BW_COUNTERS]; 5571 /** 11AX HE DL MU OFDMA TX BW stats */ 5572 A_UINT32 ofdma_tx_bw[HTT_TX_PDEV_STATS_NUM_BW_COUNTERS]; 5573 5574 /** 11AC VHT DL MU MIMO TX guard interval stats */ 5575 A_UINT32 ac_mu_mimo_tx_gi[HTT_TX_PDEV_STATS_NUM_GI_COUNTERS][HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS]; 5576 /** 11AX HE DL MU MIMO TX guard interval stats */ 5577 A_UINT32 ax_mu_mimo_tx_gi[HTT_TX_PDEV_STATS_NUM_GI_COUNTERS][HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS]; 5578 /** 11AX HE DL MU OFDMA TX guard interval stats */ 5579 A_UINT32 ofdma_tx_gi[HTT_TX_PDEV_STATS_NUM_GI_COUNTERS][HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS]; 5580 A_UINT32 trigger_type_11ax[HTT_TX_PDEV_STATS_NUM_11AX_TRIGGER_TYPES]; 5581 A_UINT32 tx_11ax_su_ext; 5582 5583 /* Stats for MCS 12/13 */ 5584 A_UINT32 tx_mcs_ext[HTT_TX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS]; 5585 A_UINT32 tx_stbc_ext[HTT_TX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS]; 5586 A_UINT32 tx_gi_ext[HTT_TX_PDEV_STATS_NUM_GI_COUNTERS][HTT_TX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS]; 5587 /** 11AX VHT DL MU MIMO extended TX MCS stats for MCS 12/13 */ 5588 A_UINT32 ax_mu_mimo_tx_mcs_ext[HTT_TX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS]; 5589 /** 11AX VHT DL MU OFDMA extended TX MCS stats for MCS 12/13 */ 5590 A_UINT32 ofdma_tx_mcs_ext[HTT_TX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS]; 5591 /** 11AX VHT DL MU MIMO extended TX guard interval stats for MCS 12/13 */ 5592 A_UINT32 ax_mu_mimo_tx_gi_ext[HTT_TX_PDEV_STATS_NUM_GI_COUNTERS][HTT_TX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS]; 5593 /** 11AX VHT DL MU OFDMA extended TX guard interval stats for MCS 12/13 */ 5594 A_UINT32 ofdma_tx_gi_ext[HTT_TX_PDEV_STATS_NUM_GI_COUNTERS][HTT_TX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS]; 5595 /* Stats for MCS 14/15 */ 5596 A_UINT32 tx_mcs_ext_2[HTT_TX_PDEV_STATS_NUM_EXTRA2_MCS_COUNTERS]; 5597 A_UINT32 tx_bw_320mhz; 5598 A_UINT32 tx_gi_ext_2[HTT_TX_PDEV_STATS_NUM_GI_COUNTERS][HTT_TX_PDEV_STATS_NUM_EXTRA2_MCS_COUNTERS]; 5599 A_UINT32 tx_su_punctured_mode[HTT_TX_PDEV_STATS_NUM_PUNCTURED_MODE_COUNTERS]; 5600 A_UINT32 reduced_tx_bw[HTT_TX_PDEV_STATS_NUM_REDUCED_CHAN_TYPES][HTT_TX_PDEV_STATS_NUM_BW_COUNTERS]; 5601 /** 11AC VHT DL MU MIMO TX BW stats at reduced channel config */ 5602 A_UINT32 reduced_ac_mu_mimo_tx_bw[HTT_TX_PDEV_STATS_NUM_REDUCED_CHAN_TYPES][HTT_TX_PDEV_STATS_NUM_BW_COUNTERS]; 5603 /** 11AX HE DL MU MIMO TX BW stats at reduced channel config */ 5604 A_UINT32 reduced_ax_mu_mimo_tx_bw[HTT_TX_PDEV_STATS_NUM_REDUCED_CHAN_TYPES][HTT_TX_PDEV_STATS_NUM_BW_COUNTERS]; 5605 /** 11AX HE DL MU OFDMA TX BW stats at reduced channel config */ 5606 A_UINT32 reduced_ax_mu_ofdma_tx_bw[HTT_TX_PDEV_STATS_NUM_REDUCED_CHAN_TYPES][HTT_TX_PDEV_STATS_NUM_BW_COUNTERS]; 5607 /** 11AX HE DL MU OFDMA TX RU Size stats */ 5608 A_UINT32 ofdma_tx_ru_size[HTT_TX_PDEV_STATS_NUM_AX_RU_SIZE_COUNTERS]; 5609 /** 11AX HE DL MU OFDMA HE-SIG-B MCS stats */ 5610 A_UINT32 ofdma_he_sig_b_mcs[HTT_TX_PDEV_STATS_NUM_HE_SIG_B_MCS_COUNTERS]; 5611 /** 11AX HE SU data + embedded trigger PPDU success stats (stats for HETP ack success PPDU cnt) */ 5612 A_UINT32 ax_su_embedded_trigger_data_ppdu; 5613 /** 11AX HE SU data + embedded trigger PPDU failure stats (stats for HETP ack failure PPDU cnt) */ 5614 A_UINT32 ax_su_embedded_trigger_data_ppdu_err; 5615 /** sta side trigger stats */ 5616 A_UINT32 trigger_type_11be[HTT_TX_PDEV_STATS_NUM_11BE_TRIGGER_TYPES]; 5617 /** Stats for Extra EHT LTF */ 5618 A_UINT32 extra_eht_ltf; 5619 /** Counter for Extra EHT LTFs in OFDMA sequences */ 5620 A_UINT32 extra_eht_ltf_ofdma; 5621 /** 11AX HE UL_BA RU Size stats */ 5622 A_UINT32 ofdma_ba_ru_size[HTT_TX_PDEV_STATS_NUM_AX_RU_SIZE_COUNTERS]; 5623 } htt_stats_tx_pdev_rate_stats_tlv; 5624 /* preserve old name alias for new name consistent with the tag name */ 5625 typedef htt_stats_tx_pdev_rate_stats_tlv htt_tx_pdev_rate_stats_tlv; 5626 5627 typedef struct { 5628 /* 11be mode pdev rate stats; placed in a separate TLV to adhere to size restrictions */ 5629 htt_tlv_hdr_t tlv_hdr; 5630 /** 11BE EHT DL MU MIMO TX MCS stats */ 5631 A_UINT32 be_mu_mimo_tx_mcs[HTT_TX_PDEV_STATS_NUM_BE_MCS_COUNTERS]; 5632 /** 11BE EHT DL MU MIMO TX NSS stats (Indicates NSS for individual users) */ 5633 A_UINT32 be_mu_mimo_tx_nss[HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS]; 5634 /** 11BE EHT DL MU MIMO TX BW stats */ 5635 A_UINT32 be_mu_mimo_tx_bw[HTT_TX_PDEV_STATS_NUM_BE_BW_COUNTERS]; 5636 /** 11BE EHT DL MU MIMO TX guard interval stats */ 5637 A_UINT32 be_mu_mimo_tx_gi[HTT_TX_PDEV_STATS_NUM_GI_COUNTERS][HTT_TX_PDEV_STATS_NUM_BE_MCS_COUNTERS]; 5638 /** 11BE DL MU MIMO LDPC count */ 5639 A_UINT32 be_mu_mimo_tx_ldpc; 5640 } htt_stats_tx_pdev_be_rate_stats_tlv; 5641 /* preserve old name alias for new name consistent with the tag name */ 5642 typedef htt_stats_tx_pdev_be_rate_stats_tlv htt_tx_pdev_rate_stats_be_tlv; 5643 5644 typedef struct { 5645 /* 5646 * SAWF pdev rate stats; 5647 * placed in a separate TLV to adhere to size restrictions 5648 */ 5649 htt_tlv_hdr_t tlv_hdr; 5650 5651 /** 5652 * Counter incremented when MCS is dropped due to the successive retries 5653 * to a peer reaching the configured limit. 5654 */ 5655 A_UINT32 rate_retry_mcs_drop_cnt; 5656 5657 /** 5658 * histogram of MCS rate drop down, indexed by pre-drop MCS 5659 */ 5660 A_UINT32 mcs_drop_rate[HTT_TX_PDEV_STATS_NUM_MCS_DROP_COUNTERS]; 5661 5662 /** 5663 * PPDU PER histogram - each PPDU has its PER computed, 5664 * and the bin corresponding to that PER percentage is incremented. 5665 */ 5666 A_UINT32 per_histogram_cnt[HTT_TX_PDEV_STATS_NUM_PER_COUNTERS]; 5667 5668 /** 5669 * When the service class contains delay bound rate parameters which 5670 * indicate low latency and we enable latency-based RA params then 5671 * the low_latency_rate_count will be incremented. 5672 * This counts the number of peer-TIDs that have been categorized as 5673 * low-latency. 5674 */ 5675 A_UINT32 low_latency_rate_cnt; 5676 5677 /** Indicate how many times rate drop happened within SIFS burst */ 5678 A_UINT32 su_burst_rate_drop_cnt; 5679 5680 /** Indicates how many within SIFS burst failed to deliver any pkt */ 5681 A_UINT32 su_burst_rate_drop_fail_cnt; 5682 } htt_stats_tx_pdev_sawf_rate_stats_tlv; 5683 /* preserve old name alias for new name consistent with the tag name */ 5684 typedef htt_stats_tx_pdev_sawf_rate_stats_tlv htt_tx_pdev_rate_stats_sawf_tlv; 5685 5686 typedef struct { 5687 htt_tlv_hdr_t tlv_hdr; 5688 5689 /** 5690 * BIT [ 7 : 0] :- mac_id 5691 * BIT [31 : 8] :- reserved 5692 */ 5693 A_UINT32 mac_id__word; 5694 5695 /** 11BE EHT DL MU OFDMA LDPC count */ 5696 A_UINT32 be_ofdma_tx_ldpc; 5697 /** 11BE EHT DL MU OFDMA TX MCS stats */ 5698 A_UINT32 be_ofdma_tx_mcs[HTT_TX_PDEV_STATS_NUM_BE_MCS_COUNTERS]; 5699 /** 5700 * 11BE EHT DL MU OFDMA TX NSS stats (Indicates NSS for individual users) 5701 */ 5702 A_UINT32 be_ofdma_tx_nss[HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS]; 5703 /** 11BE EHT DL MU OFDMA TX BW stats */ 5704 A_UINT32 be_ofdma_tx_bw[HTT_TX_PDEV_STATS_NUM_BE_BW_COUNTERS]; 5705 /** 11BE EHT DL MU OFDMA TX guard interval stats */ 5706 A_UINT32 be_ofdma_tx_gi[HTT_TX_PDEV_STATS_NUM_GI_COUNTERS][HTT_TX_PDEV_STATS_NUM_BE_MCS_COUNTERS]; 5707 /** 11BE EHT DL MU OFDMA TX RU Size stats */ 5708 A_UINT32 be_ofdma_tx_ru_size[HTT_TX_PDEV_STATS_NUM_BE_RU_SIZE_COUNTERS]; 5709 /** 11BE EHT DL MU OFDMA EHT-SIG MCS stats */ 5710 A_UINT32 be_ofdma_eht_sig_mcs[HTT_TX_PDEV_STATS_NUM_EHT_SIG_MCS_COUNTERS]; 5711 A_UINT32 be_ofdma_ba_ru_size[HTT_TX_PDEV_STATS_NUM_BE_RU_SIZE_COUNTERS]; 5712 } htt_stats_tx_pdev_rate_stats_be_ofdma_tlv; 5713 /* preserve old name alias for new name consistent with the tag name */ 5714 typedef htt_stats_tx_pdev_rate_stats_be_ofdma_tlv 5715 htt_tx_pdev_rate_stats_be_ofdma_tlv; 5716 5717 typedef struct { 5718 htt_tlv_hdr_t tlv_hdr; 5719 /** tx_ppdu_dur_hist: 5720 * Tx PPDU duration histogram, which holds the tx duration of PPDUs 5721 * under histogram bins of interval 250us 5722 */ 5723 A_UINT32 tx_ppdu_dur_hist[HTT_PDEV_STATS_PPDU_DUR_HIST_BINS]; 5724 A_UINT32 tx_success_time_us_low; 5725 A_UINT32 tx_success_time_us_high; 5726 A_UINT32 tx_fail_time_us_low; 5727 A_UINT32 tx_fail_time_us_high; 5728 A_UINT32 pdev_up_time_us_low; 5729 A_UINT32 pdev_up_time_us_high; 5730 /** tx_ofdma_ppdu_dur_hist: 5731 * Tx OFDMA PPDU duration histogram, which holds the tx duration of 5732 * OFDMA PPDUs under histogram bins of interval 250us 5733 */ 5734 A_UINT32 tx_ofdma_ppdu_dur_hist[HTT_PDEV_STATS_PPDU_DUR_HIST_BINS]; 5735 } htt_stats_tx_pdev_ppdu_dur_tlv; 5736 /* preserve old name alias for new name consistent with the tag name */ 5737 typedef htt_stats_tx_pdev_ppdu_dur_tlv htt_tx_pdev_ppdu_dur_stats_tlv; 5738 5739 /* STATS_TYPE : HTT_DBG_EXT_STATS_PDEV_TX_RATE 5740 * TLV_TAGS: 5741 * - HTT_STATS_TX_PDEV_RATE_STATS_TAG 5742 */ 5743 /* NOTE: 5744 * This structure is for documentation, and cannot be safely used directly. 5745 * Instead, use the constituent TLV structures to fill/parse. 5746 */ 5747 #ifdef ATH_TARGET 5748 typedef struct { 5749 htt_stats_tx_pdev_rate_stats_tlv rate_tlv; 5750 htt_stats_tx_pdev_be_rate_stats_tlv rate_be_tlv; 5751 htt_stats_tx_pdev_sawf_rate_stats_tlv rate_sawf_tlv; 5752 htt_stats_tx_pdev_ppdu_dur_tlv tx_ppdu_dur_tlv; 5753 } htt_tx_pdev_rate_stats_t; 5754 #endif /* ATH_TARGET */ 5755 5756 /* == PDEV RX RATE CTRL STATS == */ 5757 5758 #define HTT_RX_PDEV_STATS_NUM_LEGACY_CCK_STATS 4 5759 #define HTT_RX_PDEV_STATS_NUM_LEGACY_OFDM_STATS 8 5760 #define HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS 12 /* 0-11 */ 5761 #define HTT_RX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS 2 /* 12, 13 */ 5762 #define HTT_RX_PDEV_STATS_NUM_EXTRA2_MCS_COUNTERS 2 /* 14, 15 */ 5763 #define HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS_EXT 14 /* 0-13 */ 5764 #define HTT_RX_PDEV_STATS_NUM_GI_COUNTERS 4 5765 #define HTT_RX_PDEV_STATS_NUM_DCM_COUNTERS 5 5766 #define HTT_RX_PDEV_STATS_NUM_BW_COUNTERS 4 5767 #define HTT_RX_PDEV_STATS_TOTAL_BW_COUNTERS \ 5768 (HTT_RX_PDEV_STATS_NUM_BW_EXT_COUNTERS + HTT_RX_PDEV_STATS_NUM_BW_COUNTERS) 5769 #define HTT_RX_PDEV_STATS_NUM_BW_EXT2_COUNTERS 5 /* 20, 40, 80, 160, 320Mhz */ 5770 #define HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS 8 5771 #define HTT_RX_PDEV_STATS_ULMUMIMO_NUM_SPATIAL_STREAMS 8 5772 #define HTT_RX_PDEV_STATS_NUM_PREAMBLE_TYPES HTT_STATS_PREAM_COUNT 5773 #define HTT_RX_PDEV_MAX_OFDMA_NUM_USER 8 5774 #define HTT_RX_PDEV_MAX_ULMUMIMO_NUM_USER 8 5775 #define HTT_RX_PDEV_STATS_RXEVM_MAX_PILOTS_PER_NSS 16 5776 #define HTT_RX_PDEV_STATS_NUM_BE_MCS_COUNTERS 16 /* 0-13, -2, -1 */ 5777 #define HTT_RX_PDEV_STATS_NUM_BE_BW_COUNTERS 5 /* 20,40,80,160,320 MHz */ 5778 5779 /* HTT_RX_PDEV_STATS_NUM_RU_SIZE_COUNTERS: 5780 * RU size index 0: HTT_UL_OFDMA_V0_RU_SIZE_RU_26 5781 * RU size index 1: HTT_UL_OFDMA_V0_RU_SIZE_RU_52 5782 * RU size index 2: HTT_UL_OFDMA_V0_RU_SIZE_RU_106 5783 * RU size index 3: HTT_UL_OFDMA_V0_RU_SIZE_RU_242 5784 * RU size index 4: HTT_UL_OFDMA_V0_RU_SIZE_RU_484 5785 * RU size index 5: HTT_UL_OFDMA_V0_RU_SIZE_RU_996 5786 */ 5787 #define HTT_RX_PDEV_STATS_NUM_RU_SIZE_COUNTERS 6 5788 /* HTT_RX_PDEV_STATS_NUM_RU_SIZE_160MHZ_CNTRS: 5789 * RU size index 0: HTT_UL_OFDMA_V0_RU_SIZE_RU_26 5790 * RU size index 1: HTT_UL_OFDMA_V0_RU_SIZE_RU_52 5791 * RU size index 2: HTT_UL_OFDMA_V0_RU_SIZE_RU_106 5792 * RU size index 3: HTT_UL_OFDMA_V0_RU_SIZE_RU_242 5793 * RU size index 4: HTT_UL_OFDMA_V0_RU_SIZE_RU_484 5794 * RU size index 5: HTT_UL_OFDMA_V0_RU_SIZE_RU_996 5795 * RU size index 6: HTT_UL_OFDMA_V0_RU_SIZE_RU_996x2 5796 */ 5797 #define HTT_RX_PDEV_STATS_NUM_RU_SIZE_160MHZ_CNTRS 7 /* includes 996x2 */ 5798 5799 typedef enum { 5800 HTT_RX_PDEV_STATS_BE_RU_SIZE_26, 5801 HTT_RX_PDEV_STATS_BE_RU_SIZE_52, 5802 HTT_RX_PDEV_STATS_BE_RU_SIZE_52_26, 5803 HTT_RX_PDEV_STATS_BE_RU_SIZE_106, 5804 HTT_RX_PDEV_STATS_BE_RU_SIZE_106_26, 5805 HTT_RX_PDEV_STATS_BE_RU_SIZE_242, 5806 HTT_RX_PDEV_STATS_BE_RU_SIZE_484, 5807 HTT_RX_PDEV_STATS_BE_RU_SIZE_484_242, 5808 HTT_RX_PDEV_STATS_BE_RU_SIZE_996, 5809 HTT_RX_PDEV_STATS_BE_RU_SIZE_996_484, 5810 HTT_RX_PDEV_STATS_BE_RU_SIZE_996_484_242, 5811 HTT_RX_PDEV_STATS_BE_RU_SIZE_996x2, 5812 HTT_RX_PDEV_STATS_BE_RU_SIZE_996x2_484, 5813 HTT_RX_PDEV_STATS_BE_RU_SIZE_996x3, 5814 HTT_RX_PDEV_STATS_BE_RU_SIZE_996x3_484, 5815 HTT_RX_PDEV_STATS_BE_RU_SIZE_996x4, 5816 HTT_RX_PDEV_STATS_NUM_BE_RU_SIZE_COUNTERS, 5817 } HTT_RX_PDEV_STATS_BE_RU_SIZE; 5818 5819 #define HTT_RX_PDEV_RATE_STATS_MAC_ID_M 0x000000ff 5820 #define HTT_RX_PDEV_RATE_STATS_MAC_ID_S 0 5821 5822 #define HTT_RX_PDEV_RATE_STATS_MAC_ID_GET(_var) \ 5823 (((_var) & HTT_RX_PDEV_RATE_STATS_MAC_ID_M) >> \ 5824 HTT_RX_PDEV_RATE_STATS_MAC_ID_S) 5825 5826 #define HTT_RX_PDEV_RATE_STATS_MAC_ID_SET(_var, _val) \ 5827 do { \ 5828 HTT_CHECK_SET_VAL(HTT_RX_PDEV_RATE_STATS_MAC_ID, _val); \ 5829 ((_var) |= ((_val) << HTT_RX_PDEV_RATE_STATS_MAC_ID_S)); \ 5830 } while (0) 5831 5832 /* Introduce new RX counters to support 320MHZ support and punctured modes */ 5833 typedef enum { 5834 HTT_RX_PDEV_STATS_PUNCTURED_NONE = 0, 5835 HTT_RX_PDEV_STATS_PUNCTURED_20 = 1, 5836 HTT_RX_PDEV_STATS_PUNCTURED_40 = 2, 5837 HTT_RX_PDEV_STATS_PUNCTURED_80 = 3, 5838 HTT_RX_PDEV_STATS_PUNCTURED_120 = 4, 5839 HTT_RX_PDEV_STATS_NUM_PUNCTURED_MODE_COUNTERS = 5 5840 } HTT_RX_PDEV_STATS_NUM_PUNCTURED_MODE_TYPE; 5841 5842 #define HTT_RX_PDEV_STATS_NUM_REDUCED_CHAN_TYPES 2 /* 0 - Half, 1 - Quarter */ 5843 5844 typedef struct { 5845 htt_tlv_hdr_t tlv_hdr; 5846 5847 /** 5848 * BIT [ 7 : 0] :- mac_id 5849 * BIT [31 : 8] :- reserved 5850 */ 5851 A_UINT32 mac_id__word; 5852 A_UINT32 nsts; 5853 5854 /** Number of rx ldpc packets */ 5855 A_UINT32 rx_ldpc; 5856 /** Number of rx rts packets */ 5857 A_UINT32 rts_cnt; 5858 5859 /** units = dB above noise floor */ 5860 A_UINT32 rssi_mgmt; 5861 /** units = dB above noise floor */ 5862 A_UINT32 rssi_data; 5863 /** units = dB above noise floor */ 5864 A_UINT32 rssi_comb; 5865 A_UINT32 rx_mcs[HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS]; 5866 /** element 0,1, ...7 -> NSS 1,2, ...8 */ 5867 A_UINT32 rx_nss[HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS]; 5868 A_UINT32 rx_dcm[HTT_RX_PDEV_STATS_NUM_DCM_COUNTERS]; 5869 A_UINT32 rx_stbc[HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS]; 5870 /** element 0: 20 MHz, 1: 40 MHz, 2: 80 MHz, 3: 160 and 80+80 MHz */ 5871 A_UINT32 rx_bw[HTT_RX_PDEV_STATS_NUM_BW_COUNTERS]; 5872 A_UINT32 rx_pream[HTT_RX_PDEV_STATS_NUM_PREAMBLE_TYPES]; 5873 /** units = dB above noise floor */ 5874 A_UINT8 rssi_chain[HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS][HTT_RX_PDEV_STATS_NUM_BW_COUNTERS]; 5875 5876 /** Counters to track number of rx packets in each GI in each mcs (0-11) */ 5877 A_UINT32 rx_gi[HTT_RX_PDEV_STATS_NUM_GI_COUNTERS][HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS]; 5878 /** rx Signal Strength value in dBm unit */ 5879 A_INT32 rssi_in_dbm; 5880 5881 A_UINT32 rx_11ax_su_ext; 5882 A_UINT32 rx_11ac_mumimo; 5883 A_UINT32 rx_11ax_mumimo; 5884 A_UINT32 rx_11ax_ofdma; 5885 A_UINT32 txbf; 5886 A_UINT32 rx_legacy_cck_rate[HTT_RX_PDEV_STATS_NUM_LEGACY_CCK_STATS]; 5887 A_UINT32 rx_legacy_ofdm_rate[HTT_RX_PDEV_STATS_NUM_LEGACY_OFDM_STATS]; 5888 A_UINT32 rx_active_dur_us_low; 5889 A_UINT32 rx_active_dur_us_high; 5890 5891 /** number of times UL MU MIMO RX packets received */ 5892 A_UINT32 rx_11ax_ul_ofdma; 5893 5894 /** 11AX HE UL OFDMA RX TB PPDU MCS stats */ 5895 A_UINT32 ul_ofdma_rx_mcs[HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS]; 5896 /** 11AX HE UL OFDMA RX TB PPDU GI stats */ 5897 A_UINT32 ul_ofdma_rx_gi[HTT_TX_PDEV_STATS_NUM_GI_COUNTERS][HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS]; 5898 /** 5899 * 11AX HE UL OFDMA RX TB PPDU NSS stats 5900 * (Increments the individual user NSS in the OFDMA PPDU received) 5901 */ 5902 A_UINT32 ul_ofdma_rx_nss[HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS]; 5903 /** 11AX HE UL OFDMA RX TB PPDU BW stats */ 5904 A_UINT32 ul_ofdma_rx_bw[HTT_TX_PDEV_STATS_NUM_BW_COUNTERS]; 5905 /** Number of times UL OFDMA TB PPDUs received with stbc */ 5906 A_UINT32 ul_ofdma_rx_stbc; 5907 /** Number of times UL OFDMA TB PPDUs received with ldpc */ 5908 A_UINT32 ul_ofdma_rx_ldpc; 5909 5910 /** 5911 * Number of non data PPDUs received for each degree (number of users) 5912 * in UL OFDMA 5913 */ 5914 A_UINT32 rx_ulofdma_non_data_ppdu[HTT_RX_PDEV_MAX_OFDMA_NUM_USER]; 5915 /** 5916 * Number of data ppdus received for each degree (number of users) 5917 * in UL OFDMA 5918 */ 5919 A_UINT32 rx_ulofdma_data_ppdu[HTT_RX_PDEV_MAX_OFDMA_NUM_USER]; 5920 /** 5921 * Number of mpdus passed for each degree (number of users) 5922 * in UL OFDMA TB PPDU 5923 */ 5924 A_UINT32 rx_ulofdma_mpdu_ok[HTT_RX_PDEV_MAX_OFDMA_NUM_USER]; 5925 /** 5926 * Number of mpdus failed for each degree (number of users) 5927 * in UL OFDMA TB PPDU 5928 */ 5929 A_UINT32 rx_ulofdma_mpdu_fail[HTT_RX_PDEV_MAX_OFDMA_NUM_USER]; 5930 5931 A_UINT32 nss_count; 5932 A_UINT32 pilot_count; 5933 /** RxEVM stats in dB */ 5934 A_INT32 rx_pilot_evm_dB[HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS][HTT_RX_PDEV_STATS_RXEVM_MAX_PILOTS_PER_NSS]; 5935 /** 5936 * EVM mean across pilots, computed as 5937 * mean(10*log10(rx_pilot_evm_linear)) = mean(rx_pilot_evm_dB) 5938 */ 5939 A_INT32 rx_pilot_evm_dB_mean[HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS]; 5940 /** dBm units */ 5941 A_INT8 rx_ul_fd_rssi[HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS][HTT_RX_PDEV_MAX_OFDMA_NUM_USER]; 5942 /** per_chain_rssi_pkt_type: 5943 * This field shows what type of rx frame the per-chain RSSI was computed 5944 * on, by recording the frame type and sub-type as bit-fields within this 5945 * field: 5946 * BIT [3 : 0] :- IEEE80211_FC0_TYPE 5947 * BIT [7 : 4] :- IEEE80211_FC0_SUBTYPE 5948 * BIT [31 : 8] :- Reserved 5949 */ 5950 A_UINT32 per_chain_rssi_pkt_type; 5951 A_INT8 rx_per_chain_rssi_in_dbm[HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS][HTT_RX_PDEV_STATS_NUM_BW_COUNTERS]; 5952 A_UINT32 rx_su_ndpa; 5953 A_UINT32 rx_11ax_su_txbf_mcs[HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS]; 5954 A_UINT32 rx_mu_ndpa; 5955 A_UINT32 rx_11ax_mu_txbf_mcs[HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS]; 5956 A_UINT32 rx_br_poll; 5957 A_UINT32 rx_11ax_dl_ofdma_mcs[HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS]; 5958 A_UINT32 rx_11ax_dl_ofdma_ru[HTT_RX_PDEV_STATS_NUM_RU_SIZE_COUNTERS]; 5959 5960 /** 5961 * Number of non data ppdus received for each degree (number of users) 5962 * with UL MUMIMO 5963 */ 5964 A_UINT32 rx_ulmumimo_non_data_ppdu[HTT_RX_PDEV_MAX_ULMUMIMO_NUM_USER]; 5965 /** 5966 * Number of data ppdus received for each degree (number of users) 5967 * with UL MUMIMO 5968 */ 5969 A_UINT32 rx_ulmumimo_data_ppdu[HTT_RX_PDEV_MAX_ULMUMIMO_NUM_USER]; 5970 /** 5971 * Number of mpdus passed for each degree (number of users) 5972 * with UL MUMIMO TB PPDU 5973 */ 5974 A_UINT32 rx_ulmumimo_mpdu_ok[HTT_RX_PDEV_MAX_ULMUMIMO_NUM_USER]; 5975 /** 5976 * Number of mpdus failed for each degree (number of users) 5977 * with UL MUMIMO TB PPDU 5978 */ 5979 A_UINT32 rx_ulmumimo_mpdu_fail[HTT_RX_PDEV_MAX_ULMUMIMO_NUM_USER]; 5980 /** 5981 * Number of non data ppdus received for each degree (number of users) 5982 * in UL OFDMA 5983 */ 5984 A_UINT32 rx_ulofdma_non_data_nusers[HTT_RX_PDEV_MAX_OFDMA_NUM_USER]; 5985 /** 5986 * Number of data ppdus received for each degree (number of users) 5987 *in UL OFDMA 5988 */ 5989 A_UINT32 rx_ulofdma_data_nusers[HTT_RX_PDEV_MAX_OFDMA_NUM_USER]; 5990 5991 /* Stats for MCS 12/13 */ 5992 A_UINT32 rx_mcs_ext[HTT_RX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS]; 5993 /* 5994 * NOTE - this TLV is already large enough that it causes the HTT message 5995 * carrying it to be nearly at the message size limit that applies to 5996 * many targets/hosts. 5997 * No further fields should be added to this TLV without very careful 5998 * review to ensure the size increase is acceptable. 5999 */ 6000 } htt_stats_rx_pdev_rate_stats_tlv; 6001 /* preserve old name alias for new name consistent with the tag name */ 6002 typedef htt_stats_rx_pdev_rate_stats_tlv htt_rx_pdev_rate_stats_tlv; 6003 6004 typedef struct { 6005 htt_tlv_hdr_t tlv_hdr; 6006 /** Tx PPDU duration histogram **/ 6007 A_UINT32 rx_ppdu_dur_hist[HTT_PDEV_STATS_PPDU_DUR_HIST_BINS]; 6008 } htt_stats_rx_pdev_ppdu_dur_tlv; 6009 /* preserve old name alias for new name consistent with the tag name */ 6010 typedef htt_stats_rx_pdev_ppdu_dur_tlv htt_rx_pdev_ppdu_dur_stats_tlv; 6011 6012 #define HTT_STATS_RX_RSSI_HIST_BINS 24 6013 #define HTT_STATS_RX_RSSI_HIST_OFFSET_DBM -30 6014 #define HTT_STATS_RX_RSSI_DB_PER_BIN -3 6015 6016 typedef struct { 6017 htt_tlv_hdr_t tlv_hdr; 6018 6019 /** rssi_in_dbm_ppdu_cnt : 6020 * Number of PPDUs received within each RSSI range 6021 * rssi_in_dbm_ppdu_cnt[0] : number of PPDUs received > -30 dBm 6022 * rssi_in_dbm_ppdu_cnt[1] : number of PPDUs received from [-30 to -32] dBm 6023 * rssi_in_dbm_ppdu_cnt[2] : number of PPDUs received from [-33 to -35] dBm 6024 * ... 6025 * rssi_in_dbm_ppdu_cnt[22] : number of PPDUs received from [-93 to -95] dBm 6026 * rssi_in_dbm_ppdu_cnt[23] : number of PPDUs received <= -96 dBm 6027 **/ 6028 A_UINT32 rssi_in_dbm_ppdu_cnt[HTT_STATS_RX_RSSI_HIST_BINS]; 6029 } htt_stats_rx_pdev_rssi_hist_tlv; 6030 6031 /* STATS_TYPE : HTT_DBG_EXT_STATS_PDEV_RX_RATE 6032 * TLV_TAGS: 6033 * - HTT_STATS_RX_PDEV_RATE_STATS_TAG 6034 */ 6035 /* NOTE: 6036 * This structure is for documentation, and cannot be safely used directly. 6037 * Instead, use the constituent TLV structures to fill/parse. 6038 */ 6039 #ifdef ATH_TARGET 6040 typedef struct { 6041 htt_stats_rx_pdev_rate_stats_tlv rate_tlv; 6042 htt_stats_rx_pdev_ppdu_dur_tlv rx_ppdu_dur_tlv; 6043 htt_stats_rx_pdev_rssi_hist_tlv rx_ppdu_rssi_hist_tlv; 6044 } htt_rx_pdev_rate_stats_t; 6045 #endif /* ATH_TARGET */ 6046 6047 typedef struct { 6048 htt_tlv_hdr_t tlv_hdr; 6049 /** units = dB above noise floor */ 6050 A_UINT8 rssi_chain_ext[HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS][HTT_RX_PDEV_STATS_NUM_BW_EXT_COUNTERS]; 6051 A_INT8 rx_per_chain_rssi_ext_in_dbm[HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS][HTT_RX_PDEV_STATS_NUM_BW_EXT_COUNTERS]; 6052 /** rx mcast signal strength value in dBm unit */ 6053 A_INT32 rssi_mcast_in_dbm; 6054 /** rx mgmt packet signal Strength value in dBm unit */ 6055 A_INT32 rssi_mgmt_in_dbm; 6056 /* 6057 * Stats for MCS 0-13 since rx_pdev_rate_stats_tlv cannot be updated, 6058 * due to message size limitations. 6059 */ 6060 A_UINT32 rx_mcs_ext[HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS_EXT]; 6061 A_UINT32 rx_stbc_ext[HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS_EXT]; 6062 A_UINT32 rx_gi_ext[HTT_RX_PDEV_STATS_NUM_GI_COUNTERS][HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS_EXT]; 6063 A_UINT32 ul_ofdma_rx_mcs_ext[HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS_EXT]; 6064 A_UINT32 ul_ofdma_rx_gi_ext[HTT_TX_PDEV_STATS_NUM_GI_COUNTERS][HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS_EXT]; 6065 A_UINT32 rx_11ax_su_txbf_mcs_ext[HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS_EXT]; 6066 A_UINT32 rx_11ax_mu_txbf_mcs_ext[HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS_EXT]; 6067 A_UINT32 rx_11ax_dl_ofdma_mcs_ext[HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS_EXT]; 6068 /* MCS 14,15 */ 6069 A_UINT32 rx_mcs_ext_2[HTT_RX_PDEV_STATS_NUM_EXTRA2_MCS_COUNTERS]; 6070 A_UINT32 rx_bw_ext[HTT_RX_PDEV_STATS_NUM_BW_EXT2_COUNTERS]; 6071 A_UINT32 rx_gi_ext_2[HTT_RX_PDEV_STATS_NUM_GI_COUNTERS][HTT_RX_PDEV_STATS_NUM_EXTRA2_MCS_COUNTERS]; 6072 A_UINT32 rx_su_punctured_mode[HTT_RX_PDEV_STATS_NUM_PUNCTURED_MODE_COUNTERS]; 6073 A_UINT32 reduced_rx_bw[HTT_RX_PDEV_STATS_NUM_REDUCED_CHAN_TYPES][HTT_RX_PDEV_STATS_NUM_BW_COUNTERS]; 6074 A_UINT8 rssi_chain_ext_2[HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS][HTT_RX_PDEV_STATS_NUM_BW_EXT_2_COUNTERS]; /* units = dB above noise floor */ 6075 A_INT8 rx_per_chain_rssi_ext_2_in_dbm[HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS][HTT_RX_PDEV_STATS_NUM_BW_EXT_2_COUNTERS]; 6076 } htt_stats_rx_pdev_rate_ext_stats_tlv; 6077 /* preserve old name alias for new name consistent with the tag name */ 6078 typedef htt_stats_rx_pdev_rate_ext_stats_tlv htt_rx_pdev_rate_ext_stats_tlv; 6079 6080 /* STATS_TYPE : HTT_DBG_EXT_STATS_PDEV_RX_RATE_EXT 6081 * TLV_TAGS: 6082 * - HTT_STATS_RX_PDEV_RATE_EXT_STATS_TAG 6083 */ 6084 /* NOTE: 6085 * This structure is for documentation, and cannot be safely used directly. 6086 * Instead, use the constituent TLV structures to fill/parse. 6087 */ 6088 #ifdef ATH_TARGET 6089 typedef struct { 6090 htt_stats_rx_pdev_rate_ext_stats_tlv rate_tlv; 6091 } htt_rx_pdev_rate_ext_stats_t; 6092 #endif /* ATH_TARGET */ 6093 6094 #define HTT_STATS_CMN_MAC_ID_M 0x000000ff 6095 #define HTT_STATS_CMN_MAC_ID_S 0 6096 6097 #define HTT_STATS_CMN_MAC_ID_GET(_var) \ 6098 (((_var) & HTT_STATS_CMN_MAC_ID_M) >> \ 6099 HTT_STATS_CMN_MAC_ID_S) 6100 6101 #define HTT_STATS_CMN_MAC_ID_SET(_var, _val) \ 6102 do { \ 6103 HTT_CHECK_SET_VAL(HTT_STATS_CMN_MAC_ID, _val); \ 6104 ((_var) |= ((_val) << HTT_STATS_CMN_MAC_ID_S)); \ 6105 } while (0) 6106 6107 #define HTT_RX_UL_MAX_UPLINK_RSSI_TRACK 5 6108 6109 typedef struct { 6110 htt_tlv_hdr_t tlv_hdr; 6111 6112 /** 6113 * BIT [ 7 : 0] :- mac_id 6114 * BIT [31 : 8] :- reserved 6115 */ 6116 A_UINT32 mac_id__word; 6117 6118 A_UINT32 rx_11ax_ul_ofdma; 6119 6120 A_UINT32 ul_ofdma_rx_mcs[HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS]; 6121 A_UINT32 ul_ofdma_rx_gi[HTT_RX_PDEV_STATS_NUM_GI_COUNTERS][HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS]; 6122 A_UINT32 ul_ofdma_rx_nss[HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS]; 6123 A_UINT32 ul_ofdma_rx_bw[HTT_RX_PDEV_STATS_NUM_BW_COUNTERS]; 6124 A_UINT32 ul_ofdma_rx_stbc; 6125 A_UINT32 ul_ofdma_rx_ldpc; 6126 6127 /* 6128 * These are arrays to hold the number of PPDUs that we received per RU. 6129 * E.g. PPDUs (data or non data) received in RU26 will be incremented in 6130 * array offset 0 and similarly RU52 will be incremented in array offset 1 6131 */ 6132 A_UINT32 rx_ulofdma_data_ru_size_ppdu[HTT_RX_PDEV_STATS_NUM_RU_SIZE_160MHZ_CNTRS]; /* ppdu level */ 6133 A_UINT32 rx_ulofdma_non_data_ru_size_ppdu[HTT_RX_PDEV_STATS_NUM_RU_SIZE_160MHZ_CNTRS]; /* ppdu level */ 6134 6135 /* 6136 * These arrays hold Target RSSI (rx power the AP wants), 6137 * FD RSSI (rx power the AP sees) & Power headroom values of STAs 6138 * which can be identified by AIDs, during trigger based RX. 6139 * Array acts a circular buffer and holds values for last 5 STAs 6140 * in the same order as RX. 6141 */ 6142 /** 6143 * STA AID array for identifying which STA the 6144 * Target-RSSI / FD-RSSI / pwr headroom stats are for 6145 */ 6146 A_UINT32 uplink_sta_aid[HTT_RX_UL_MAX_UPLINK_RSSI_TRACK]; 6147 /** 6148 * Trig Target RSSI for STA AID in same index - UNIT(dBm) 6149 */ 6150 A_INT32 uplink_sta_target_rssi[HTT_RX_UL_MAX_UPLINK_RSSI_TRACK]; 6151 /** 6152 * Trig FD RSSI from STA AID in same index - UNIT(dBm) 6153 */ 6154 A_INT32 uplink_sta_fd_rssi[HTT_RX_UL_MAX_UPLINK_RSSI_TRACK]; 6155 /** 6156 * Trig power headroom for STA AID in same idx - UNIT(dB) 6157 */ 6158 A_UINT32 uplink_sta_power_headroom[HTT_RX_UL_MAX_UPLINK_RSSI_TRACK]; 6159 A_UINT32 reduced_ul_ofdma_rx_bw[HTT_RX_PDEV_STATS_NUM_REDUCED_CHAN_TYPES][HTT_RX_PDEV_STATS_NUM_BW_COUNTERS]; 6160 6161 /* 6162 * Number of HE UL OFDMA per-user responses containing only a QoS null in 6163 * response to basic trigger. Typically a data response is expected. 6164 */ 6165 A_UINT32 ul_ofdma_basic_trigger_rx_qos_null_only; 6166 } htt_stats_rx_pdev_ul_trig_stats_tlv; 6167 /* preserve old name alias for new name consistent with the tag name */ 6168 typedef htt_stats_rx_pdev_ul_trig_stats_tlv htt_rx_pdev_ul_trigger_stats_tlv; 6169 6170 /* STATS_TYPE : HTT_DBG_EXT_STATS_PDEV_UL_TRIG_STATS 6171 * TLV_TAGS: 6172 * - HTT_STATS_RX_PDEV_UL_TRIG_STATS_TAG 6173 * NOTE: 6174 * This structure is for documentation, and cannot be safely used directly. 6175 * Instead, use the constituent TLV structures to fill/parse. 6176 */ 6177 #ifdef ATH_TARGET 6178 typedef struct { 6179 htt_stats_rx_pdev_ul_trig_stats_tlv ul_trigger_tlv; 6180 } htt_rx_pdev_ul_trigger_stats_t; 6181 #endif /* ATH_TARGET */ 6182 6183 typedef struct { 6184 htt_tlv_hdr_t tlv_hdr; 6185 6186 /** 6187 * BIT [ 7 : 0] :- mac_id 6188 * BIT [31 : 8] :- reserved 6189 */ 6190 A_UINT32 mac_id__word; 6191 6192 A_UINT32 rx_11be_ul_ofdma; 6193 6194 A_UINT32 be_ul_ofdma_rx_mcs[HTT_RX_PDEV_STATS_NUM_BE_MCS_COUNTERS]; 6195 A_UINT32 be_ul_ofdma_rx_gi[HTT_RX_PDEV_STATS_NUM_GI_COUNTERS][HTT_RX_PDEV_STATS_NUM_BE_MCS_COUNTERS]; 6196 A_UINT32 be_ul_ofdma_rx_nss[HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS]; 6197 A_UINT32 be_ul_ofdma_rx_bw[HTT_RX_PDEV_STATS_NUM_BE_BW_COUNTERS]; 6198 A_UINT32 be_ul_ofdma_rx_stbc; 6199 A_UINT32 be_ul_ofdma_rx_ldpc; 6200 6201 /* 6202 * These are arrays to hold the number of PPDUs that we received per RU. 6203 * E.g. PPDUs (data or non data) received in RU26 will be incremented in 6204 * array offset 0 and similarly RU52 will be incremented in array offset 1 6205 */ 6206 /** PPDU level */ 6207 A_UINT32 be_rx_ulofdma_data_ru_size_ppdu[HTT_RX_PDEV_STATS_NUM_BE_RU_SIZE_COUNTERS]; 6208 /** PPDU level */ 6209 A_UINT32 be_rx_ulofdma_non_data_ru_size_ppdu[HTT_RX_PDEV_STATS_NUM_BE_RU_SIZE_COUNTERS]; 6210 6211 /* 6212 * These arrays hold Target RSSI (rx power the AP wants), 6213 * FD RSSI (rx power the AP sees) & Power headroom values of STAs 6214 * which can be identified by AIDs, during trigger based RX. 6215 * Array acts a circular buffer and holds values for last 5 STAs 6216 * in the same order as RX. 6217 */ 6218 /** 6219 * STA AID array for identifying which STA the 6220 * Target-RSSI / FD-RSSI / pwr headroom stats are for 6221 */ 6222 A_UINT32 be_uplink_sta_aid[HTT_RX_UL_MAX_UPLINK_RSSI_TRACK]; 6223 /** 6224 * Trig Target RSSI for STA AID in same index - UNIT(dBm) 6225 */ 6226 A_INT32 be_uplink_sta_target_rssi[HTT_RX_UL_MAX_UPLINK_RSSI_TRACK]; 6227 /** 6228 * Trig FD RSSI from STA AID in same index - UNIT(dBm) 6229 */ 6230 A_INT32 be_uplink_sta_fd_rssi[HTT_RX_UL_MAX_UPLINK_RSSI_TRACK]; 6231 /** 6232 * Trig power headroom for STA AID in same idx - UNIT(dB) 6233 */ 6234 A_UINT32 be_uplink_sta_power_headroom[HTT_RX_UL_MAX_UPLINK_RSSI_TRACK]; 6235 6236 /* 6237 * Number of EHT UL OFDMA per-user responses containing only a QoS null in 6238 * response to basic trigger. Typically a data response is expected. 6239 */ 6240 A_UINT32 be_ul_ofdma_basic_trigger_rx_qos_null_only; 6241 6242 /* UL MLO Queue Depth Sharing Stats */ 6243 A_UINT32 ul_mlo_send_qdepth_params_count; 6244 A_UINT32 ul_mlo_proc_qdepth_params_count; 6245 A_UINT32 ul_mlo_proc_accepted_qdepth_params_count; 6246 A_UINT32 ul_mlo_proc_discarded_qdepth_params_count; 6247 } htt_stats_rx_pdev_be_ul_trig_stats_tlv; 6248 /* preserve old name alias for new name consistent with the tag name */ 6249 typedef htt_stats_rx_pdev_be_ul_trig_stats_tlv 6250 htt_rx_pdev_be_ul_trigger_stats_tlv; 6251 6252 /* STATS_TYPE : HTT_DBG_EXT_STATS_PDEV_UL_TRIG_STATS 6253 * TLV_TAGS: 6254 * - HTT_STATS_RX_PDEV_BE_UL_TRIG_STATS_TAG 6255 * NOTE: 6256 * This structure is for documentation, and cannot be safely used directly. 6257 * Instead, use the constituent TLV structures to fill/parse. 6258 */ 6259 #ifdef ATH_TARGET 6260 typedef struct { 6261 htt_stats_rx_pdev_be_ul_trig_stats_tlv ul_trigger_tlv; 6262 } htt_rx_pdev_be_ul_trigger_stats_t; 6263 #endif /* ATH_TARGET */ 6264 6265 typedef struct { 6266 htt_tlv_hdr_t tlv_hdr; 6267 6268 A_UINT32 user_index; 6269 /** PPDU level */ 6270 A_UINT32 rx_ulofdma_non_data_ppdu; 6271 /** PPDU level */ 6272 A_UINT32 rx_ulofdma_data_ppdu; 6273 /** MPDU level */ 6274 A_UINT32 rx_ulofdma_mpdu_ok; 6275 /** MPDU level */ 6276 A_UINT32 rx_ulofdma_mpdu_fail; 6277 A_UINT32 rx_ulofdma_non_data_nusers; 6278 A_UINT32 rx_ulofdma_data_nusers; 6279 } htt_stats_rx_pdev_ul_ofdma_user_stats_tlv; 6280 /* preserve old name alias for new name consistent with the tag name */ 6281 typedef htt_stats_rx_pdev_ul_ofdma_user_stats_tlv 6282 htt_rx_pdev_ul_ofdma_user_stats_tlv; 6283 6284 typedef struct { 6285 htt_tlv_hdr_t tlv_hdr; 6286 6287 A_UINT32 user_index; 6288 /** PPDU level */ 6289 A_UINT32 be_rx_ulofdma_non_data_ppdu; 6290 /** PPDU level */ 6291 A_UINT32 be_rx_ulofdma_data_ppdu; 6292 /** MPDU level */ 6293 A_UINT32 be_rx_ulofdma_mpdu_ok; 6294 /** MPDU level */ 6295 A_UINT32 be_rx_ulofdma_mpdu_fail; 6296 A_UINT32 be_rx_ulofdma_non_data_nusers; 6297 A_UINT32 be_rx_ulofdma_data_nusers; 6298 } htt_stats_rx_pdev_be_ul_ofdma_user_stats_tlv; 6299 /* preserve old name alias for new name consistent with the tag name */ 6300 typedef htt_stats_rx_pdev_be_ul_ofdma_user_stats_tlv 6301 htt_rx_pdev_be_ul_ofdma_user_stats_tlv; 6302 6303 typedef struct { 6304 htt_tlv_hdr_t tlv_hdr; 6305 6306 A_UINT32 user_index; 6307 /** PPDU level */ 6308 A_UINT32 rx_ulmumimo_non_data_ppdu; 6309 /** PPDU level */ 6310 A_UINT32 rx_ulmumimo_data_ppdu; 6311 /** MPDU level */ 6312 A_UINT32 rx_ulmumimo_mpdu_ok; 6313 /** MPDU level */ 6314 A_UINT32 rx_ulmumimo_mpdu_fail; 6315 } htt_stats_rx_pdev_ul_mimo_user_stats_tlv; 6316 /* preserve old name alias for new name consistent with the tag name */ 6317 typedef htt_stats_rx_pdev_ul_mimo_user_stats_tlv 6318 htt_rx_pdev_ul_mimo_user_stats_tlv; 6319 6320 typedef struct { 6321 htt_tlv_hdr_t tlv_hdr; 6322 6323 A_UINT32 user_index; 6324 /** PPDU level */ 6325 A_UINT32 be_rx_ulmumimo_non_data_ppdu; 6326 /** PPDU level */ 6327 A_UINT32 be_rx_ulmumimo_data_ppdu; 6328 /** MPDU level */ 6329 A_UINT32 be_rx_ulmumimo_mpdu_ok; 6330 /** MPDU level */ 6331 A_UINT32 be_rx_ulmumimo_mpdu_fail; 6332 } htt_stats_rx_pdev_be_ul_mimo_user_stats_tlv; 6333 /* preserve old name alias for new name consistent with the tag name */ 6334 typedef htt_stats_rx_pdev_be_ul_mimo_user_stats_tlv 6335 htt_rx_pdev_be_ul_mimo_user_stats_tlv; 6336 6337 /* == RX PDEV/SOC STATS == */ 6338 6339 typedef struct { 6340 htt_tlv_hdr_t tlv_hdr; 6341 6342 /** 6343 * BIT [7:0] :- mac_id 6344 * BIT [31:8] :- reserved 6345 * 6346 * Refer to HTT_STATS_CMN_MAC_ID_GET/SET macros. 6347 */ 6348 A_UINT32 mac_id__word; 6349 6350 /** Number of times UL MUMIMO RX packets received */ 6351 A_UINT32 rx_11ax_ul_mumimo; 6352 6353 /** 11AX HE UL MU-MIMO RX TB PPDU MCS stats */ 6354 A_UINT32 ul_mumimo_rx_mcs[HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS]; 6355 /** 6356 * 11AX HE UL MU-MIMO RX GI & LTF stats. 6357 * Index 0 indicates 1xLTF + 1.6 msec GI 6358 * Index 1 indicates 2xLTF + 1.6 msec GI 6359 * Index 2 indicates 4xLTF + 3.2 msec GI 6360 */ 6361 A_UINT32 ul_mumimo_rx_gi[HTT_RX_PDEV_STATS_NUM_GI_COUNTERS][HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS]; 6362 /** 6363 * 11AX HE UL MU-MIMO RX TB PPDU NSS stats 6364 * (Increments the individual user NSS in the UL MU MIMO PPDU received) 6365 */ 6366 A_UINT32 ul_mumimo_rx_nss[HTT_RX_PDEV_STATS_ULMUMIMO_NUM_SPATIAL_STREAMS]; 6367 /** 11AX HE UL MU-MIMO RX TB PPDU BW stats */ 6368 A_UINT32 ul_mumimo_rx_bw[HTT_RX_PDEV_STATS_NUM_BW_COUNTERS]; 6369 /** Number of times UL MUMIMO TB PPDUs received with STBC */ 6370 A_UINT32 ul_mumimo_rx_stbc; 6371 /** Number of times UL MUMIMO TB PPDUs received with LDPC */ 6372 A_UINT32 ul_mumimo_rx_ldpc; 6373 6374 /* Stats for MCS 12/13 */ 6375 A_UINT32 ul_mumimo_rx_mcs_ext[HTT_RX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS]; 6376 A_UINT32 ul_mumimo_rx_gi_ext[HTT_RX_PDEV_STATS_NUM_GI_COUNTERS][HTT_RX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS]; 6377 6378 /** RSSI in dBm for Rx TB PPDUs */ 6379 A_INT8 rx_ul_mumimo_chain_rssi_in_dbm[HTT_RX_PDEV_STATS_ULMUMIMO_NUM_SPATIAL_STREAMS][HTT_RX_PDEV_STATS_TOTAL_BW_COUNTERS]; 6380 /** Target RSSI programmed in UL MUMIMO triggers (units dBm) */ 6381 A_INT8 rx_ul_mumimo_target_rssi[HTT_TX_PDEV_STATS_NUM_UL_MUMIMO_USER_STATS][HTT_RX_PDEV_STATS_NUM_BW_COUNTERS]; 6382 /** FD RSSI measured for Rx UL TB PPDUs (units dBm) */ 6383 A_INT8 rx_ul_mumimo_fd_rssi[HTT_TX_PDEV_STATS_NUM_UL_MUMIMO_USER_STATS][HTT_RX_PDEV_STATS_ULMUMIMO_NUM_SPATIAL_STREAMS]; 6384 /** Average pilot EVM measued for RX UL TB PPDU */ 6385 A_INT8 rx_ulmumimo_pilot_evm_dB_mean[HTT_TX_PDEV_STATS_NUM_UL_MUMIMO_USER_STATS][HTT_RX_PDEV_STATS_ULMUMIMO_NUM_SPATIAL_STREAMS]; 6386 A_UINT32 reduced_ul_mumimo_rx_bw[HTT_RX_PDEV_STATS_NUM_REDUCED_CHAN_TYPES][HTT_RX_PDEV_STATS_NUM_BW_COUNTERS]; 6387 6388 /* 6389 * Number of HE UL MU-MIMO per-user responses containing only a QoS null in 6390 * response to basic trigger. Typically a data response is expected. 6391 */ 6392 A_UINT32 ul_mumimo_basic_trigger_rx_qos_null_only; 6393 } htt_stats_rx_pdev_ul_mumimo_trig_stats_tlv; 6394 /* preserve old name alias for new name consistent with the tag name */ 6395 typedef htt_stats_rx_pdev_ul_mumimo_trig_stats_tlv 6396 htt_rx_pdev_ul_mumimo_trig_stats_tlv; 6397 6398 typedef struct { 6399 htt_tlv_hdr_t tlv_hdr; 6400 6401 /** 6402 * BIT [7:0] :- mac_id 6403 * BIT [31:8] :- reserved 6404 * 6405 * Refer to HTT_STATS_CMN_MAC_ID_GET/SET macros. 6406 */ 6407 A_UINT32 mac_id__word; 6408 6409 /** Number of times UL MUMIMO RX packets received */ 6410 A_UINT32 rx_11be_ul_mumimo; 6411 6412 /** 11BE EHT UL MU-MIMO RX TB PPDU MCS stats */ 6413 A_UINT32 be_ul_mumimo_rx_mcs[HTT_RX_PDEV_STATS_NUM_BE_MCS_COUNTERS]; 6414 /** 6415 * 11BE EHT UL MU-MIMO RX GI & LTF stats. 6416 * Index 0 indicates 1xLTF + 1.6 msec GI 6417 * Index 1 indicates 2xLTF + 1.6 msec GI 6418 * Index 2 indicates 4xLTF + 3.2 msec GI 6419 */ 6420 A_UINT32 be_ul_mumimo_rx_gi[HTT_RX_PDEV_STATS_NUM_GI_COUNTERS][HTT_RX_PDEV_STATS_NUM_BE_MCS_COUNTERS]; 6421 /** 6422 * 11BE EHT UL MU-MIMO RX TB PPDU NSS stats 6423 * (Increments the individual user NSS in the UL MU MIMO PPDU received) 6424 */ 6425 A_UINT32 be_ul_mumimo_rx_nss[HTT_RX_PDEV_STATS_ULMUMIMO_NUM_SPATIAL_STREAMS]; 6426 /** 11BE EHT UL MU-MIMO RX TB PPDU BW stats */ 6427 A_UINT32 be_ul_mumimo_rx_bw[HTT_RX_PDEV_STATS_NUM_BE_BW_COUNTERS]; 6428 /** Number of times UL MUMIMO TB PPDUs received with STBC */ 6429 A_UINT32 be_ul_mumimo_rx_stbc; 6430 /** Number of times UL MUMIMO TB PPDUs received with LDPC */ 6431 A_UINT32 be_ul_mumimo_rx_ldpc; 6432 6433 /** RSSI in dBm for Rx TB PPDUs */ 6434 A_INT8 be_rx_ul_mumimo_chain_rssi_in_dbm[HTT_RX_PDEV_STATS_ULMUMIMO_NUM_SPATIAL_STREAMS][HTT_RX_PDEV_STATS_NUM_BE_BW_COUNTERS]; 6435 /** Target RSSI programmed in UL MUMIMO triggers (units dBm) */ 6436 A_INT8 be_rx_ul_mumimo_target_rssi[HTT_RX_PDEV_MAX_ULMUMIMO_NUM_USER][HTT_RX_PDEV_STATS_NUM_BE_BW_COUNTERS]; 6437 /** FD RSSI measured for Rx UL TB PPDUs (units dBm) */ 6438 A_INT8 be_rx_ul_mumimo_fd_rssi[HTT_RX_PDEV_MAX_ULMUMIMO_NUM_USER][HTT_RX_PDEV_STATS_ULMUMIMO_NUM_SPATIAL_STREAMS]; 6439 /** Average pilot EVM measued for RX UL TB PPDU */ 6440 A_INT8 be_rx_ulmumimo_pilot_evm_dB_mean[HTT_RX_PDEV_MAX_ULMUMIMO_NUM_USER][HTT_RX_PDEV_STATS_ULMUMIMO_NUM_SPATIAL_STREAMS]; 6441 /** Number of times UL MUMIMO TB PPDUs received in a punctured mode */ 6442 A_UINT32 rx_ul_mumimo_punctured_mode[HTT_RX_PDEV_STATS_NUM_PUNCTURED_MODE_COUNTERS]; 6443 6444 /* 6445 * Number of EHT UL MU-MIMO per-user responses containing only a QoS null 6446 * in response to basic trigger. Typically a data response is expected. 6447 */ 6448 A_UINT32 be_ul_mumimo_basic_trigger_rx_qos_null_only; 6449 } htt_stats_rx_pdev_ul_mumimo_trig_be_stats_tlv; 6450 /* preserve old name alias for new name consistent with the tag name */ 6451 typedef htt_stats_rx_pdev_ul_mumimo_trig_be_stats_tlv 6452 htt_rx_pdev_ul_mumimo_trig_be_stats_tlv; 6453 6454 /* STATS_TYPE : HTT_DBG_EXT_STATS_PDEV_UL_MUMIMO_TRIG_STATS 6455 * TLV_TAGS: 6456 * - HTT_STATS_RX_PDEV_UL_MUMIMO_TRIG_STATS_TAG 6457 * - HTT_STATS_RX_PDEV_UL_MUMIMO_TRIG_BE_STATS_TAG 6458 */ 6459 #ifdef ATH_TARGET 6460 typedef struct { 6461 htt_stats_rx_pdev_ul_mumimo_trig_stats_tlv ul_mumimo_trig_tlv; 6462 htt_stats_rx_pdev_ul_mumimo_trig_be_stats_tlv ul_mumimo_trig_be_tlv; 6463 } htt_rx_pdev_ul_mumimo_trig_stats_t; 6464 #endif /* ATH_TARGET */ 6465 6466 typedef struct { 6467 htt_tlv_hdr_t tlv_hdr; 6468 /** Num Packets received on REO FW ring */ 6469 A_UINT32 fw_reo_ring_data_msdu; 6470 /** Num bc/mc packets indicated from fw to host */ 6471 A_UINT32 fw_to_host_data_msdu_bcmc; 6472 /** Num unicast packets indicated from fw to host */ 6473 A_UINT32 fw_to_host_data_msdu_uc; 6474 /** Num remote buf recycle from offload */ 6475 A_UINT32 ofld_remote_data_buf_recycle_cnt; 6476 /** Num remote free buf given to offload */ 6477 A_UINT32 ofld_remote_free_buf_indication_cnt; 6478 6479 /** Num unicast packets from local path indicated to host */ 6480 A_UINT32 ofld_buf_to_host_data_msdu_uc; 6481 /** Num unicast packets from REO indicated to host */ 6482 A_UINT32 reo_fw_ring_to_host_data_msdu_uc; 6483 6484 /** Num Packets received from WBM SW1 ring */ 6485 A_UINT32 wbm_sw_ring_reap; 6486 /** Num packets from WBM forwarded from fw to host via WBM */ 6487 A_UINT32 wbm_forward_to_host_cnt; 6488 /** Num packets from WBM recycled to target refill ring */ 6489 A_UINT32 wbm_target_recycle_cnt; 6490 6491 /** 6492 * Total Num of recycled to refill ring, 6493 * including packets from WBM and REO 6494 */ 6495 A_UINT32 target_refill_ring_recycle_cnt; 6496 } htt_stats_rx_soc_fw_stats_tlv; 6497 /* preserve old name alias for new name consistent with the tag name */ 6498 typedef htt_stats_rx_soc_fw_stats_tlv htt_rx_soc_fw_stats_tlv; 6499 6500 #define HTT_RX_SOC_FW_REFILL_RING_EMPTY_TLV_SZ(_num_elems) (sizeof(A_UINT32) * (_num_elems)) 6501 6502 /* NOTE: Variable length TLV, use length spec to infer array size */ 6503 typedef struct { 6504 htt_tlv_hdr_t tlv_hdr; 6505 /** refill_ring_empty_cnt: 6506 * Num ring empty encountered, 6507 * HTT_RX_STATS_REFILL_MAX_RING 6508 */ 6509 HTT_STATS_VAR_LEN_ARRAY1(A_UINT32, refill_ring_empty_cnt); 6510 } htt_stats_rx_soc_fw_refill_ring_empty_tlv; 6511 /* preserve old name alias for new name consistent with the tag name */ 6512 typedef htt_stats_rx_soc_fw_refill_ring_empty_tlv 6513 htt_rx_soc_fw_refill_ring_empty_tlv_v; 6514 6515 #define HTT_RX_SOC_FW_REFILL_RING_EMPTY_TLV_SZ(_num_elems) (sizeof(A_UINT32) * (_num_elems)) 6516 6517 /* NOTE: Variable length TLV, use length spec to infer array size */ 6518 typedef struct { 6519 htt_tlv_hdr_t tlv_hdr; 6520 /** refill_ring_num_refill: 6521 * Num total buf refilled from refill ring, 6522 * HTT_RX_STATS_REFILL_MAX_RING 6523 */ 6524 HTT_STATS_VAR_LEN_ARRAY1(A_UINT32, refill_ring_num_refill); 6525 } htt_stats_rx_soc_fw_refill_ring_num_refill_tlv; 6526 /* preserve old name alias for new name consistent with the tag name */ 6527 typedef htt_stats_rx_soc_fw_refill_ring_num_refill_tlv 6528 htt_rx_soc_fw_refill_ring_num_refill_tlv_v; 6529 6530 /* RXDMA error code from WBM released packets */ 6531 typedef enum { 6532 HTT_RX_RXDMA_OVERFLOW_ERR = 0, 6533 HTT_RX_RXDMA_MPDU_LENGTH_ERR = 1, 6534 HTT_RX_RXDMA_FCS_ERR = 2, 6535 HTT_RX_RXDMA_DECRYPT_ERR = 3, 6536 HTT_RX_RXDMA_TKIP_MIC_ERR = 4, 6537 HTT_RX_RXDMA_UNECRYPTED_ERR = 5, 6538 HTT_RX_RXDMA_MSDU_LEN_ERR = 6, 6539 HTT_RX_RXDMA_MSDU_LIMIT_ERR = 7, 6540 HTT_RX_RXDMA_WIFI_PARSE_ERR = 8, 6541 HTT_RX_RXDMA_AMSDU_PARSE_ERR = 9, 6542 HTT_RX_RXDMA_SA_TIMEOUT_ERR = 10, 6543 HTT_RX_RXDMA_DA_TIMEOUT_ERR = 11, 6544 HTT_RX_RXDMA_FLOW_TIMEOUT_ERR = 12, 6545 HTT_RX_RXDMA_FLUSH_REQUEST = 13, 6546 HTT_RX_RXDMA_ERR_CODE_RVSD0 = 14, 6547 HTT_RX_RXDMA_ERR_CODE_RVSD1 = 15, 6548 6549 /* 6550 * This MAX_ERR_CODE should not be used in any host/target messages, 6551 * so that even though it is defined within a host/target interface 6552 * definition header file, it isn't actually part of the host/target 6553 * interface, and thus can be modified. 6554 */ 6555 HTT_RX_RXDMA_MAX_ERR_CODE 6556 } htt_rx_rxdma_error_code_enum; 6557 6558 /* NOTE: Variable length TLV, use length spec to infer array size */ 6559 typedef struct { 6560 htt_tlv_hdr_t tlv_hdr; 6561 6562 /** NOTE: 6563 * The mapping of RXDMA error types to rxdma_err array elements is HW dependent. 6564 * It is expected but not required that the target will provide a rxdma_err element 6565 * for each of the htt_rx_rxdma_error_code_enum values, up to but not including 6566 * MAX_ERR_CODE. The host should ignore any array elements whose 6567 * indices are >= the MAX_ERR_CODE value the host was compiled with. 6568 * 6569 * HTT_RX_RXDMA_MAX_ERR_CODE 6570 */ 6571 HTT_STATS_VAR_LEN_ARRAY1(A_UINT32, rxdma_err); 6572 } htt_stats_rx_refill_rxdma_err_tlv; 6573 /* preserve old name alias for new name consistent with the tag name */ 6574 typedef htt_stats_rx_refill_rxdma_err_tlv 6575 htt_rx_soc_fw_refill_ring_num_rxdma_err_tlv_v; 6576 6577 /* REO error code from WBM released packets */ 6578 typedef enum { 6579 HTT_RX_REO_QUEUE_DESC_ADDR_ZERO = 0, 6580 HTT_RX_REO_QUEUE_DESC_NOT_VALID = 1, 6581 HTT_RX_AMPDU_IN_NON_BA = 2, 6582 HTT_RX_NON_BA_DUPLICATE = 3, 6583 HTT_RX_BA_DUPLICATE = 4, 6584 HTT_RX_REGULAR_FRAME_2K_JUMP = 5, 6585 HTT_RX_BAR_FRAME_2K_JUMP = 6, 6586 HTT_RX_REGULAR_FRAME_OOR = 7, 6587 HTT_RX_BAR_FRAME_OOR = 8, 6588 HTT_RX_BAR_FRAME_NO_BA_SESSION = 9, 6589 HTT_RX_BAR_FRAME_SN_EQUALS_SSN = 10, 6590 HTT_RX_PN_CHECK_FAILED = 11, 6591 HTT_RX_2K_ERROR_HANDLING_FLAG_SET = 12, 6592 HTT_RX_PN_ERROR_HANDLING_FLAG_SET = 13, 6593 HTT_RX_QUEUE_DESCRIPTOR_BLOCKED_SET = 14, 6594 HTT_RX_REO_ERR_CODE_RVSD = 15, 6595 6596 /* 6597 * This MAX_ERR_CODE should not be used in any host/target messages, 6598 * so that even though it is defined within a host/target interface 6599 * definition header file, it isn't actually part of the host/target 6600 * interface, and thus can be modified. 6601 */ 6602 HTT_RX_REO_MAX_ERR_CODE 6603 } htt_rx_reo_error_code_enum; 6604 6605 /* NOTE: Variable length TLV, use length spec to infer array size */ 6606 typedef struct { 6607 htt_tlv_hdr_t tlv_hdr; 6608 6609 /** NOTE: 6610 * The mapping of REO error types to reo_err array elements is HW dependent. 6611 * It is expected but not required that the target will provide a rxdma_err element 6612 * for each of the htt_rx_reo_error_code_enum values, up to but not including 6613 * MAX_ERR_CODE. The host should ignore any array elements whose 6614 * indices are >= the MAX_ERR_CODE value the host was compiled with. 6615 * 6616 * HTT_RX_REO_MAX_ERR_CODE 6617 */ 6618 HTT_STATS_VAR_LEN_ARRAY1(A_UINT32, reo_err); 6619 } htt_stats_rx_refill_reo_err_tlv; 6620 /* preserve old name alias for new name consistent with the tag name */ 6621 typedef htt_stats_rx_refill_reo_err_tlv 6622 htt_rx_soc_fw_refill_ring_num_reo_err_tlv_v; 6623 6624 /* NOTE: 6625 * This structure is for documentation, and cannot be safely used directly. 6626 * Instead, use the constituent TLV structures to fill/parse. 6627 */ 6628 #ifdef ATH_TARGET 6629 typedef struct { 6630 htt_stats_rx_soc_fw_stats_tlv fw_tlv; 6631 htt_stats_rx_soc_fw_refill_ring_empty_tlv fw_refill_ring_empty_tlv; 6632 htt_stats_rx_soc_fw_refill_ring_num_refill_tlv 6633 fw_refill_ring_num_refill_tlv; 6634 htt_stats_rx_refill_rxdma_err_tlv fw_refill_ring_num_rxdma_err_tlv; 6635 htt_stats_rx_refill_reo_err_tlv fw_refill_ring_num_reo_err_tlv; 6636 } htt_rx_soc_stats_t; 6637 #endif /* ATH_TARGET */ 6638 6639 /* == RX PDEV STATS == */ 6640 #define HTT_RX_PDEV_FW_STATS_MAC_ID_M 0x000000ff 6641 #define HTT_RX_PDEV_FW_STATS_MAC_ID_S 0 6642 6643 #define HTT_RX_PDEV_FW_STATS_MAC_ID_GET(_var) \ 6644 (((_var) & HTT_RX_PDEV_FW_STATS_MAC_ID_M) >> \ 6645 HTT_RX_PDEV_FW_STATS_MAC_ID_S) 6646 6647 #define HTT_RX_PDEV_FW_STATS_MAC_ID_SET(_var, _val) \ 6648 do { \ 6649 HTT_CHECK_SET_VAL(HTT_RX_PDEV_FW_STATS_MAC_ID, _val); \ 6650 ((_var) |= ((_val) << HTT_RX_PDEV_FW_STATS_MAC_ID_S)); \ 6651 } while (0) 6652 6653 typedef struct { 6654 htt_tlv_hdr_t tlv_hdr; 6655 6656 /** 6657 * BIT [ 7 : 0] :- mac_id 6658 * BIT [31 : 8] :- reserved 6659 */ 6660 A_UINT32 mac_id__word; 6661 /** Num PPDU status processed from HW */ 6662 A_UINT32 ppdu_recvd; 6663 /** Num MPDU across PPDUs with FCS ok */ 6664 A_UINT32 mpdu_cnt_fcs_ok; 6665 /** Num MPDU across PPDUs with FCS err */ 6666 A_UINT32 mpdu_cnt_fcs_err; 6667 /** Num MSDU across PPDUs */ 6668 A_UINT32 tcp_msdu_cnt; 6669 /** Num MSDU across PPDUs */ 6670 A_UINT32 tcp_ack_msdu_cnt; 6671 /** Num MSDU across PPDUs */ 6672 A_UINT32 udp_msdu_cnt; 6673 /** Num MSDU across PPDUs */ 6674 A_UINT32 other_msdu_cnt; 6675 /** Num MPDU on FW ring indicated */ 6676 A_UINT32 fw_ring_mpdu_ind; 6677 /** Num MGMT MPDU given to protocol */ 6678 A_UINT32 fw_ring_mgmt_subtype[HTT_STATS_SUBTYPE_MAX]; 6679 /** Num ctrl MPDU given to protocol */ 6680 A_UINT32 fw_ring_ctrl_subtype[HTT_STATS_SUBTYPE_MAX]; 6681 /** Num mcast data packet received */ 6682 A_UINT32 fw_ring_mcast_data_msdu; 6683 /** Num broadcast data packet received */ 6684 A_UINT32 fw_ring_bcast_data_msdu; 6685 /** Num unicast data packet received */ 6686 A_UINT32 fw_ring_ucast_data_msdu; 6687 /** Num null data packet received */ 6688 A_UINT32 fw_ring_null_data_msdu; 6689 /** Num MPDU on FW ring dropped */ 6690 A_UINT32 fw_ring_mpdu_drop; 6691 6692 /** Num buf indication to offload */ 6693 A_UINT32 ofld_local_data_ind_cnt; 6694 /** Num buf recycle from offload */ 6695 A_UINT32 ofld_local_data_buf_recycle_cnt; 6696 /** Num buf indication to data_rx */ 6697 A_UINT32 drx_local_data_ind_cnt; 6698 /** Num buf recycle from data_rx */ 6699 A_UINT32 drx_local_data_buf_recycle_cnt; 6700 /** Num buf indication to protocol */ 6701 A_UINT32 local_nondata_ind_cnt; 6702 /** Num buf recycle from protocol */ 6703 A_UINT32 local_nondata_buf_recycle_cnt; 6704 6705 /** Num buf fed */ 6706 A_UINT32 fw_status_buf_ring_refill_cnt; 6707 /** Num ring empty encountered */ 6708 A_UINT32 fw_status_buf_ring_empty_cnt; 6709 /** Num buf fed */ 6710 A_UINT32 fw_pkt_buf_ring_refill_cnt; 6711 /** Num ring empty encountered */ 6712 A_UINT32 fw_pkt_buf_ring_empty_cnt; 6713 /** Num buf fed */ 6714 A_UINT32 fw_link_buf_ring_refill_cnt; 6715 /** Num ring empty encountered */ 6716 A_UINT32 fw_link_buf_ring_empty_cnt; 6717 6718 /** Num buf fed */ 6719 A_UINT32 host_pkt_buf_ring_refill_cnt; 6720 /** Num ring empty encountered */ 6721 A_UINT32 host_pkt_buf_ring_empty_cnt; 6722 /** Num buf fed */ 6723 A_UINT32 mon_pkt_buf_ring_refill_cnt; 6724 /** Num ring empty encountered */ 6725 A_UINT32 mon_pkt_buf_ring_empty_cnt; 6726 /** Num buf fed */ 6727 A_UINT32 mon_status_buf_ring_refill_cnt; 6728 /** Num ring empty encountered */ 6729 A_UINT32 mon_status_buf_ring_empty_cnt; 6730 /** Num buf fed */ 6731 A_UINT32 mon_desc_buf_ring_refill_cnt; 6732 /** Num ring empty encountered */ 6733 A_UINT32 mon_desc_buf_ring_empty_cnt; 6734 /** Num buf fed */ 6735 A_UINT32 mon_dest_ring_update_cnt; 6736 /** Num ring full encountered */ 6737 A_UINT32 mon_dest_ring_full_cnt; 6738 6739 /** Num rx suspend is attempted */ 6740 A_UINT32 rx_suspend_cnt; 6741 /** Num rx suspend failed */ 6742 A_UINT32 rx_suspend_fail_cnt; 6743 /** Num rx resume attempted */ 6744 A_UINT32 rx_resume_cnt; 6745 /** Num rx resume failed */ 6746 A_UINT32 rx_resume_fail_cnt; 6747 /** Num rx ring switch */ 6748 A_UINT32 rx_ring_switch_cnt; 6749 /** Num rx ring restore */ 6750 A_UINT32 rx_ring_restore_cnt; 6751 /** Num rx flush issued */ 6752 A_UINT32 rx_flush_cnt; 6753 /** Num rx recovery */ 6754 A_UINT32 rx_recovery_reset_cnt; 6755 } htt_stats_rx_pdev_fw_stats_tlv; 6756 /* preserve old name alias for new name consistent with the tag name */ 6757 typedef htt_stats_rx_pdev_fw_stats_tlv htt_rx_pdev_fw_stats_tlv; 6758 6759 typedef struct { 6760 htt_tlv_hdr_t tlv_hdr; 6761 /** peer mac address */ 6762 htt_mac_addr peer_mac_addr; 6763 /** Num of tx mgmt frames with subtype on peer level */ 6764 A_UINT32 peer_tx_mgmt_subtype[HTT_STATS_SUBTYPE_MAX]; 6765 /** Num of rx mgmt frames with subtype on peer level */ 6766 A_UINT32 peer_rx_mgmt_subtype[HTT_STATS_SUBTYPE_MAX]; 6767 } htt_stats_peer_ctrl_path_txrx_stats_tlv; 6768 /* preserve old name alias for new name consistent with the tag name */ 6769 typedef htt_stats_peer_ctrl_path_txrx_stats_tlv 6770 htt_peer_ctrl_path_txrx_stats_tlv; 6771 6772 #define HTT_STATS_PHY_ERR_MAX 43 6773 6774 typedef struct { 6775 htt_tlv_hdr_t tlv_hdr; 6776 6777 /** 6778 * BIT [ 7 : 0] :- mac_id 6779 * BIT [31 : 8] :- reserved 6780 */ 6781 A_UINT32 mac_id__word; 6782 /** Num of phy err */ 6783 A_UINT32 total_phy_err_cnt; 6784 /** Counts of different types of phy errs 6785 * The mapping of PHY error types to phy_err array elements is HW dependent. 6786 * The only currently-supported mapping is shown below: 6787 * 6788 * 0 phyrx_err_phy_off Reception aborted due to receiving a PHY_OFF TLV 6789 * 1 phyrx_err_synth_off 6790 * 2 phyrx_err_ofdma_timing 6791 * 3 phyrx_err_ofdma_signal_parity 6792 * 4 phyrx_err_ofdma_rate_illegal 6793 * 5 phyrx_err_ofdma_length_illegal 6794 * 6 phyrx_err_ofdma_restart 6795 * 7 phyrx_err_ofdma_service 6796 * 8 phyrx_err_ppdu_ofdma_power_drop 6797 * 9 phyrx_err_cck_blokker 6798 * 10 phyrx_err_cck_timing 6799 * 11 phyrx_err_cck_header_crc 6800 * 12 phyrx_err_cck_rate_illegal 6801 * 13 phyrx_err_cck_length_illegal 6802 * 14 phyrx_err_cck_restart 6803 * 15 phyrx_err_cck_service 6804 * 16 phyrx_err_cck_power_drop 6805 * 17 phyrx_err_ht_crc_err 6806 * 18 phyrx_err_ht_length_illegal 6807 * 19 phyrx_err_ht_rate_illegal 6808 * 20 phyrx_err_ht_zlf 6809 * 21 phyrx_err_false_radar_ext 6810 * 22 phyrx_err_green_field 6811 * 23 phyrx_err_bw_gt_dyn_bw 6812 * 24 phyrx_err_leg_ht_mismatch 6813 * 25 phyrx_err_vht_crc_error 6814 * 26 phyrx_err_vht_siga_unsupported 6815 * 27 phyrx_err_vht_lsig_len_invalid 6816 * 28 phyrx_err_vht_ndp_or_zlf 6817 * 29 phyrx_err_vht_nsym_lt_zero 6818 * 30 phyrx_err_vht_rx_extra_symbol_mismatch 6819 * 31 phyrx_err_vht_rx_skip_group_id0 6820 * 32 phyrx_err_vht_rx_skip_group_id1to62 6821 * 33 phyrx_err_vht_rx_skip_group_id63 6822 * 34 phyrx_err_ofdm_ldpc_decoder_disabled 6823 * 35 phyrx_err_defer_nap 6824 * 36 phyrx_err_fdomain_timeout 6825 * 37 phyrx_err_lsig_rel_check 6826 * 38 phyrx_err_bt_collision 6827 * 39 phyrx_err_unsupported_mu_feedback 6828 * 40 phyrx_err_ppdu_tx_interrupt_rx 6829 * 41 phyrx_err_unsupported_cbf 6830 * 42 phyrx_err_other 6831 */ 6832 A_UINT32 phy_err[HTT_STATS_PHY_ERR_MAX]; 6833 } htt_stats_rx_pdev_fw_stats_phy_err_tlv; 6834 /* preserve old name alias for new name consistent with the tag name */ 6835 typedef htt_stats_rx_pdev_fw_stats_phy_err_tlv htt_rx_pdev_fw_stats_phy_err_tlv; 6836 6837 #define HTT_RX_PDEV_FW_RING_MPDU_ERR_TLV_SZ(_num_elems) (sizeof(A_UINT32) * (_num_elems)) 6838 6839 /* NOTE: Variable length TLV, use length spec to infer array size */ 6840 typedef struct { 6841 htt_tlv_hdr_t tlv_hdr; 6842 /** fw_ring_mpdu_err: 6843 * Num error MPDU for each RxDMA error type, 6844 * HTT_RX_STATS_RXDMA_MAX_ERR 6845 */ 6846 HTT_STATS_VAR_LEN_ARRAY1(A_UINT32, fw_ring_mpdu_err); 6847 } htt_stats_rx_pdev_fw_ring_mpdu_err_tlv; 6848 /* preserve old name alias for new name consistent with the tag name */ 6849 typedef htt_stats_rx_pdev_fw_ring_mpdu_err_tlv 6850 htt_rx_pdev_fw_ring_mpdu_err_tlv_v; 6851 6852 #define HTT_RX_PDEV_FW_MPDU_DROP_TLV_SZ(_num_elems) (sizeof(A_UINT32) * (_num_elems)) 6853 6854 /* NOTE: Variable length TLV, use length spec to infer array size */ 6855 typedef struct { 6856 htt_tlv_hdr_t tlv_hdr; 6857 /** fw_mpdu_drop: 6858 * Num MPDU dropped, 6859 * HTT_RX_STATS_FW_DROP_REASON_MAX 6860 */ 6861 HTT_STATS_VAR_LEN_ARRAY1(A_UINT32, fw_mpdu_drop); 6862 } htt_stats_rx_pdev_fw_mpdu_drop_tlv; 6863 /* preserve old name alias for new name consistent with the tag name */ 6864 typedef htt_stats_rx_pdev_fw_mpdu_drop_tlv htt_rx_pdev_fw_mpdu_drop_tlv_v; 6865 6866 /* STATS_TYPE : HTT_DBG_EXT_STATS_PDEV_RX 6867 * TLV_TAGS: 6868 * - HTT_STATS_RX_SOC_FW_STATS_TAG (head TLV in soc_stats) 6869 * - HTT_STATS_RX_SOC_FW_REFILL_RING_EMPTY_TAG (inside soc_stats) 6870 * - HTT_STATS_RX_SOC_FW_REFILL_RING_NUM_REFILL_TAG (inside soc_stats) 6871 * - HTT_STATS_RX_PDEV_FW_STATS_TAG 6872 * - HTT_STATS_RX_PDEV_FW_RING_MPDU_ERR_TAG 6873 * - HTT_STATS_RX_PDEV_FW_MPDU_DROP_TAG 6874 */ 6875 /* NOTE: 6876 * This structure is for documentation, and cannot be safely used directly. 6877 * Instead, use the constituent TLV structures to fill/parse. 6878 */ 6879 #ifdef ATH_TARGET 6880 typedef struct { 6881 htt_rx_soc_stats_t soc_stats; 6882 htt_stats_rx_pdev_fw_stats_tlv fw_stats_tlv; 6883 htt_stats_rx_pdev_fw_ring_mpdu_err_tlv fw_ring_mpdu_err_tlv; 6884 htt_stats_rx_pdev_fw_mpdu_drop_tlv fw_ring_mpdu_drop; 6885 htt_stats_rx_pdev_fw_stats_phy_err_tlv fw_stats_phy_err_tlv; 6886 } htt_rx_pdev_stats_t; 6887 #endif /* ATH_TARGET */ 6888 6889 /* STATS_TYPE : HTT_DBG_EXT_PEER_CTRL_PATH_TXRX_STATS 6890 * TLV_TAGS: 6891 * - HTT_STATS_PEER_CTRL_PATH_TXRX_STATS_TAG 6892 * 6893 */ 6894 #ifdef ATH_TARGET 6895 typedef struct { 6896 htt_stats_peer_ctrl_path_txrx_stats_tlv peer_ctrl_path_txrx_stats_tlv; 6897 } htt_ctrl_path_txrx_stats_t; 6898 #endif /* ATH_TARGET */ 6899 6900 #define HTT_PDEV_CCA_STATS_TX_FRAME_INFO_PRESENT (0x1) 6901 #define HTT_PDEV_CCA_STATS_RX_FRAME_INFO_PRESENT (0x2) 6902 #define HTT_PDEV_CCA_STATS_RX_CLEAR_INFO_PRESENT (0x4) 6903 #define HTT_PDEV_CCA_STATS_MY_RX_FRAME_INFO_PRESENT (0x8) 6904 #define HTT_PDEV_CCA_STATS_USEC_CNT_INFO_PRESENT (0x10) 6905 #define HTT_PDEV_CCA_STATS_MED_RX_IDLE_INFO_PRESENT (0x20) 6906 #define HTT_PDEV_CCA_STATS_MED_TX_IDLE_GLOBAL_INFO_PRESENT (0x40) 6907 #define HTT_PDEV_CCA_STATS_CCA_OBBS_USEC_INFO_PRESENT (0x80) 6908 6909 typedef struct { 6910 htt_tlv_hdr_t tlv_hdr; 6911 6912 /* Below values are obtained from the HW Cycles counter registers */ 6913 A_UINT32 tx_frame_usec; 6914 A_UINT32 rx_frame_usec; 6915 A_UINT32 rx_clear_usec; 6916 A_UINT32 my_rx_frame_usec; 6917 A_UINT32 usec_cnt; 6918 A_UINT32 med_rx_idle_usec; 6919 A_UINT32 med_tx_idle_global_usec; 6920 A_UINT32 cca_obss_usec; 6921 A_UINT32 pre_rx_frame_usec; 6922 } htt_stats_pdev_cca_counters_tlv; 6923 /* preserve old name alias for new name consistent with the tag name */ 6924 typedef htt_stats_pdev_cca_counters_tlv htt_pdev_stats_cca_counters_tlv; 6925 6926 /* NOTE: THIS htt_pdev_cca_stats_hist_tlv STRUCTURE IS DEPRECATED, 6927 * due to lack of support in some host stats infrastructures for 6928 * TLVs nested within TLVs. 6929 */ 6930 typedef struct { 6931 htt_tlv_hdr_t tlv_hdr; 6932 6933 /** The channel number on which these stats were collected */ 6934 A_UINT32 chan_num; 6935 6936 /** num of CCA records (Num of htt_pdev_stats_cca_counters_tlv)*/ 6937 A_UINT32 num_records; 6938 6939 /** 6940 * Bit map of valid CCA counters 6941 * Bit0 - tx_frame_usec 6942 * Bit1 - rx_frame_usec 6943 * Bit2 - rx_clear_usec 6944 * Bit3 - my_rx_frame_usec 6945 * bit4 - usec_cnt 6946 * Bit5 - med_rx_idle_usec 6947 * Bit6 - med_tx_idle_global_usec 6948 * Bit7 - cca_obss_usec 6949 * 6950 * See HTT_PDEV_CCA_STATS_xxx_INFO_PRESENT defs 6951 */ 6952 A_UINT32 valid_cca_counters_bitmap; 6953 6954 /** Indicates the stats collection interval 6955 * Valid Values: 6956 * 100 - For the 100ms interval CCA stats histogram 6957 * 1000 - For 1sec interval CCA histogram 6958 * 0xFFFFFFFF - For Cumulative CCA Stats 6959 */ 6960 A_UINT32 collection_interval; 6961 6962 /** 6963 * This will be followed by an array which contains the CCA stats 6964 * collected in the last N intervals, 6965 * if the indication is for last N intervals CCA stats. 6966 * Then the pdev_cca_stats[0] element contains the oldest CCA stats 6967 * and pdev_cca_stats[N-1] will have the most recent CCA stats. 6968 */ 6969 HTT_STATS_VAR_LEN_ARRAY1(htt_stats_pdev_cca_counters_tlv, cca_hist_tlv); 6970 } htt_pdev_cca_stats_hist_tlv; 6971 6972 typedef struct { 6973 htt_tlv_hdr_t tlv_hdr; 6974 6975 /** The channel number on which these stats were collected */ 6976 A_UINT32 chan_num; 6977 6978 /** num of CCA records (Num of htt_pdev_stats_cca_counters_tlv)*/ 6979 A_UINT32 num_records; 6980 6981 /** 6982 * Bit map of valid CCA counters 6983 * Bit0 - tx_frame_usec 6984 * Bit1 - rx_frame_usec 6985 * Bit2 - rx_clear_usec 6986 * Bit3 - my_rx_frame_usec 6987 * bit4 - usec_cnt 6988 * Bit5 - med_rx_idle_usec 6989 * Bit6 - med_tx_idle_global_usec 6990 * Bit7 - cca_obss_usec 6991 * 6992 * See HTT_PDEV_CCA_STATS_xxx_INFO_PRESENT defs 6993 */ 6994 A_UINT32 valid_cca_counters_bitmap; 6995 6996 /** Indicates the stats collection interval 6997 * Valid Values: 6998 * 100 - For the 100ms interval CCA stats histogram 6999 * 1000 - For 1sec interval CCA histogram 7000 * 0xFFFFFFFF - For Cumulative CCA Stats 7001 */ 7002 A_UINT32 collection_interval; 7003 7004 /** 7005 * This will be followed by an array which contains the CCA stats 7006 * collected in the last N intervals, 7007 * if the indication is for last N intervals CCA stats. 7008 * Then the pdev_cca_stats[0] element contains the oldest CCA stats 7009 * and pdev_cca_stats[N-1] will have the most recent CCA stats. 7010 * htt_pdev_stats_cca_counters_tlv cca_hist_tlv[1]; 7011 */ 7012 } htt_pdev_cca_stats_hist_v1_tlv; 7013 7014 #define HTT_TWT_SESSION_FLAG_FLOW_ID_M 0x0000000f 7015 #define HTT_TWT_SESSION_FLAG_FLOW_ID_S 0 7016 7017 #define HTT_TWT_SESSION_FLAG_BTWT_PEER_CNT_M 0x0000fff0 7018 #define HTT_TWT_SESSION_FLAG_BTWT_PEER_CNT_S 4 7019 7020 #define HTT_TWT_SESSION_FLAG_BCAST_TWT_M 0x00010000 7021 #define HTT_TWT_SESSION_FLAG_BCAST_TWT_S 16 7022 7023 #define HTT_TWT_SESSION_FLAG_TRIGGER_TWT_M 0x00020000 7024 #define HTT_TWT_SESSION_FLAG_TRIGGER_TWT_S 17 7025 7026 #define HTT_TWT_SESSION_FLAG_ANNOUN_TWT_M 0x00040000 7027 #define HTT_TWT_SESSION_FLAG_ANNOUN_TWT_S 18 7028 7029 #define HTT_TWT_SESSION_FLAG_FLOW_ID_GET(_var) \ 7030 (((_var) & HTT_TWT_SESSION_FLAG_FLOW_ID_M) >> \ 7031 HTT_TWT_SESSION_FLAG_FLOW_ID_S) 7032 7033 #define HTT_TWT_SESSION_FLAG_FLOW_ID_SET(_var, _val) \ 7034 do { \ 7035 HTT_CHECK_SET_VAL(HTT_TWT_SESSION_FLAG_FLOW_ID, _val); \ 7036 ((_var) |= ((_val) << HTT_TWT_SESSION_FLAG_FLOW_ID_S)); \ 7037 } while (0) 7038 7039 #define HTT_TWT_SESSION_FLAG_BTWT_PEER_CNT_GET(_var) \ 7040 (((_var) & HTT_TWT_SESSION_FLAG_BTWT_PEER_CNT_M) >> \ 7041 HTT_TWT_SESSION_FLAG_BTWT_PEER_CNT_S) 7042 7043 #define HTT_TWT_SESSION_FLAG_BTWT_PEER_CNT_SET(_var, _val) \ 7044 do { \ 7045 HTT_CHECK_SET_VAL(HTT_TWT_SESSION_FLAG_BTWT_PEER_CNT, _val); \ 7046 ((_var) |= ((_val) << HTT_TWT_SESSION_FLAG_BTWT_PEER_CNT_S)); \ 7047 } while (0) 7048 7049 #define HTT_TWT_SESSION_FLAG_BCAST_TWT_GET(_var) \ 7050 (((_var) & HTT_TWT_SESSION_FLAG_BCAST_TWT_M) >> \ 7051 HTT_TWT_SESSION_FLAG_BCAST_TWT_S) 7052 7053 #define HTT_TWT_SESSION_FLAG_BCAST_TWT_SET(_var, _val) \ 7054 do { \ 7055 HTT_CHECK_SET_VAL(HTT_TWT_SESSION_FLAG_BCAST_TWT, _val); \ 7056 ((_var) |= ((_val) << HTT_TWT_SESSION_FLAG_BCAST_TWT_S)); \ 7057 } while (0) 7058 7059 #define HTT_TWT_SESSION_FLAG_TRIGGER_TWT_GET(_var) \ 7060 (((_var) & HTT_TWT_SESSION_FLAG_TRIGGER_TWT_M) >> \ 7061 HTT_TWT_SESSION_FLAG_TRIGGER_TWT_S) 7062 7063 #define HTT_TWT_SESSION_FLAG_TRIGGER_TWT_SET(_var, _val) \ 7064 do { \ 7065 HTT_CHECK_SET_VAL(HTT_TWT_SESSION_FLAG_TRIGGER_TWT, _val); \ 7066 ((_var) |= ((_val) << HTT_TWT_SESSION_FLAG_TRIGGER_TWT_S)); \ 7067 } while (0) 7068 7069 #define HTT_TWT_SESSION_FLAG_ANNOUN_TWT_GET(_var) \ 7070 (((_var) & HTT_TWT_SESSION_FLAG_ANNOUN_TWT_M) >> \ 7071 HTT_TWT_SESSION_FLAG_ANNOUN_TWT_S) 7072 7073 #define HTT_TWT_SESSION_FLAG_ANNOUN_TWT_SET(_var, _val) \ 7074 do { \ 7075 HTT_CHECK_SET_VAL(HTT_TWT_SESSION_FLAG_ANNOUN_TWT, _val); \ 7076 ((_var) |= ((_val) << HTT_TWT_SESSION_FLAG_ANNOUN_TWT_S)); \ 7077 } while (0) 7078 7079 #define TWT_DIALOG_ID_UNAVAILABLE 0xFFFFFFFF 7080 7081 typedef struct { 7082 htt_tlv_hdr_t tlv_hdr; 7083 7084 A_UINT32 vdev_id; 7085 htt_mac_addr peer_mac; 7086 A_UINT32 flow_id_flags; 7087 /** 7088 * TWT_DIALOG_ID_UNAVAILABLE is used when TWT session is 7089 * not initiated by host 7090 */ 7091 A_UINT32 dialog_id; 7092 A_UINT32 wake_dura_us; 7093 A_UINT32 wake_intvl_us; 7094 A_UINT32 sp_offset_us; 7095 } htt_stats_pdev_twt_session_tlv; 7096 /* preserve old name alias for new name consistent with the tag name */ 7097 typedef htt_stats_pdev_twt_session_tlv htt_pdev_stats_twt_session_tlv; 7098 7099 typedef struct { 7100 htt_tlv_hdr_t tlv_hdr; 7101 7102 A_UINT32 pdev_id; 7103 A_UINT32 num_sessions; 7104 7105 HTT_STATS_VAR_LEN_ARRAY1(htt_stats_pdev_twt_session_tlv, twt_session); 7106 } htt_stats_pdev_twt_sessions_tlv; 7107 /* preserve old name alias for new name consistent with the tag name */ 7108 typedef htt_stats_pdev_twt_sessions_tlv htt_pdev_stats_twt_sessions_tlv; 7109 7110 /* STATS_TYPE: HTT_DBG_EXT_STATS_TWT_SESSIONS 7111 * TLV_TAGS: 7112 * - HTT_STATS_PDEV_TWT_SESSIONS_TAG 7113 * - HTT_STATS_PDEV_TWT_SESSION_TAG 7114 */ 7115 /* NOTE: 7116 * This structure is for documentation, and cannot be safely used directly. 7117 * Instead, use the constituent TLV structures to fill/parse. 7118 */ 7119 #ifdef ATH_TARGET 7120 typedef struct { 7121 htt_stats_pdev_twt_session_tlv twt_sessions[1]; 7122 } htt_pdev_twt_sessions_stats_t; 7123 #endif /* ATH_TARGET */ 7124 7125 typedef enum { 7126 /* Global link descriptor queued in REO */ 7127 HTT_RX_REO_RESOURCE_GLOBAL_LINK_DESC_COUNT_0 = 0, 7128 HTT_RX_REO_RESOURCE_GLOBAL_LINK_DESC_COUNT_1 = 1, 7129 HTT_RX_REO_RESOURCE_GLOBAL_LINK_DESC_COUNT_2 = 2, 7130 /*Number of queue descriptors of this aging group */ 7131 HTT_RX_REO_RESOURCE_BUFFERS_USED_AC0 = 3, 7132 HTT_RX_REO_RESOURCE_BUFFERS_USED_AC1 = 4, 7133 HTT_RX_REO_RESOURCE_BUFFERS_USED_AC2 = 5, 7134 HTT_RX_REO_RESOURCE_BUFFERS_USED_AC3 = 6, 7135 /* Total number of MSDUs buffered in AC */ 7136 HTT_RX_REO_RESOURCE_AGING_NUM_QUEUES_AC0 = 7, 7137 HTT_RX_REO_RESOURCE_AGING_NUM_QUEUES_AC1 = 8, 7138 HTT_RX_REO_RESOURCE_AGING_NUM_QUEUES_AC2 = 9, 7139 HTT_RX_REO_RESOURCE_AGING_NUM_QUEUES_AC3 = 10, 7140 7141 HTT_RX_REO_RESOURCE_STATS_MAX = 16 7142 } htt_rx_reo_resource_sample_id_enum; 7143 7144 typedef struct { 7145 htt_tlv_hdr_t tlv_hdr; 7146 /* Variable based on the Number of records. HTT_RX_REO_RESOURCE_STATS_MAX */ 7147 /** htt_rx_reo_debug_sample_id_enum */ 7148 A_UINT32 sample_id; 7149 /** Max value of all samples */ 7150 A_UINT32 total_max; 7151 /** Average value of total samples */ 7152 A_UINT32 total_avg; 7153 /** Num of samples including both zeros and non zeros ones*/ 7154 A_UINT32 total_sample; 7155 /** Average value of all non zeros samples */ 7156 A_UINT32 non_zeros_avg; 7157 /** Num of non zeros samples */ 7158 A_UINT32 non_zeros_sample; 7159 /** Max value of last N non zero samples (N = last_non_zeros_sample) */ 7160 A_UINT32 last_non_zeros_max; 7161 /** Min value of last N non zero samples (N = last_non_zeros_sample) */ 7162 A_UINT32 last_non_zeros_min; 7163 /** Average value of last N non zero samples (N = last_non_zeros_sample) */ 7164 A_UINT32 last_non_zeros_avg; 7165 /** Num of last non zero samples */ 7166 A_UINT32 last_non_zeros_sample; 7167 } htt_stats_rx_reo_resource_stats_tlv; 7168 /* preserve old name alias for new name consistent with the tag name */ 7169 typedef htt_stats_rx_reo_resource_stats_tlv htt_rx_reo_resource_stats_tlv_v; 7170 7171 /* STATS_TYPE: HTT_DBG_EXT_STATS_REO_RESOURCE_STATS 7172 * TLV_TAGS: 7173 * - HTT_STATS_RX_REO_RESOURCE_STATS_TAG 7174 */ 7175 /* NOTE: 7176 * This structure is for documentation, and cannot be safely used directly. 7177 * Instead, use the constituent TLV structures to fill/parse. 7178 */ 7179 #ifdef ATH_TARGET 7180 typedef struct { 7181 htt_stats_rx_reo_resource_stats_tlv reo_resource_stats; 7182 } htt_soc_reo_resource_stats_t; 7183 #endif /* ATH_TARGET */ 7184 7185 /* == TX SOUNDING STATS == */ 7186 7187 /* config_param0 */ 7188 7189 #define HTT_DBG_EXT_STATS_SET_VDEV_MASK(_var) ((_var << 1) | 0x1) 7190 #define HTT_DBG_EXT_STATS_GET_VDEV_ID_FROM_VDEV_MASK(_var) ((_var >> 1) & 0xFF) 7191 #define HTT_DBG_EXT_STATS_IS_VDEV_ID_SET(_var) ((_var) & 0x1) 7192 7193 typedef enum { 7194 /* Implicit beamforming stats */ 7195 HTT_IMPLICIT_TXBF_STEER_STATS = 0, 7196 /* Single user short inter frame sequence steer stats */ 7197 HTT_EXPLICIT_TXBF_SU_SIFS_STEER_STATS = 1, 7198 /* Single user random back off steer stats */ 7199 HTT_EXPLICIT_TXBF_SU_RBO_STEER_STATS = 2, 7200 /* Multi user short inter frame sequence steer stats */ 7201 HTT_EXPLICIT_TXBF_MU_SIFS_STEER_STATS = 3, 7202 /* Multi user random back off steer stats */ 7203 HTT_EXPLICIT_TXBF_MU_RBO_STEER_STATS = 4, 7204 /* For backward compatibility new modes cannot be added */ 7205 HTT_TXBF_MAX_NUM_OF_MODES = 5 7206 } htt_txbf_sound_steer_modes; 7207 7208 typedef enum { 7209 HTT_TX_AC_SOUNDING_MODE = 0, 7210 HTT_TX_AX_SOUNDING_MODE = 1, 7211 HTT_TX_BE_SOUNDING_MODE = 2, 7212 HTT_TX_CMN_SOUNDING_MODE = 3, 7213 HTT_TX_CV_CORR_MODE = 4, 7214 } htt_stats_sounding_tx_mode; 7215 7216 #define HTT_TX_CV_CORR_MAX_NUM_COLUMNS 8 7217 7218 typedef struct { 7219 htt_tlv_hdr_t tlv_hdr; 7220 A_UINT32 tx_sounding_mode; /* HTT_TX_XX_SOUNDING_MODE */ 7221 /* Counts number of soundings for all steering modes in each bw */ 7222 A_UINT32 cbf_20[HTT_TXBF_MAX_NUM_OF_MODES]; 7223 A_UINT32 cbf_40[HTT_TXBF_MAX_NUM_OF_MODES]; 7224 A_UINT32 cbf_80[HTT_TXBF_MAX_NUM_OF_MODES]; 7225 A_UINT32 cbf_160[HTT_TXBF_MAX_NUM_OF_MODES]; 7226 /** 7227 * The sounding array is a 2-D array stored as an 1-D array of 7228 * A_UINT32. The stats for a particular user/bw combination is 7229 * referenced with the following: 7230 * 7231 * sounding[(user* max_bw) + bw] 7232 * 7233 * ... where max_bw == 4 for 160mhz 7234 */ 7235 A_UINT32 sounding[HTT_TX_NUM_OF_SOUNDING_STATS_WORDS]; 7236 7237 /* cv upload handler stats */ 7238 /** total times CV nc mismatched */ 7239 A_UINT32 cv_nc_mismatch_err; 7240 /** total times CV has FCS error */ 7241 A_UINT32 cv_fcs_err; 7242 /** total times CV has invalid NSS index */ 7243 A_UINT32 cv_frag_idx_mismatch; 7244 /** total times CV has invalid SW peer ID */ 7245 A_UINT32 cv_invalid_peer_id; 7246 /** total times CV rejected because TXBF is not setup in peer */ 7247 A_UINT32 cv_no_txbf_setup; 7248 /** total times CV expired while in updating state */ 7249 A_UINT32 cv_expiry_in_update; 7250 /** total times Pkt b/w exceeding the cbf_bw */ 7251 A_UINT32 cv_pkt_bw_exceed; 7252 /** total times CV DMA not completed */ 7253 A_UINT32 cv_dma_not_done_err; 7254 /** total times CV update to peer failed */ 7255 A_UINT32 cv_update_failed; 7256 7257 /* cv query stats */ 7258 /** total times CV query happened */ 7259 A_UINT32 cv_total_query; 7260 /** total pattern based CV query */ 7261 A_UINT32 cv_total_pattern_query; 7262 /** total BW based CV query */ 7263 A_UINT32 cv_total_bw_query; 7264 /** incorrect encoding in CV flags */ 7265 A_UINT32 cv_invalid_bw_coding; 7266 /** forced sounding enabled for the peer */ 7267 A_UINT32 cv_forced_sounding; 7268 /** standalone sounding sequence on-going */ 7269 A_UINT32 cv_standalone_sounding; 7270 /** NC of available CV lower than expected */ 7271 A_UINT32 cv_nc_mismatch; 7272 /** feedback type different from expected */ 7273 A_UINT32 cv_fb_type_mismatch; 7274 /** CV BW not equal to expected BW for OFDMA */ 7275 A_UINT32 cv_ofdma_bw_mismatch; 7276 /** CV BW not greater than or equal to expected BW */ 7277 A_UINT32 cv_bw_mismatch; 7278 /** CV pattern not matching with the expected pattern */ 7279 A_UINT32 cv_pattern_mismatch; 7280 /** CV available is of different preamble type than expected. */ 7281 A_UINT32 cv_preamble_mismatch; 7282 /** NR of available CV is lower than expected. */ 7283 A_UINT32 cv_nr_mismatch; 7284 /** CV in use count has exceeded threshold and cannot be used further. */ 7285 A_UINT32 cv_in_use_cnt_exceeded; 7286 /** A valid CV has been found. */ 7287 A_UINT32 cv_found; 7288 /** No valid CV was found. */ 7289 A_UINT32 cv_not_found; 7290 /** Sounding per user in 320MHz bandwidth */ 7291 A_UINT32 sounding_320[HTT_TX_PDEV_STATS_NUM_BE_MUMIMO_USER_STATS]; 7292 /** Counts number of soundings for all steering modes in 320MHz bandwidth */ 7293 A_UINT32 cbf_320[HTT_TXBF_MAX_NUM_OF_MODES]; 7294 /* This part can be used for new counters added for CV query/upload. */ 7295 /** non-trigger based ranging sequence on-going */ 7296 A_UINT32 cv_ntbr_sounding; 7297 /** CV found, but upload is in progress. */ 7298 A_UINT32 cv_found_upload_in_progress; 7299 /** Expired CV found during query. */ 7300 A_UINT32 cv_expired_during_query; 7301 /** total times CV dma timeout happened */ 7302 A_UINT32 cv_dma_timeout_error; 7303 /** total times CV bufs uploaded for IBF case */ 7304 A_UINT32 cv_buf_ibf_uploads; 7305 /** total times CV bufs uploaded for EBF case */ 7306 A_UINT32 cv_buf_ebf_uploads; 7307 /** total times CV bufs received from IPC ring */ 7308 A_UINT32 cv_buf_received; 7309 /** total times CV bufs fed back to the IPC ring */ 7310 A_UINT32 cv_buf_fed_back; 7311 /** Total times CV query happened for IBF case */ 7312 A_UINT32 cv_total_query_ibf; 7313 /** A valid CV has been found for IBF case */ 7314 A_UINT32 cv_found_ibf; 7315 /** A valid CV has not been found for IBF case */ 7316 A_UINT32 cv_not_found_ibf; 7317 /** Expired CV found during query for IBF case */ 7318 A_UINT32 cv_expired_during_query_ibf; 7319 /** Total number of times adaptive sounding logic has been queried */ 7320 A_UINT32 adaptive_snd_total_query; 7321 /** 7322 * Total number of times adaptive sounding mcs drop has been computed 7323 * and recorded. 7324 */ 7325 A_UINT32 adaptive_snd_total_mcs_drop[HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS + HTT_TX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS]; 7326 /** Total number of times adaptive sounding logic kicked in */ 7327 A_UINT32 adaptive_snd_kicked_in; 7328 /** Total number of times we switched back to normal sounding interval */ 7329 A_UINT32 adaptive_snd_back_to_default; 7330 7331 /** 7332 * Below are CV correlation feature related stats. 7333 * This feature is used for DL MU MIMO, but is not available 7334 * from certain legacy targets. 7335 */ 7336 7337 /** number of CV Correlation triggers for online mode */ 7338 A_UINT32 cv_corr_trigger_online_mode; 7339 /** number of CV Correlation triggers for offline mode */ 7340 A_UINT32 cv_corr_trigger_offline_mode; 7341 /** number of CV Correlation triggers for hybrid mode */ 7342 A_UINT32 cv_corr_trigger_hybrid_mode; 7343 /** number of CV Correlation triggers with computation level 0 */ 7344 A_UINT32 cv_corr_trigger_computation_level_0; 7345 /** number of CV Correlation triggers with computation level 1 */ 7346 A_UINT32 cv_corr_trigger_computation_level_1; 7347 /** number of CV Correlation triggers with computation level 2 */ 7348 A_UINT32 cv_corr_trigger_computation_level_2; 7349 /** number of users for which CV Correlation was triggered */ 7350 A_UINT32 cv_corr_trigger_num_users[HTT_TX_CV_CORR_MAX_NUM_COLUMNS]; 7351 /** number of streams for which CV Correlation was triggered */ 7352 A_UINT32 cv_corr_trigger_num_streams[HTT_TX_CV_CORR_MAX_NUM_COLUMNS]; 7353 /** number of CV Correlation buffers received through IPC tickle */ 7354 A_UINT32 cv_corr_upload_total_buf_received; 7355 /** number of CV Correlation buffers fed back to the IPC ring */ 7356 A_UINT32 cv_corr_upload_total_buf_fed_back; 7357 /** number of CV Correlation buffers for which processing failed */ 7358 A_UINT32 cv_corr_upload_total_processing_failed; 7359 /** 7360 * number of CV Correlation buffers for which processing failed, 7361 * due to no users being present in parsed buffer 7362 */ 7363 A_UINT32 cv_corr_upload_failed_total_users_zero; 7364 /** 7365 * number of CV Correlation buffers for which processing failed, 7366 * due to number of users present in parsed buffer exceeded 7367 * CV_CORR_MAX_NUM_COLUMNS 7368 */ 7369 A_UINT32 cv_corr_upload_failed_total_users_exceeded; 7370 /** 7371 * number of CV Correlation buffers for which processing failed, 7372 * due to peer pointer for parsed peer not available 7373 */ 7374 A_UINT32 cv_corr_upload_failed_peer_not_found; 7375 /** 7376 * number of CV Correlation buffers for which processing encountered, 7377 * Nss of peer exceeding SCHED_ALGO_MAX_SUPPORTED_MUMIMO_NSS 7378 */ 7379 A_UINT32 cv_corr_upload_user_nss_exceeded; 7380 /** 7381 * number of CV Correlation buffers for which processing encountered, 7382 * invalid reverse look up index for fetching CV correlation results 7383 */ 7384 A_UINT32 cv_corr_upload_invalid_lookup_index; 7385 /** number of users present in uploaded CV Correlation results buffer */ 7386 A_UINT32 cv_corr_upload_total_num_users[HTT_TX_CV_CORR_MAX_NUM_COLUMNS]; 7387 /** number of streams present in uploaded CV Correlation results buffer */ 7388 A_UINT32 cv_corr_upload_total_num_streams[HTT_TX_CV_CORR_MAX_NUM_COLUMNS]; 7389 } htt_stats_tx_sounding_stats_tlv; 7390 /* preserve old name alias for new name consistent with the tag name */ 7391 typedef htt_stats_tx_sounding_stats_tlv htt_tx_sounding_stats_tlv; 7392 7393 /* STATS_TYPE : HTT_DBG_EXT_STATS_TX_SOUNDING_INFO 7394 * TLV_TAGS: 7395 * - HTT_STATS_TX_SOUNDING_STATS_TAG 7396 */ 7397 /* NOTE: 7398 * This structure is for documentation, and cannot be safely used directly. 7399 * Instead, use the constituent TLV structures to fill/parse. 7400 */ 7401 #ifdef ATH_TARGET 7402 typedef struct { 7403 htt_stats_tx_sounding_stats_tlv sounding_tlv; 7404 } htt_tx_sounding_stats_t; 7405 #endif /* ATH_TARGET */ 7406 7407 typedef struct { 7408 htt_tlv_hdr_t tlv_hdr; 7409 7410 A_UINT32 num_obss_tx_ppdu_success; 7411 A_UINT32 num_obss_tx_ppdu_failure; 7412 /** num_sr_tx_transmissions: 7413 * Counter of TX done by aborting other BSS RX with spatial reuse 7414 * (for cases where rx RSSI from other BSS is below the packet-detection 7415 * threshold for doing spatial reuse) 7416 */ 7417 union { 7418 A_UINT32 num_sr_tx_transmissions; /* CORRECTED - use this one */ 7419 A_UINT32 num_sr_tx_tranmissions; /* DEPRECATED - has typo in name */ 7420 }; 7421 union { 7422 /** 7423 * Count the number of times the RSSI from an other-BSS signal 7424 * is below the spatial reuse power threshold, thus providing an 7425 * opportunity for spatial reuse since OBSS interference will be 7426 * inconsequential. 7427 */ 7428 A_UINT32 num_spatial_reuse_opportunities; 7429 7430 /* DEPRECATED: num_sr_rx_ge_pd_rssi_thr 7431 * This old name has been deprecated because it does not 7432 * clearly and accurately reflect the information stored within 7433 * this field. 7434 * Use the new name (num_spatial_reuse_opportunities) instead of 7435 * the deprecated old name (num_sr_rx_ge_pd_rssi_thr). 7436 */ 7437 A_UINT32 num_sr_rx_ge_pd_rssi_thr; 7438 }; 7439 7440 /** 7441 * Count of number of times OBSS frames were aborted and non-SRG 7442 * opportunities were created. Non-SRG opportunities are created when 7443 * incoming OBSS RSSI is lesser than the global configured non-SRG RSSI 7444 * threshold and non-SRG OBSS color / non-SRG OBSS BSSID registers 7445 * allow non-SRG TX. 7446 */ 7447 A_UINT32 num_non_srg_opportunities; 7448 /** 7449 * Count of number of times TX PPDU were transmitted using non-SRG 7450 * opportunities created. Incoming OBSS frame RSSI is compared with per 7451 * PPDU non-SRG RSSI threshold configured in each PPDU. If incoming OBSS 7452 * RSSI < non-SRG RSSI threshold configured in each PPDU, then non-SRG 7453 * transmission happens. 7454 */ 7455 A_UINT32 num_non_srg_ppdu_tried; 7456 /** 7457 * Count of number of times non-SRG based TX transmissions were successful 7458 */ 7459 A_UINT32 num_non_srg_ppdu_success; 7460 /** 7461 * Count of number of times OBSS frames were aborted and SRG opportunities 7462 * were created. Srg opportunities are created when incoming OBSS RSSI 7463 * is less than the global configured SRG RSSI threshold and SRC OBSS 7464 * color / SRG OBSS BSSID / SRG partial bssid / SRG BSS color bitmap 7465 * registers allow SRG TX. 7466 */ 7467 A_UINT32 num_srg_opportunities; 7468 /** 7469 * Count of number of times TX PPDU were transmitted using SRG 7470 * opportunities created. 7471 * Incoming OBSS frame RSSI is compared with per PPDU SRG RSSI 7472 * threshold configured in each PPDU. 7473 * If incoming OBSS RSSI < SRG RSSI threshold configured in each PPDU, 7474 * then SRG transmission happens. 7475 */ 7476 A_UINT32 num_srg_ppdu_tried; 7477 /** 7478 * Count of number of times SRG based TX transmissions were successful 7479 */ 7480 A_UINT32 num_srg_ppdu_success; 7481 /** 7482 * Count of number of times PSR opportunities were created by aborting 7483 * OBSS UL OFDMA HE-TB PPDU frame. HE-TB ppdu frames are aborted if the 7484 * spatial reuse info in the OBSS trigger common field is set to allow PSR 7485 * based spatial reuse. 7486 */ 7487 A_UINT32 num_psr_opportunities; 7488 /** 7489 * Count of number of times TX PPDU were transmitted using PSR 7490 * opportunities created. 7491 */ 7492 A_UINT32 num_psr_ppdu_tried; 7493 /** 7494 * Count of number of times PSR based TX transmissions were successful. 7495 */ 7496 A_UINT32 num_psr_ppdu_success; 7497 /** 7498 * Count of number of times TX PPDU per access category were transmitted 7499 * using non-SRG opportunities created. 7500 */ 7501 A_UINT32 num_non_srg_ppdu_tried_per_ac[HTT_NUM_AC_WMM]; 7502 /** 7503 * Count of number of times non-SRG based TX transmissions per access 7504 * category were successful 7505 */ 7506 A_UINT32 num_non_srg_ppdu_success_per_ac[HTT_NUM_AC_WMM]; 7507 /** 7508 * Count of number of times TX PPDU per access category were transmitted 7509 * using SRG opportunities created. 7510 */ 7511 A_UINT32 num_srg_ppdu_tried_per_ac[HTT_NUM_AC_WMM]; 7512 /** 7513 * Count of number of times SRG based TX transmissions per access 7514 * category were successful 7515 */ 7516 A_UINT32 num_srg_ppdu_success_per_ac[HTT_NUM_AC_WMM]; 7517 /** 7518 * Count of number of times ppdu was flushed due to ongoing OBSS 7519 * frame duration value lesser than minimum required frame duration. 7520 */ 7521 A_UINT32 num_obss_min_duration_check_flush_cnt; 7522 /** 7523 * Count of number of times ppdu was flushed due to ppdu duration 7524 * exceeding aborted OBSS frame duration 7525 */ 7526 A_UINT32 num_sr_ppdu_abort_flush_cnt; 7527 } htt_stats_pdev_obss_pd_tlv; 7528 /* preserve old name alias for new name consistent with the tag name */ 7529 typedef htt_stats_pdev_obss_pd_tlv htt_pdev_obss_pd_stats_tlv; 7530 7531 /* NOTE: 7532 * This structure is for documentation, and cannot be safely used directly. 7533 * Instead, use the constituent TLV structures to fill/parse. 7534 */ 7535 #ifdef ATH_TARGET 7536 typedef struct { 7537 htt_stats_pdev_obss_pd_tlv obss_pd_stat; 7538 } htt_pdev_obss_pd_stats_t; 7539 #endif /* ATH_TARGET */ 7540 7541 typedef struct { 7542 htt_tlv_hdr_t tlv_hdr; 7543 A_UINT32 pdev_id; 7544 A_UINT32 current_head_idx; 7545 A_UINT32 current_tail_idx; 7546 A_UINT32 num_htt_msgs_sent; 7547 /** 7548 * Time in milliseconds for which the ring has been in 7549 * its current backpressure condition 7550 */ 7551 A_UINT32 backpressure_time_ms; 7552 /** backpressure_hist - 7553 * histogram showing how many times different degrees of backpressure 7554 * duration occurred: 7555 * Index 0 indicates the number of times ring was 7556 * continuously in backpressure state for 100 - 200ms. 7557 * Index 1 indicates the number of times ring was 7558 * continuously in backpressure state for 200 - 300ms. 7559 * Index 2 indicates the number of times ring was 7560 * continuously in backpressure state for 300 - 400ms. 7561 * Index 3 indicates the number of times ring was 7562 * continuously in backpressure state for 400 - 500ms. 7563 * Index 4 indicates the number of times ring was 7564 * continuously in backpressure state beyond 500ms. 7565 */ 7566 A_UINT32 backpressure_hist[5]; 7567 } htt_stats_ring_backpressure_stats_tlv; 7568 /* preserve old name alias for new name consistent with the tag name */ 7569 typedef htt_stats_ring_backpressure_stats_tlv htt_ring_backpressure_stats_tlv; 7570 7571 /* STATS_TYPE : HTT_STATS_RING_BACKPRESSURE_STATS_INFO 7572 * TLV_TAGS: 7573 * - HTT_STATS_RING_BACKPRESSURE_STATS_TAG 7574 */ 7575 /* NOTE: 7576 * This structure is for documentation, and cannot be safely used directly. 7577 * Instead, use the constituent TLV structures to fill/parse. 7578 */ 7579 #ifdef ATH_TARGET 7580 typedef struct { 7581 htt_stats_sring_cmn_tlv cmn_tlv; 7582 struct { 7583 htt_stats_string_tlv sring_str_tlv; 7584 htt_stats_ring_backpressure_stats_tlv backpressure_stats_tlv; 7585 } r[1]; /* variable-length array */ 7586 } htt_ring_backpressure_stats_t; 7587 #endif /* ATH_TARGET */ 7588 7589 #define HTT_LATENCY_PROFILE_MAX_HIST 3 7590 #define HTT_STATS_MAX_PROF_STATS_NAME_LEN 32 7591 #define HTT_INTERRUPTS_LATENCY_PROFILE_MAX_HIST 3 7592 typedef struct { 7593 htt_tlv_hdr_t tlv_hdr; 7594 /** print_header: 7595 * This field suggests whether the host should print a header when 7596 * displaying the TLV (because this is the first latency_prof_stats 7597 * TLV within a series), or if only the TLV contents should be displayed 7598 * without a header (because this is not the first TLV within the series). 7599 */ 7600 A_UINT32 print_header; 7601 A_UINT8 latency_prof_name[HTT_STATS_MAX_PROF_STATS_NAME_LEN]; 7602 /** number of data values included in the tot sum */ 7603 A_UINT32 cnt; 7604 /** time in us */ 7605 A_UINT32 min; 7606 /** time in us */ 7607 A_UINT32 max; 7608 A_UINT32 last; 7609 /** time in us */ 7610 A_UINT32 tot; 7611 /** time in us */ 7612 A_UINT32 avg; 7613 /** hist_intvl: 7614 * Histogram interval, i.e. the latency range covered by each 7615 * bin of the histogram, in microsecond units. 7616 * hist[0] counts how many latencies were between 0 to hist_intvl 7617 * hist[1] counts how many latencies were between hist_intvl to 2*hist_intvl 7618 * hist[2] counts how many latencies were more than 2*hist_intvl 7619 */ 7620 A_UINT32 hist_intvl; 7621 A_UINT32 hist[HTT_LATENCY_PROFILE_MAX_HIST]; 7622 /** max page faults in any 1 sampling window */ 7623 A_UINT32 page_fault_max; 7624 /** summed over all sampling windows */ 7625 A_UINT32 page_fault_total; 7626 /** ignored_latency_count: 7627 * ignore some of profile latency to avoid avg skewing 7628 */ 7629 A_UINT32 ignored_latency_count; 7630 /** interrupts_max: max interrupts within any single sampling window */ 7631 A_UINT32 interrupts_max; 7632 /** interrupts_hist: histogram of interrupt rate 7633 * bin0 contains the number of sampling windows that had 0 interrupts, 7634 * bin1 contains the number of sampling windows that had 1-4 interrupts, 7635 * bin2 contains the number of sampling windows that had > 4 interrupts 7636 */ 7637 A_UINT32 interrupts_hist[HTT_INTERRUPTS_LATENCY_PROFILE_MAX_HIST]; 7638 /* min time in us for pcycles spent on q6 core on all HW threads */ 7639 A_UINT32 min_pcycles_time; 7640 /* max time in us for pcycles spent on q6 core on all HW threads */ 7641 A_UINT32 max_pcycles_time; 7642 /* total time in us for pcycles spent on q6 core on all HW threads */ 7643 A_UINT32 tot_pcycles_time; 7644 /* avg time in us for pcycles spent on q6 core on all HW threads */ 7645 A_UINT32 avg_pcycles_time; 7646 } htt_stats_latency_prof_stats_tlv; 7647 /* preserve old name alias for new name consistent with the tag name */ 7648 typedef htt_stats_latency_prof_stats_tlv htt_latency_prof_stats_tlv; 7649 7650 typedef struct { 7651 htt_tlv_hdr_t tlv_hdr; 7652 /** duration: 7653 * Time period over which counts were gathered, units = microseconds. 7654 */ 7655 A_UINT32 duration; 7656 A_UINT32 tx_msdu_cnt; 7657 A_UINT32 tx_mpdu_cnt; 7658 A_UINT32 tx_ppdu_cnt; 7659 A_UINT32 rx_msdu_cnt; 7660 A_UINT32 rx_mpdu_cnt; 7661 } htt_stats_latency_ctx_tlv; 7662 /* preserve old name alias for new name consistent with the tag name */ 7663 typedef htt_stats_latency_ctx_tlv htt_latency_prof_ctx_tlv; 7664 7665 typedef struct { 7666 htt_tlv_hdr_t tlv_hdr; 7667 /** count of enabled profiles */ 7668 A_UINT32 prof_enable_cnt; 7669 } htt_stats_latency_cnt_tlv; 7670 /* preserve old name alias for new name consistent with the tag name */ 7671 typedef htt_stats_latency_cnt_tlv htt_latency_prof_cnt_tlv; 7672 7673 /* STATS_TYPE : HTT_DBG_EXT_STATS_LATENCY_PROF_STATS 7674 * TLV_TAGS: 7675 * HTT_STATS_LATENCY_PROF_STATS_TAG / htt_latency_prof_stats_tlv 7676 * HTT_STATS_LATENCY_CTX_TAG / htt_latency_prof_ctx_tlv 7677 * HTT_STATS_LATENCY_CNT_TAG / htt_latency_prof_cnt_tlv 7678 */ 7679 /* NOTE: 7680 * This structure is for documentation, and cannot be safely used directly. 7681 * Instead, use the constituent TLV structures to fill/parse. 7682 */ 7683 #ifdef ATH_TARGET 7684 typedef struct { 7685 htt_stats_latency_prof_stats_tlv latency_prof_stat; 7686 htt_stats_latency_ctx_tlv latency_ctx_stat; 7687 htt_stats_latency_cnt_tlv latency_cnt_stat; 7688 } htt_soc_latency_stats_t; 7689 #endif /* ATH_TARGET */ 7690 7691 #define HTT_RX_MAX_PEAK_OCCUPANCY_INDEX 10 7692 #define HTT_RX_MAX_CURRENT_OCCUPANCY_INDEX 10 7693 #define HTT_RX_SQUARE_INDEX 6 7694 #define HTT_RX_MAX_PEAK_SEARCH_INDEX 4 7695 #define HTT_RX_MAX_PENDING_SEARCH_INDEX 4 7696 7697 /* STATS_TYPE : HTT_DBG_EXT_RX_FSE_STATS 7698 * TLV_TAGS: 7699 * - HTT_STATS_RX_FSE_STATS_TAG 7700 */ 7701 typedef struct { 7702 htt_tlv_hdr_t tlv_hdr; 7703 7704 /** 7705 * Number of times host requested for fse enable/disable 7706 */ 7707 A_UINT32 fse_enable_cnt; 7708 A_UINT32 fse_disable_cnt; 7709 /** 7710 * Number of times host requested for fse cache invalidation 7711 * individual entries or full cache 7712 */ 7713 A_UINT32 fse_cache_invalidate_entry_cnt; 7714 A_UINT32 fse_full_cache_invalidate_cnt; 7715 7716 /** 7717 * Cache hits count will increase if there is a matching flow in the cache 7718 * There is no register for cache miss but the number of cache misses can 7719 * be calculated as 7720 * cache miss = (num_searches - cache_hits) 7721 * Thus, there is no need to have a separate variable for cache misses. 7722 * Num searches is flow search times done in the cache. 7723 */ 7724 A_UINT32 fse_num_cache_hits_cnt; 7725 A_UINT32 fse_num_searches_cnt; 7726 /** 7727 * Cache Occupancy holds 2 types of values: Peak and Current. 7728 * 10 bins are used to keep track of peak occupancy. 7729 * 8 of these bins represent ranges of values, while the first and last 7730 * bins represent the extreme cases of the cache being completely empty 7731 * or completely full. 7732 * For the non-extreme bins, the number of cache occupancy values per 7733 * bin is the maximum cache occupancy (128), divided by the number of 7734 * non-extreme bins (8), so 128/8 = 16 values per bin. 7735 * The range of values for each histogram bins is specified below: 7736 * Bin0 = Counter increments when cache occupancy is empty 7737 * Bin1 = Counter increments when cache occupancy is within [1 to 16] 7738 * Bin2 = Counter increments when cache occupancy is within [17 to 32] 7739 * Bin3 = Counter increments when cache occupancy is within [33 to 48] 7740 * Bin4 = Counter increments when cache occupancy is within [49 to 64] 7741 * Bin5 = Counter increments when cache occupancy is within [65 to 80] 7742 * Bin6 = Counter increments when cache occupancy is within [81 to 96] 7743 * Bin7 = Counter increments when cache occupancy is within [97 to 112] 7744 * Bin8 = Counter increments when cache occupancy is within [113 to 127] 7745 * Bin9 = Counter increments when cache occupancy is equal to 128 7746 * The above histogram bin definitions apply to both the peak-occupancy 7747 * histogram and the current-occupancy histogram. 7748 * 7749 * @fse_cache_occupancy_peak_cnt: 7750 * Array records periodically PEAK cache occupancy values. 7751 * Peak Occupancy will increment only if it is greater than current 7752 * occupancy value. 7753 * 7754 * @fse_cache_occupancy_curr_cnt: 7755 * Array records periodically current cache occupancy value. 7756 * Current Cache occupancy always holds instant snapshot of 7757 * current number of cache entries. 7758 **/ 7759 A_UINT32 fse_cache_occupancy_peak_cnt[HTT_RX_MAX_PEAK_OCCUPANCY_INDEX]; 7760 A_UINT32 fse_cache_occupancy_curr_cnt[HTT_RX_MAX_CURRENT_OCCUPANCY_INDEX]; 7761 /** 7762 * Square stat is sum of squares of cache occupancy to better understand 7763 * any variation/deviation within each cache set, over a given time-window. 7764 * 7765 * Square stat is calculated this way: 7766 * Square = SUM(Squares of all Occupancy in a Set) / 8 7767 * The cache has 16-way set associativity, so the occupancy of a 7768 * set can vary from 0 to 16. There are 8 sets within the cache. 7769 * Therefore, the minimum possible square value is 0, and the maximum 7770 * possible square value is (8*16^2) / 8 = 256. 7771 * 7772 * 6 bins are used to keep track of square stats: 7773 * Bin0 = increments when square of current cache occupancy is zero 7774 * Bin1 = increments when square of current cache occupancy is within 7775 * [1 to 50] 7776 * Bin2 = increments when square of current cache occupancy is within 7777 * [51 to 100] 7778 * Bin3 = increments when square of current cache occupancy is within 7779 * [101 to 200] 7780 * Bin4 = increments when square of current cache occupancy is within 7781 * [201 to 255] 7782 * Bin5 = increments when square of current cache occupancy is 256 7783 */ 7784 A_UINT32 fse_search_stat_square_cnt[HTT_RX_SQUARE_INDEX]; 7785 /** 7786 * Search stats has 2 types of values: Peak Pending and Number of 7787 * Search Pending. 7788 * GSE command ring for FSE can hold maximum of 5 Pending searches 7789 * at any given time. 7790 * 7791 * 4 bins are used to keep track of search stats: 7792 * Bin0 = Counter increments when there are NO pending searches 7793 * (For peak, it will be number of pending searches greater 7794 * than GSE command ring FIFO outstanding requests. 7795 * For Search Pending, it will be number of pending search 7796 * inside GSE command ring FIFO.) 7797 * Bin1 = Counter increments when number of pending searches are within 7798 * [1 to 2] 7799 * Bin2 = Counter increments when number of pending searches are within 7800 * [3 to 4] 7801 * Bin3 = Counter increments when number of pending searches are 7802 * greater/equal to [ >= 5] 7803 */ 7804 A_UINT32 fse_search_stat_peak_cnt[HTT_RX_MAX_PEAK_SEARCH_INDEX]; 7805 A_UINT32 fse_search_stat_search_pending_cnt[HTT_RX_MAX_PENDING_SEARCH_INDEX]; 7806 } htt_stats_rx_fse_stats_tlv; 7807 /* preserve old name alias for new name consistent with the tag name */ 7808 typedef htt_stats_rx_fse_stats_tlv htt_rx_fse_stats_tlv; 7809 7810 /* NOTE: 7811 * This structure is for documentation, and cannot be safely used directly. 7812 * Instead, use the constituent TLV structures to fill/parse. 7813 */ 7814 #ifdef ATH_TARGET 7815 typedef struct { 7816 htt_stats_rx_fse_stats_tlv rx_fse_stats; 7817 } htt_rx_fse_stats_t; 7818 #endif /* ATH_TARGET */ 7819 7820 #define HTT_TX_TXBF_RATE_STATS_NUM_MCS_COUNTERS 14 7821 #define HTT_TX_TXBF_RATE_STATS_NUM_BW_COUNTERS 5 /* 20, 40, 80, 160, 320 */ 7822 7823 #define HTT_TX_TXBF_RATE_STATS_NUM_REDUCED_CHAN_TYPES 2/* 0: Half, 1: Quarter */ 7824 7825 typedef struct { 7826 htt_tlv_hdr_t tlv_hdr; 7827 /** SU TxBF TX MCS stats */ 7828 A_UINT32 tx_su_txbf_mcs[HTT_TX_TXBF_RATE_STATS_NUM_MCS_COUNTERS]; 7829 /** Implicit BF TX MCS stats */ 7830 A_UINT32 tx_su_ibf_mcs[HTT_TX_TXBF_RATE_STATS_NUM_MCS_COUNTERS]; 7831 /** Open loop TX MCS stats */ 7832 A_UINT32 tx_su_ol_mcs[HTT_TX_TXBF_RATE_STATS_NUM_MCS_COUNTERS]; 7833 /** SU TxBF TX NSS stats */ 7834 A_UINT32 tx_su_txbf_nss[HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS]; 7835 /** Implicit BF TX NSS stats */ 7836 A_UINT32 tx_su_ibf_nss[HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS]; 7837 /** Open loop TX NSS stats */ 7838 A_UINT32 tx_su_ol_nss[HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS]; 7839 /** SU TxBF TX BW stats */ 7840 A_UINT32 tx_su_txbf_bw[HTT_TX_TXBF_RATE_STATS_NUM_BW_COUNTERS]; 7841 /** Implicit BF TX BW stats */ 7842 A_UINT32 tx_su_ibf_bw[HTT_TX_TXBF_RATE_STATS_NUM_BW_COUNTERS]; 7843 /** Open loop TX BW stats */ 7844 A_UINT32 tx_su_ol_bw[HTT_TX_TXBF_RATE_STATS_NUM_BW_COUNTERS]; 7845 /** Legacy and OFDM TX rate stats */ 7846 A_UINT32 tx_legacy_ofdm_rate[HTT_TX_PDEV_STATS_NUM_LEGACY_OFDM_STATS]; 7847 /** SU TxBF TX BW stats */ 7848 A_UINT32 reduced_tx_su_txbf_bw[HTT_TX_TXBF_RATE_STATS_NUM_REDUCED_CHAN_TYPES][HTT_TX_TXBF_RATE_STATS_NUM_BW_COUNTERS]; 7849 /** Implicit BF TX BW stats */ 7850 A_UINT32 reduced_tx_su_ibf_bw[HTT_TX_TXBF_RATE_STATS_NUM_REDUCED_CHAN_TYPES][HTT_TX_TXBF_RATE_STATS_NUM_BW_COUNTERS]; 7851 /** Open loop TX BW stats */ 7852 A_UINT32 reduced_tx_su_ol_bw[HTT_TX_TXBF_RATE_STATS_NUM_REDUCED_CHAN_TYPES][HTT_TX_TXBF_RATE_STATS_NUM_BW_COUNTERS]; 7853 /** Txbf flag reason stats */ 7854 A_UINT32 txbf_flag_set_mu_mode; 7855 A_UINT32 txbf_flag_set_final_status; 7856 A_UINT32 txbf_flag_not_set_verified_txbf_mode; 7857 A_UINT32 txbf_flag_not_set_disable_p2p_access; 7858 A_UINT32 txbf_flag_not_set_max_nss_reached_in_he160; 7859 A_UINT32 txbf_flag_not_set_disable_ul_dl_ofdma; 7860 A_UINT32 txbf_flag_not_set_mcs_threshold_value; 7861 A_UINT32 txbf_flag_not_set_final_status; 7862 } htt_stats_pdev_tx_rate_txbf_stats_tlv; 7863 /* preserve old name alias for new name consistent with the tag name */ 7864 typedef htt_stats_pdev_tx_rate_txbf_stats_tlv htt_tx_pdev_txbf_rate_stats_tlv; 7865 7866 typedef enum { 7867 HTT_STATS_RC_MODE_DLSU = 0, 7868 HTT_STATS_RC_MODE_DLMUMIMO = 1, 7869 HTT_STATS_RC_MODE_DLOFDMA = 2, 7870 HTT_STATS_RC_MODE_ULMUMIMO = 3, 7871 HTT_STATS_RC_MODE_ULOFDMA = 4, 7872 } htt_stats_rc_mode; 7873 7874 typedef struct { 7875 A_UINT32 ppdus_tried; 7876 A_UINT32 ppdus_ack_failed; 7877 A_UINT32 mpdus_tried; 7878 A_UINT32 mpdus_failed; 7879 } htt_tx_rate_stats_t; 7880 7881 typedef enum { 7882 HTT_RC_MODE_SU_OL, 7883 HTT_RC_MODE_SU_BF, 7884 HTT_RC_MODE_MU1_INTF, 7885 HTT_RC_MODE_MU2_INTF, 7886 HTT_Rc_MODE_MU3_INTF, 7887 HTT_RC_MODE_MU4_INTF, 7888 HTT_RC_MODE_MU5_INTF, 7889 HTT_RC_MODE_MU6_INTF, 7890 HTT_RC_MODE_MU7_INTF, 7891 HTT_RC_MODE_2D_COUNT, 7892 } HTT_RC_MODE; 7893 7894 typedef enum { 7895 HTT_STATS_RU_TYPE_INVALID = 0, 7896 HTT_STATS_RU_TYPE_SINGLE_RU_ONLY = 1, 7897 HTT_STATS_RU_TYPE_SINGLE_AND_MULTI_RU = 2, 7898 } htt_stats_ru_type; 7899 7900 typedef struct { 7901 htt_tlv_hdr_t tlv_hdr; 7902 7903 /** HTT_STATS_RC_MODE_XX */ 7904 A_UINT32 rc_mode; 7905 7906 A_UINT32 last_probed_mcs; 7907 7908 A_UINT32 last_probed_nss; 7909 7910 A_UINT32 last_probed_bw; 7911 7912 htt_tx_rate_stats_t per_bw[HTT_TX_PDEV_STATS_NUM_BW_COUNTERS]; 7913 7914 htt_tx_rate_stats_t per_nss[HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS]; 7915 7916 htt_tx_rate_stats_t per_mcs[HTT_TX_TXBF_RATE_STATS_NUM_MCS_COUNTERS]; 7917 7918 /** 320MHz extension for PER */ 7919 htt_tx_rate_stats_t per_bw320; 7920 7921 A_UINT32 probe_cnt_per_rcmode[HTT_RC_MODE_2D_COUNT]; 7922 7923 A_UINT32 ru_type; /* refer to htt_stats_ru_type enum */ 7924 htt_tx_rate_stats_t per_ru[HTT_TX_PDEV_STATS_NUM_BE_RU_SIZE_COUNTERS]; 7925 } htt_stats_per_rate_stats_tlv; 7926 /* preserve old name alias for new name consistent with the tag name */ 7927 typedef htt_stats_per_rate_stats_tlv htt_tx_rate_stats_per_tlv; 7928 7929 /* NOTE: 7930 * This structure is for documentation, and cannot be safely used directly. 7931 * Instead, use the constituent TLV structures to fill/parse. 7932 */ 7933 #ifdef ATH_TARGET 7934 typedef struct { 7935 htt_stats_pdev_tx_rate_txbf_stats_tlv txbf_rate_stats; 7936 } htt_pdev_txbf_rate_stats_t; 7937 #endif /* ATH_TARGET */ 7938 7939 #ifdef ATH_TARGET 7940 typedef struct { 7941 htt_stats_per_rate_stats_tlv per_stats; 7942 } htt_tx_pdev_per_stats_t; 7943 #endif /* ATH_TARGET */ 7944 7945 typedef enum { 7946 HTT_ULTRIG_QBOOST_TRIGGER = 0, 7947 HTT_ULTRIG_PSPOLL_TRIGGER, 7948 HTT_ULTRIG_UAPSD_TRIGGER, 7949 HTT_ULTRIG_11AX_TRIGGER, 7950 HTT_ULTRIG_11AX_WILDCARD_TRIGGER, 7951 HTT_ULTRIG_11AX_UNASSOC_WILDCARD_TRIGGER, 7952 HTT_STA_UL_OFDMA_NUM_TRIG_TYPE, 7953 } HTT_STA_UL_OFDMA_RX_TRIG_TYPE; 7954 7955 typedef enum { 7956 HTT_11AX_TRIGGER_BASIC_E = 0, 7957 HTT_11AX_TRIGGER_BRPOLL_E = 1, 7958 HTT_11AX_TRIGGER_MU_BAR_E = 2, 7959 HTT_11AX_TRIGGER_MU_RTS_E = 3, 7960 HTT_11AX_TRIGGER_BUFFER_SIZE_E = 4, 7961 HTT_11AX_TRIGGER_GCR_MU_BAR_E = 5, 7962 HTT_11AX_TRIGGER_BQRP_E = 6, 7963 HTT_11AX_TRIGGER_NDP_FB_REPORT_POLL_E = 7, 7964 HTT_11AX_TRIGGER_RESERVED_8_E = 8, 7965 HTT_11AX_TRIGGER_RESERVED_9_E = 9, 7966 HTT_11AX_TRIGGER_RESERVED_10_E = 10, 7967 HTT_11AX_TRIGGER_RESERVED_11_E = 11, 7968 HTT_11AX_TRIGGER_RESERVED_12_E = 12, 7969 HTT_11AX_TRIGGER_RESERVED_13_E = 13, 7970 HTT_11AX_TRIGGER_RESERVED_14_E = 14, 7971 HTT_11AX_TRIGGER_RESERVED_15_E = 15, 7972 HTT_STA_UL_OFDMA_NUM_11AX_TRIG_TYPE, 7973 } HTT_STA_UL_OFDMA_11AX_TRIG_TYPE; 7974 7975 /* UL RESP Queues 0 - HIPRI, 1 - LOPRI & 2 - BSR */ 7976 #define HTT_STA_UL_OFDMA_NUM_UL_QUEUES 3 7977 /* Actual resp type sent by STA for trigger 7978 * 0 - HE TB PPDU, 1 - NULL Delimiter */ 7979 #define HTT_STA_UL_OFDMA_NUM_RESP_END_TYPE 2 7980 /* Counter for MCS 0-13 */ 7981 #define HTT_STA_UL_OFDMA_NUM_MCS_COUNTERS 14 7982 /* Counters BW 20,40,80,160,320 */ 7983 #define HTT_STA_UL_OFDMA_NUM_BW_COUNTERS 5 7984 #define HTT_STA_UL_OFDMA_NUM_REDUCED_CHAN_TYPES 2 /* 0 - Half, 1 - Quarter */ 7985 7986 /* STATS_TYPE : HTT_DBG_EXT_STA_11AX_UL_STATS 7987 * TLV_TAGS: 7988 * - HTT_STATS_STA_UL_OFDMA_STATS_TAG 7989 */ 7990 typedef struct { 7991 htt_tlv_hdr_t tlv_hdr; 7992 7993 A_UINT32 pdev_id; 7994 7995 /** 7996 * Trigger Type reported by HWSCH on RX reception 7997 * Each index populate enum HTT_STA_UL_OFDMA_RX_TRIG_TYPE 7998 */ 7999 A_UINT32 rx_trigger_type[HTT_STA_UL_OFDMA_NUM_TRIG_TYPE]; 8000 /** 8001 * 11AX Trigger Type on RX reception 8002 * Each index populate enum HTT_STA_UL_OFDMA_11AX_TRIG_TYPE 8003 */ 8004 A_UINT32 ax_trigger_type[HTT_STA_UL_OFDMA_NUM_11AX_TRIG_TYPE]; 8005 8006 /** Num data PPDUs/Delims responded to trigs. per HWQ for UL RESP */ 8007 A_UINT32 num_data_ppdu_responded_per_hwq[HTT_STA_UL_OFDMA_NUM_UL_QUEUES]; 8008 A_UINT32 num_null_delimiters_responded_per_hwq[HTT_STA_UL_OFDMA_NUM_UL_QUEUES]; 8009 /** 8010 * Overall UL STA RESP Status 0 - HE TB PPDU, 1 - NULL Delimiter 8011 * Super set of num_data_ppdu_responded_per_hwq, 8012 * num_null_delimiters_responded_per_hwq 8013 */ 8014 A_UINT32 num_total_trig_responses[HTT_STA_UL_OFDMA_NUM_RESP_END_TYPE]; 8015 8016 /** 8017 * Time interval between current time ms and last successful trigger RX 8018 * 0xFFFFFFFF denotes no trig received / timestamp roll back 8019 */ 8020 A_UINT32 last_trig_rx_time_delta_ms; 8021 8022 /** 8023 * Rate Statistics for UL OFDMA 8024 * UL TB PPDU TX MCS, NSS, GI, BW from STA HWQ 8025 */ 8026 A_UINT32 ul_ofdma_tx_mcs[HTT_STA_UL_OFDMA_NUM_MCS_COUNTERS]; 8027 A_UINT32 ul_ofdma_tx_nss[HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS]; 8028 A_UINT32 ul_ofdma_tx_gi[HTT_TX_PDEV_STATS_NUM_GI_COUNTERS][HTT_STA_UL_OFDMA_NUM_MCS_COUNTERS]; 8029 A_UINT32 ul_ofdma_tx_ldpc; 8030 A_UINT32 ul_ofdma_tx_bw[HTT_STA_UL_OFDMA_NUM_BW_COUNTERS]; 8031 8032 /** Trig based PPDU TX/ RBO based PPDU TX Count */ 8033 A_UINT32 trig_based_ppdu_tx; 8034 A_UINT32 rbo_based_ppdu_tx; 8035 /** Switch MU EDCA to SU EDCA Count */ 8036 A_UINT32 mu_edca_to_su_edca_switch_count; 8037 /** Num MU EDCA applied Count */ 8038 A_UINT32 num_mu_edca_param_apply_count; 8039 8040 /** 8041 * Current MU EDCA Parameters for WMM ACs 8042 * Mode - 0 - SU EDCA, 1- MU EDCA 8043 */ 8044 A_UINT32 current_edca_hwq_mode[HTT_NUM_AC_WMM]; 8045 /** Contention Window minimum. Range: 1 - 10 */ 8046 A_UINT32 current_cw_min[HTT_NUM_AC_WMM]; 8047 /** Contention Window maximum. Range: 1 - 10 */ 8048 A_UINT32 current_cw_max[HTT_NUM_AC_WMM]; 8049 /** AIFS value - 0 -255 */ 8050 A_UINT32 current_aifs[HTT_NUM_AC_WMM]; 8051 A_UINT32 reduced_ul_ofdma_tx_bw[HTT_STA_UL_OFDMA_NUM_REDUCED_CHAN_TYPES][HTT_STA_UL_OFDMA_NUM_BW_COUNTERS]; 8052 } htt_stats_sta_ul_ofdma_stats_tlv; 8053 /* preserve old name alias for new name consistent with the tag name */ 8054 typedef htt_stats_sta_ul_ofdma_stats_tlv htt_sta_ul_ofdma_stats_tlv; 8055 8056 /* NOTE: 8057 * This structure is for documentation, and cannot be safely used directly. 8058 * Instead, use the constituent TLV structures to fill/parse. 8059 */ 8060 #ifdef ATH_TARGET 8061 typedef struct { 8062 htt_stats_sta_ul_ofdma_stats_tlv ul_ofdma_sta_stats; 8063 } htt_sta_11ax_ul_stats_t; 8064 #endif /* ATH_TARGET */ 8065 8066 typedef struct { 8067 htt_tlv_hdr_t tlv_hdr; 8068 /** No of Fine Timing Measurement frames transmitted successfully */ 8069 A_UINT32 tx_ftm_suc; 8070 /** 8071 * No of Fine Timing Measurement frames transmitted successfully 8072 * after retry 8073 */ 8074 A_UINT32 tx_ftm_suc_retry; 8075 /** No of Fine Timing Measurement frames not transmitted successfully */ 8076 A_UINT32 tx_ftm_fail; 8077 /** 8078 * No of Fine Timing Measurement Request frames received, 8079 * including initial, non-initial, and duplicates 8080 */ 8081 A_UINT32 rx_ftmr_cnt; 8082 /** 8083 * No of duplicate Fine Timing Measurement Request frames received, 8084 * including both initial and non-initial 8085 */ 8086 A_UINT32 rx_ftmr_dup_cnt; 8087 /** No of initial Fine Timing Measurement Request frames received */ 8088 A_UINT32 rx_iftmr_cnt; 8089 /** 8090 * No of duplicate initial Fine Timing Measurement Request frames received 8091 */ 8092 A_UINT32 rx_iftmr_dup_cnt; 8093 /** No of responder sessions rejected when initiator was active */ 8094 A_UINT32 initiator_active_responder_rejected_cnt; 8095 /** Responder terminate count */ 8096 A_UINT32 responder_terminate_cnt; 8097 A_UINT32 vdev_id; 8098 } htt_stats_vdev_rtt_resp_stats_tlv; 8099 /* preserve old name alias for new name consistent with the tag name */ 8100 typedef htt_stats_vdev_rtt_resp_stats_tlv htt_vdev_rtt_resp_stats_tlv; 8101 8102 #ifdef ATH_TARGET 8103 typedef struct { 8104 htt_stats_vdev_rtt_resp_stats_tlv vdev_rtt_resp_stats; 8105 } htt_vdev_rtt_resp_stats_t; 8106 #endif /* ATH_TARGET */ 8107 8108 typedef struct { 8109 htt_tlv_hdr_t tlv_hdr; 8110 8111 A_UINT32 vdev_id; 8112 /** 8113 * No of Fine Timing Measurement request frames transmitted successfully 8114 */ 8115 A_UINT32 tx_ftmr_cnt; 8116 /** 8117 * No of Fine Timing Measurement request frames not transmitted successfully 8118 */ 8119 A_UINT32 tx_ftmr_fail; 8120 /** 8121 * No of Fine Timing Measurement request frames transmitted successfully 8122 * after retry 8123 */ 8124 A_UINT32 tx_ftmr_suc_retry; 8125 /** 8126 * No of Fine Timing Measurement frames received, including initial, 8127 * non-initial, and duplicates 8128 */ 8129 A_UINT32 rx_ftm_cnt; 8130 /** Initiator Terminate count */ 8131 A_UINT32 initiator_terminate_cnt; 8132 /** Debug count to check the Measurement request from host */ 8133 A_UINT32 tx_meas_req_count; 8134 } htt_stats_vdev_rtt_init_stats_tlv; 8135 /* preserve old name alias for new name consistent with the tag name */ 8136 typedef htt_stats_vdev_rtt_init_stats_tlv htt_vdev_rtt_init_stats_tlv; 8137 8138 #ifdef ATH_TARGET 8139 typedef struct { 8140 htt_stats_vdev_rtt_init_stats_tlv vdev_rtt_init_stats; 8141 } htt_vdev_rtt_init_stats_t; 8142 #endif /* ATH_TARGET */ 8143 8144 8145 #define HTT_STATS_MAX_SCH_CMD_RESULT 25 8146 8147 /* TXSEND self generated frames */ 8148 typedef enum { 8149 HTT_TXSEND_FTYPE_SGEN_TF_POLL, 8150 HTT_TXSEND_FTYPE_SGEN_TF_SOUND, 8151 HTT_TXSEND_FTYPE_SGEN_TBR_NDPA, 8152 HTT_TXSEND_FTYPE_SGEN_TBR_NDP, 8153 HTT_TXSEND_FTYPE_SGEN_TBR_LMR, 8154 HTT_TXSEND_FTYPE_SGEN_TF_REPORT, 8155 8156 HTT_TXSEND_FTYPE_MAX 8157 } 8158 htt_stats_txsend_ftype_t; 8159 8160 typedef struct { 8161 htt_tlv_hdr_t tlv_hdr; 8162 /* 11AZ TBR SU Stats */ 8163 A_UINT32 tbr_su_ftype_queued[HTT_TXSEND_FTYPE_MAX]; 8164 /* 11AZ TBR MU Stats */ 8165 A_UINT32 tbr_mu_ftype_queued[HTT_TXSEND_FTYPE_MAX]; 8166 } htt_stats_pdev_rtt_tbr_selfgen_queued_stats_tlv; 8167 8168 typedef struct { 8169 htt_tlv_hdr_t tlv_hdr; 8170 /** tbr_num_sch_cmd_result_buckets: 8171 * Number of sch cmd results buckets in use per chip 8172 * Each bucket contains the counter of the number of times that bucket 8173 * index was seen in the sch_cmd_result. The last bucket will capture 8174 * the count of sch_cmd_result matching the last bucket index and the 8175 * count of all the sch_cmd_results that exceeded the last bucket index 8176 * value. 8177 * tbr_num_sch_cmd_result_buckets must be <= HTT_STATS_MAX_SCH_CMD_RESULT 8178 */ 8179 A_UINT32 tbr_num_sch_cmd_result_buckets; 8180 /* cmd result status for SU frames in case of TB ranging */ 8181 A_UINT32 opaque_tbr_su_ftype_cmd_result[HTT_TXSEND_FTYPE_MAX][HTT_STATS_MAX_SCH_CMD_RESULT]; 8182 /* cmd result status for MU frames in case of TB ranging */ 8183 A_UINT32 opaque_tbr_mu_ftype_cmd_result[HTT_TXSEND_FTYPE_MAX][HTT_STATS_MAX_SCH_CMD_RESULT]; 8184 } htt_stats_pdev_rtt_tbr_cmd_result_stats_tlv; 8185 8186 typedef struct { 8187 htt_tlv_hdr_t tlv_hdr; 8188 /** ista_ranging_ndpa_cnt: 8189 * Indicates the number of Ranging NDPA sent successfully. 8190 */ 8191 A_UINT32 ista_ranging_ndpa_cnt; 8192 /** ista_ranging_ndp_cnt: 8193 * Indicates the number of Ranging NDP sent successfully. 8194 */ 8195 A_UINT32 ista_ranging_ndp_cnt; 8196 /** ista_ranging_i2r_lmr_cnt: 8197 * Indicates the number of Ranging I2R LMR sent successfully. 8198 */ 8199 A_UINT32 ista_ranging_i2r_lmr_cnt; 8200 /** rtsa_ranging_resp_cnt 8201 * Indicates the number of times RXPCU initiates a Ranging response 8202 * as a RSTA. 8203 */ 8204 A_UINT32 rtsa_ranging_resp_cnt; 8205 /** rtsa_ranging_ndp_cnt: 8206 * Indicates the number of Ranging NDP response sent successfully. 8207 */ 8208 A_UINT32 rtsa_ranging_ndp_cnt; 8209 /** rsta_ranging_lmr_cnt: 8210 * Indicates the number of Ranging R2I LMR response sent successfully. 8211 */ 8212 A_UINT32 rsta_ranging_lmr_cnt; 8213 /** tb_ranging_cts2s_rcvd_cnt: 8214 * Indicates the number of expected CTS2S response received for TF Poll 8215 * sent. 8216 */ 8217 A_UINT32 tb_ranging_cts2s_rcvd_cnt; 8218 /** tb_ranging_ndp_rcvd_cnt: 8219 * Indicates the number of expected NDP response received for TF Sound 8220 * or Secure Sound sent. 8221 */ 8222 A_UINT32 tb_ranging_ndp_rcvd_cnt; 8223 /** tb_ranging_lmr_rcvd_cnt: 8224 * Indicates the number of expected LMR response received for TF Report 8225 * sent. 8226 */ 8227 A_UINT32 tb_ranging_lmr_rcvd_cnt; 8228 /** tb_ranging_tf_poll_resp_sent_cnt: 8229 * Indicates the number of successful responses sent for TF Poll 8230 * received. 8231 */ 8232 A_UINT32 tb_ranging_tf_poll_resp_sent_cnt; 8233 /** tb_ranging_tf_sound_resp_sent_cnt: 8234 * Indicates the number of successful responses sent for TF Sound 8235 * (or Secure) received. 8236 */ 8237 A_UINT32 tb_ranging_tf_sound_resp_sent_cnt; 8238 /** tb_ranging_tf_report_resp_sent_cnt: 8239 * Indicates the number of successful responses sent for TF Report 8240 * received. 8241 */ 8242 A_UINT32 tb_ranging_tf_report_resp_sent_cnt; 8243 } htt_stats_pdev_rtt_hw_stats_tlv; 8244 8245 typedef struct { 8246 htt_tlv_hdr_t tlv_hdr; 8247 A_UINT32 pdev_id; 8248 /** tx_11mc_ftm_suc: 8249 * Number of 11mc Fine Timing Measurement frames transmitted successfully. 8250 */ 8251 A_UINT32 tx_11mc_ftm_suc; 8252 /** tx_11mc_ftm_suc_retry: 8253 * Number of Fine Timing Measurement frames transmitted successfully 8254 * after retrying. 8255 */ 8256 A_UINT32 tx_11mc_ftm_suc_retry; 8257 /** tx_11mc_ftm_fail: 8258 * Number of Fine Timing Measurement frames not transmitted successfully. 8259 */ 8260 A_UINT32 tx_11mc_ftm_fail; 8261 /** rx_11mc_ftmr_cnt: 8262 * Number of FTMR frames received, including initial, non-initial, 8263 * and duplicates. 8264 */ 8265 A_UINT32 rx_11mc_ftmr_cnt; 8266 /** rx_11mc_ftmr_dup_cnt: 8267 * Number of duplicate Fine Timing Measurement Request frames received, 8268 * including both initial and non-initial. 8269 */ 8270 A_UINT32 rx_11mc_ftmr_dup_cnt; 8271 /** rx_11mc_iftmr_cnt: 8272 * Number of initial Fine Timing Measurement Request frames received. 8273 */ 8274 A_UINT32 rx_11mc_iftmr_cnt; 8275 /** rx_11mc_iftmr_dup_cnt: 8276 * Number of duplicate initial Fine Timing Measurement Request frames 8277 * received. 8278 */ 8279 A_UINT32 rx_11mc_iftmr_dup_cnt; 8280 /** ftmr_drop_11mc_resp_role_not_enabled_cnt: 8281 * Number of FTMR frames dropped as 11mc is not supported for this VAP. 8282 */ 8283 A_UINT32 ftmr_drop_11mc_resp_role_not_enabled_cnt; 8284 /** initiator_active_responder_rejected_cnt: 8285 * Number of responder sessions rejected when initiator was active. 8286 */ 8287 A_UINT32 initiator_active_responder_rejected_cnt; 8288 /** responder_terminate_cnt: 8289 * Number of times Responder session got terminated. 8290 */ 8291 A_UINT32 responder_terminate_cnt; 8292 /** active_rsta_open: 8293 * Number of active responder contexts in open mode. 8294 */ 8295 A_UINT32 active_rsta_open; 8296 /** active_rsta_mac: 8297 * Number of active responder contexts in mac security mode. 8298 */ 8299 A_UINT32 active_rsta_mac; 8300 /** active_rsta_mac_phy: 8301 * Number of active responder contexts in mac_phy security mode. 8302 */ 8303 A_UINT32 active_rsta_mac_phy; 8304 /** num_assoc_ranging_peers: 8305 * Number of active associated ISTA ranging peers. 8306 */ 8307 A_UINT32 num_assoc_ranging_peers; 8308 /** num_unassoc_ranging_peers: 8309 * Number of active un-associated ISTA ranging peers. 8310 */ 8311 A_UINT32 num_unassoc_ranging_peers; 8312 /** responder_alloc_cnt: 8313 * Number of responder contexts allocated. 8314 */ 8315 A_UINT32 responder_alloc_cnt; 8316 /** responder_alloc_failure: 8317 * Number of times responder context failed to be allocated. 8318 */ 8319 A_UINT32 responder_alloc_failure; 8320 /** pn_check_failure_cnt: 8321 * Number of times PN check failed. 8322 */ 8323 A_UINT32 pn_check_failure_cnt; 8324 /** pasn_m1_auth_recv_cnt: 8325 * Num of M1 auth frames received for PASN over the air from iSTA. 8326 */ 8327 A_UINT32 pasn_m1_auth_recv_cnt; 8328 /** pasn_m1_auth_drop_cnt: 8329 * Number of M1 auth frames received for PASN over the air from iSTA 8330 * but dropped in FW due to any reason (such as unavailability of 8331 * responder ctxt or any other check). 8332 */ 8333 A_UINT32 pasn_m1_auth_drop_cnt; 8334 /** pasn_m2_auth_recv_cnt: 8335 * Number of M2 auth frames received in FW for PASN from Host driver. 8336 */ 8337 A_UINT32 pasn_m2_auth_recv_cnt; 8338 /** pasn_m2_auth_tx_fail_cnt: 8339 * Number of M2 auth frames received in FW but Tx failed. 8340 */ 8341 A_UINT32 pasn_m2_auth_tx_fail_cnt; 8342 /** pasn_m3_auth_recv_cnt: 8343 * Number of M3 auth frames received for PASN. 8344 */ 8345 A_UINT32 pasn_m3_auth_recv_cnt; 8346 /** pasn_m3_auth_drop_cnt: 8347 * Number of M3 auth frames received for PASN over the air from iSTA but 8348 * dropped in FW due to any reason. 8349 */ 8350 A_UINT32 pasn_m3_auth_drop_cnt; 8351 /** pasn_peer_create_request_cnt: 8352 * Number of times FW requested PASN peer create request to Host. 8353 */ 8354 A_UINT32 pasn_peer_create_request_cnt; 8355 /** pasn_peer_create_timeout_cnt: 8356 * Number of times PASN peer was not created within timeout period. 8357 */ 8358 A_UINT32 pasn_peer_create_timeout_cnt; 8359 /** pasn_peer_created_cnt: 8360 * Number of times Host sent PASN peer create request to FW. 8361 */ 8362 A_UINT32 pasn_peer_created_cnt; 8363 /** sec_ranging_not_supported_mfp_not_setup: 8364 * management frame protection not setup, drop secure ranging request. 8365 */ 8366 A_UINT32 sec_ranging_not_supported_mfp_not_setup; 8367 /** non_sec_ranging_discarded_for_assoc_peer_with_mfpr_set: 8368 * Non secured ranging request discarded for Assoc peer with MFPR set. 8369 */ 8370 A_UINT32 non_sec_ranging_discarded_for_assoc_peer_with_mfpr_set; 8371 /** open_ranging_discarded_with_URNM_MFPR_set_for_pasn_peer: 8372 * Failure in case non-secured frame is received for PASN peer and 8373 * URNM_MFPR is set. 8374 */ 8375 A_UINT32 open_ranging_discarded_with_URNM_MFPR_set_for_pasn_peer; 8376 /** unassoc_non_pasn_ranging_not_supported_with_URNM_MFPR: 8377 * Failure in case non-assoc/non-PASN sta is sending open FTMR and 8378 * RSTA does not support un-secured ranging. 8379 */ 8380 A_UINT32 unassoc_non_pasn_ranging_not_supported_with_URNM_MFPR; 8381 /** num_req_bw_20_MHz: 8382 * Number of requests with BW 20 MHz. 8383 */ 8384 A_UINT32 num_req_bw_20_MHz; 8385 /** num_req_bw_40_MHz: 8386 * Number of requests with BW 40 MHz. 8387 */ 8388 A_UINT32 num_req_bw_40_MHz; 8389 /** num_req_bw_80_MHz: 8390 * Number of requests with BW 80 MHz. 8391 */ 8392 A_UINT32 num_req_bw_80_MHz; 8393 /** num_req_bw_160_MHz: 8394 * Number of requests with BW 160 MHz. 8395 */ 8396 A_UINT32 num_req_bw_160_MHz; 8397 /** tx_11az_ftm_successful: 8398 * Number of 11AZ FTM frames transmitted successfully. 8399 */ 8400 A_UINT32 tx_11az_ftm_successful; 8401 /** tx_11az_ftm_failed: 8402 * Number of 11AZ FTM frames for which Tx failed. 8403 */ 8404 A_UINT32 tx_11az_ftm_failed; 8405 /** rx_11az_ftmr_cnt: 8406 * Number of 11AZ FTM frames received. 8407 */ 8408 A_UINT32 rx_11az_ftmr_cnt; 8409 /** rx_11az_ftmr_dup_cnt: 8410 * Number of duplicate 11az ftmr frames dropped. 8411 */ 8412 A_UINT32 rx_11az_ftmr_dup_cnt; 8413 /** rx_11az_iftmr_dup_cnt: 8414 * Number of duplicate 11az iftmr frames dropped. 8415 */ 8416 A_UINT32 rx_11az_iftmr_dup_cnt; 8417 /** malformed_ftmr: 8418 * Number of malformed FTMR frames received from client leading to 8419 * frame parse error. 8420 */ 8421 A_UINT32 malformed_ftmr; 8422 /** ftmr_drop_ntb_resp_role_not_enabled_cnt: 8423 * Number of FTMR frames dropped as NTB is not supported for this VAP. 8424 */ 8425 A_UINT32 ftmr_drop_ntb_resp_role_not_enabled_cnt; 8426 /** ftmr_drop_tb_resp_role_not_enabled_cnt: 8427 * Number of FTMR frames dropped as TB is not supported for this VAP. 8428 */ 8429 A_UINT32 ftmr_drop_tb_resp_role_not_enabled_cnt; 8430 /** invalid_ftm_request_params: 8431 * Number of FTMR frames received with invalid params. 8432 */ 8433 A_UINT32 invalid_ftm_request_params; 8434 /** requested_bw_format_not_supported: 8435 * FTMR rejected as requested format is lower or higher than AP's 8436 * capability, or unknown. 8437 */ 8438 A_UINT32 requested_bw_format_not_supported; 8439 /** ntb_unsec_unassoc_mode_ranging_peer_alloc_failed: 8440 * AST entry creation failed for NTB unsecured mode. 8441 */ 8442 A_UINT32 ntb_unsec_unassoc_mode_ranging_peer_alloc_failed; 8443 /** tb_unassoc_unsec_mode_pasn_peer_creation_failed: 8444 * PASN peer creation failed for unsecured mode TBR. 8445 */ 8446 A_UINT32 tb_unassoc_unsec_mode_pasn_peer_creation_failed; 8447 /** num_ranging_sequences_processed: 8448 * Number of ranging sequences processed for NTB and TB. 8449 */ 8450 A_UINT32 num_ranging_sequences_processed; 8451 /** Number of NDPs transmitted for NTBR */ 8452 A_UINT32 ntb_tx_ndp; 8453 A_UINT32 ndp_rx_cnt; 8454 /** Number of NDPAs received for 11AZ NTB ranging */ 8455 A_UINT32 num_ntb_ranging_NDPAs_recv; 8456 /** Number of LMR frames received */ 8457 A_UINT32 recv_lmr; 8458 /** invalid_ftmr_cnt: 8459 * Number of invalid FTMR frames received 8460 * iftmr with null ie element is invalid 8461 * The Frame is valid if any of the following combination is present: 8462 * a. LCI sub ie + parameter ie 8463 * b. LCR sub ie + parameter ie 8464 * c. parameter ie 8465 * d. LCI sub ie + LCR sub ie + parameter ie 8466 */ 8467 A_UINT32 invalid_ftmr_cnt; 8468 /** Number of times the 'max time b/w measurement' timer got expired */ 8469 A_UINT32 max_time_bw_meas_exp_cnt; 8470 } htt_stats_pdev_rtt_resp_stats_tlv; 8471 8472 /* STATS_TYPE: HTT_DBG_EXT_PDEV_RTT_RESP_STATS 8473 * TLV_TAGS: 8474 * HTT_STATS_PDEV_RTT_RESP_STATS_TAG 8475 * HTT_STATS_PDEV_RTT_HW_STATS_TAG 8476 * HTT_STATS_PDEV_RTT_TBR_SELFGEN_QUEUED_STATS_TAG 8477 * HTT_STATS_PDEV_RTT_TBR_CMD_RESULT_STATS_TAG 8478 */ 8479 #ifdef ATH_TARGET 8480 typedef struct { 8481 htt_stats_pdev_rtt_resp_stats_tlv pdev_rtt_resp_stats; 8482 htt_stats_pdev_rtt_hw_stats_tlv pdev_rtt_hw_stats; 8483 htt_stats_pdev_rtt_tbr_selfgen_queued_stats_tlv pdev_rtt_tbr_selfgen_queued_stats; 8484 htt_stats_pdev_rtt_tbr_cmd_result_stats_tlv pdev_rtt_tbr_cmd_result_stats; 8485 } htt_pdev_rtt_resp_stats_t; 8486 #endif /* ATH_TARGET */ 8487 8488 typedef struct { 8489 htt_tlv_hdr_t tlv_hdr; 8490 A_UINT32 pdev_id; 8491 /** tx_11mc_ftmr_cnt: 8492 * Number of 11mc Fine Timing Measurement request frames transmitted 8493 * successfully. 8494 */ 8495 A_UINT32 tx_11mc_ftmr_cnt; 8496 /** tx_11mc_ftmr_fail: 8497 * Number of 11mc Fine Timing Measurement request frames not transmitted 8498 * successfully. 8499 */ 8500 A_UINT32 tx_11mc_ftmr_fail; 8501 /** tx_11mc_ftmr_suc_retry: 8502 * Number of 11mc Fine Timing Measurement request frames transmitted 8503 * successfully after retrying. 8504 */ 8505 A_UINT32 tx_11mc_ftmr_suc_retry; 8506 /** rx_11mc_ftm_cnt: 8507 * Number of 11mc Fine Timing Measurement frames received, including 8508 * initial, non-initial, and duplicates. 8509 */ 8510 A_UINT32 rx_11mc_ftm_cnt; 8511 /** Count of Ranging Measurement requests received from host */ 8512 A_UINT32 tx_meas_req_count; 8513 /** Initiator role not supported on the vdev */ 8514 A_UINT32 init_role_not_enabled; 8515 /** Number of times Initiator context got terminated */ 8516 A_UINT32 initiator_terminate_cnt; 8517 /** Number of times Tx of FTMR failed */ 8518 A_UINT32 tx_11az_ftmr_fail; 8519 /** tx_11az_ftmr_start: 8520 * Number of Fine Timing Measurement start requests transmitted 8521 * successfully. 8522 */ 8523 A_UINT32 tx_11az_ftmr_start; 8524 /** tx_11az_ftmr_stop: 8525 * Number of Fine Timing Measurement stop requests transmitted 8526 * successfully. 8527 */ 8528 A_UINT32 tx_11az_ftmr_stop; 8529 /** Number of FTM frames received successfully */ 8530 A_UINT32 rx_11az_ftm_cnt; 8531 /** Number of active ISTA sessions */ 8532 A_UINT32 active_ista; 8533 /** HE preamble not enabled on Initiator side */ 8534 A_UINT32 invalid_preamble; 8535 /** Initiator invalid channel bw format */ 8536 A_UINT32 invalid_chan_bw_format; 8537 /* mgmt_buff_alloc_fail_cnt Management Buffer allocation failure count */ 8538 A_UINT32 mgmt_buff_alloc_fail_cnt; 8539 /** ftm_parse_failure: 8540 * Count of FTM frame IE parse failure or RSTA sending measurement 8541 * negotiation failure. 8542 */ 8543 A_UINT32 ftm_parse_failure; 8544 /** Count of NTB/TB ranging negotiation completed successfully */ 8545 A_UINT32 ranging_negotiation_successful_cnt; 8546 /** incompatible_ftm_params: 8547 * Number of occurrences of failure due to incompatible parameters 8548 * suggested by rSTA during negotiation. 8549 */ 8550 A_UINT32 incompatible_ftm_params; 8551 /** sec_ranging_req_in_open_mode: 8552 * Number of occurrences of failure if BSS peer exists in open mode and 8553 * secured mode RTT ranging is requested. 8554 */ 8555 A_UINT32 sec_ranging_req_in_open_mode; 8556 /** ftmr_tx_failed_null_11az_peer: 8557 * Number of occurrences where FTMR was not transmitted as there was 8558 * no 11AZ peer. 8559 */ 8560 A_UINT32 ftmr_tx_failed_null_11az_peer; 8561 /** Number of times ftmr retry timed out */ 8562 A_UINT32 ftmr_retry_timeout; 8563 /** Number of times the 'max time b/w measurement' timer got expired */ 8564 A_UINT32 max_time_bw_meas_exp_cnt; 8565 /** tb_meas_duration_expiry_cnt: 8566 * Number of times TBR measurement duration expired. 8567 */ 8568 A_UINT32 tb_meas_duration_expiry_cnt; 8569 /** num_tb_ranging_requests: 8570 * Number of TB ranging requests ready for negotiation. 8571 */ 8572 A_UINT32 num_tb_ranging_requests; 8573 /** Number of times NTB ranging was triggered successfully */ 8574 A_UINT32 ntbr_triggered_successfully; 8575 /** Number of times NTB ranging failed to be triggered */ 8576 A_UINT32 ntbr_trigger_failed; 8577 /** No valid index found for programming vreg settings */ 8578 A_UINT32 invalid_or_no_vreg_idx; 8579 /** Number of times VREG setting failed */ 8580 A_UINT32 set_vreg_params_failed; 8581 /** Number of occurrences of SAC mismatch */ 8582 A_UINT32 sac_mismatch; 8583 /** pasn_m1_auth_recv_cnt: 8584 * Number of M1 auth frames received for PASN from Host. 8585 */ 8586 A_UINT32 pasn_m1_auth_recv_cnt; 8587 /** pasn_m1_auth_tx_fail_cnt: 8588 * Number of M1 auth frames received in FW but Tx failed. 8589 */ 8590 A_UINT32 pasn_m1_auth_tx_fail_cnt; 8591 /** pasn_m2_auth_recv_cnt: 8592 * Number of M2 auth frames received in FW for PASN over the air from rSTA. 8593 */ 8594 A_UINT32 pasn_m2_auth_recv_cnt; 8595 /** pasn_m2_auth_drop_cnt: 8596 * Number of M2 auth frames received in FW but dropped due to any reason. 8597 */ 8598 A_UINT32 pasn_m2_auth_drop_cnt; 8599 /** pasn_m3_auth_recv_cnt: 8600 * Number of M3 auth frames received for PASN from Host. 8601 */ 8602 A_UINT32 pasn_m3_auth_recv_cnt; 8603 /** pasn_m3_auth_tx_fail_cnt: 8604 * Number of M3 auth frames received in FW but Tx failed. 8605 */ 8606 A_UINT32 pasn_m3_auth_tx_fail_cnt; 8607 /** pasn_peer_create_request_cnt: 8608 * Number of times FW requested PASN peer create request to Host. 8609 */ 8610 A_UINT32 pasn_peer_create_request_cnt; 8611 /** pasn_peer_create_timeout_cnt: 8612 * Number of times PASN peer was not created within timeout period. 8613 */ 8614 A_UINT32 pasn_peer_create_timeout_cnt; 8615 /** pasn_peer_created_cnt: 8616 * Number of times Host sent PASN peer create request to FW. 8617 */ 8618 A_UINT32 pasn_peer_created_cnt; 8619 /** Number of occurrences of Tx of NDPA failing */ 8620 A_UINT32 ntbr_ndpa_failed; 8621 /** ntbr_sequence_successful: 8622 * The NDPA, NDP and LMR exchanges are successful and sched cmd status 8623 * is 0. 8624 */ 8625 A_UINT32 ntbr_sequence_successful; 8626 /** ntbr_ndp_failed: 8627 * Number of occurrences of NDPA being transmitted successfully 8628 * but NDP failing for NTB ranging. 8629 */ 8630 A_UINT32 ntbr_ndp_failed; 8631 /** sch_cmd_status_cnts: 8632 * Elements 0-7 count the number of times the sch_cmd_status was equal to 8633 * the corresponding value of the index of the array sch_cmd_status_cnts[], 8634 * and element 8 counts the numbers of times the status was some other 8635 * value >=8. 8636 */ 8637 A_UINT32 sch_cmd_status_cnts[9]; 8638 /** Number of times LMR reception timed out */ 8639 A_UINT32 lmr_timeout; 8640 /** Number of LMR frames received */ 8641 A_UINT32 lmr_recv; 8642 /** Number of trigger frames received */ 8643 A_UINT32 num_trigger_frames_received; 8644 /** Number of NDPAs received for TBR */ 8645 A_UINT32 num_tb_ranging_NDPAs_recv; 8646 /** Number of ranging NDPs received for NTBR/TB */ 8647 A_UINT32 ndp_rx_cnt; 8648 } htt_stats_pdev_rtt_init_stats_tlv; 8649 8650 /* STATS_TYPE: HTT_DBG_EXT_PDEV_RTT_INITIATOR_STATS 8651 * TLV_TAGS: 8652 * HTT_STATS_PDEV_RTT_INIT_STATS_TAG 8653 * HTT_STATS_PDEV_RTT_HW_STATS_TAG 8654 */ 8655 #ifdef ATH_TARGET 8656 typedef struct { 8657 htt_stats_pdev_rtt_init_stats_tlv pdev_rtt_init_stats; 8658 htt_stats_pdev_rtt_hw_stats_tlv pdev_rtt_hw_stats; 8659 } htt_pdev_rtt_init_stats_t; 8660 #endif /* ATH_TARGET */ 8661 8662 enum { 8663 HTT_STATS_WIFI_RADAR_CAL_TYPE_NONE = 0, 8664 HTT_STATS_WIFI_RADAR_CAL_TYPE_GAIN_BINARY_SEARCH = 1, 8665 HTT_STATS_WIFI_RADAR_CAL_TYPE_TX_GAIN_BINARY_SEARCH = 2, 8666 HTT_STATS_WIFI_RADAR_CAL_TYPE_RECAL_GAIN_VALIDATION = 3, 8667 HTT_STATS_WIFI_RADAR_CAL_TYPE_RECAL_GAIN_BINARY_SEARCH = 4, 8668 /* the value 5 is reserved for future use */ 8669 8670 HTT_STATS_NUM_WIFI_RADAR_CAL_TYPES = 6 8671 }; 8672 8673 enum { 8674 HTT_STATS_WIFI_RADAR_CAL_FAILURE_NONE = 0, 8675 HTT_STATS_WIFI_RADAR_CAL_FAILURE_DPD_ABORT = 1, 8676 HTT_STATS_WIFI_RADAR_CAL_FAILURE_CONVERGENCE = 2, 8677 HTT_STATS_WIFI_RADAR_CAL_FAILURE_TX_EXCEEDS_RETRY = 3, 8678 HTT_STATS_WIFI_RADAR_CAL_FAILURE_CAPTURE = 4, 8679 HTT_STATS_WIFI_RADAR_CAL_FAILURE_NEW_CHANNEL_CHANGE = 5, 8680 HTT_STATS_WIFI_RADAR_CAL_FAILURE_NEW_CAL_REQ = 6, 8681 /* the values 7-9 are reserved for future use */ 8682 8683 HTT_STATS_NUM_WIFI_RADAR_CAL_FAILURE_REASONS = 10 8684 }; 8685 8686 typedef struct { 8687 htt_tlv_hdr_t tlv_hdr; 8688 A_UINT32 capture_in_progress; 8689 A_UINT32 calibration_in_progress; 8690 /* Capture time interval, in ms */ 8691 A_UINT32 periodicity; 8692 /* Last user request timestamp, in ms */ 8693 A_UINT32 latest_req_timestamp; 8694 /* Last target res timestamp, in ms */ 8695 A_UINT32 latest_resp_timestamp; 8696 /* Time taken by last calibration to end, in ms */ 8697 A_UINT32 latest_calibration_timing; 8698 /* Time taken by last calibration to end, in ms for each chain */ 8699 A_UINT32 calibration_timing_per_chain[HTT_STATS_MAX_CHAINS]; 8700 /* To log user request count */ 8701 A_UINT32 wifi_radar_req_count; 8702 /* Total packet success count */ 8703 A_UINT32 num_wifi_radar_pkt_success; 8704 /* Total packet queued count */ 8705 A_UINT32 num_wifi_radar_pkt_queued; 8706 /* Total packet success count during latest calibration alone */ 8707 A_UINT32 num_wifi_radar_cal_pkt_success; 8708 /* Tx Gain Calibration Output - Initial Tx Gain index*/ 8709 A_UINT32 wifi_radar_cal_init_tx_gain; 8710 /* Last Calibration Type, refer to HTT_STATS_WIFI_RADAR_CAL_TYPE_ consts */ 8711 A_UINT32 latest_wifi_radar_cal_type; 8712 /* Calibration Type counters */ 8713 A_UINT32 wifi_radar_cal_type_counts[HTT_STATS_NUM_WIFI_RADAR_CAL_TYPES]; 8714 /* 8715 * Last Calibration Fail Reason, 8716 * refer to HTT_STATS_WIFI_RADAR_CAL_FAILURE_ consts 8717 */ 8718 A_UINT32 latest_wifi_radar_cal_fail_reason; 8719 /* Calibration Fail Reason counters */ 8720 A_UINT32 wifi_radar_cal_fail_reason_counts[HTT_STATS_NUM_WIFI_RADAR_CAL_FAILURE_REASONS]; 8721 /* WiFi Radar Licensed for SKU: 0 - No; 1 - Yes */ 8722 A_UINT32 wifi_radar_licensed; 8723 /* 8724 * cmd result to show failure count of CTS2SELF across MAX_CMD_RESULT 8725 * reasons 8726 */ 8727 A_UINT32 cmd_results_cts2self[HTT_STATS_MAX_SCH_CMD_RESULT]; 8728 /* 8729 * cmd result to show failure count of wifi radar across MAX_CMD_RESULT 8730 * reasons 8731 */ 8732 A_UINT32 cmd_results_wifi_radar[HTT_STATS_MAX_SCH_CMD_RESULT]; 8733 /* Tx gain index from gain table obtained/used for calibration */ 8734 A_UINT32 wifi_radar_tx_gains[HTT_STATS_MAX_CHAINS]; 8735 /* Rx gain index from gain table obtained/used from calibration */ 8736 A_UINT32 wifi_radar_rx_gains[HTT_STATS_MAX_CHAINS][HTT_STATS_MAX_CHAINS]; 8737 } htt_stats_tx_pdev_wifi_radar_tlv; 8738 8739 /* STATS_TYPE : HTT_DBG_EXT_PKTLOG_AND_HTT_RING_STATS 8740 * TLV_TAGS: 8741 * - HTT_STATS_PKTLOG_AND_HTT_RING_STATS_TAG 8742 */ 8743 /* NOTE: 8744 * This structure is for documentation, and cannot be safely used directly. 8745 * Instead, use the constituent TLV structures to fill/parse. 8746 */ 8747 typedef struct { 8748 htt_tlv_hdr_t tlv_hdr; 8749 8750 /** No of pktlog payloads that were dropped in htt_ppdu_stats path */ 8751 A_UINT32 pktlog_lite_drop_cnt; 8752 /** No of pktlog payloads that were dropped in TQM path */ 8753 A_UINT32 pktlog_tqm_drop_cnt; 8754 /** No of pktlog ppdu stats payloads that were dropped */ 8755 A_UINT32 pktlog_ppdu_stats_drop_cnt; 8756 /** No of pktlog ppdu ctrl payloads that were dropped */ 8757 A_UINT32 pktlog_ppdu_ctrl_drop_cnt; 8758 /** No of pktlog sw events payloads that were dropped */ 8759 A_UINT32 pktlog_sw_events_drop_cnt; 8760 } htt_stats_pktlog_and_htt_ring_stats_tlv; 8761 /* preserve old name alias for new name consistent with the tag name */ 8762 typedef htt_stats_pktlog_and_htt_ring_stats_tlv 8763 htt_pktlog_and_htt_ring_stats_tlv; 8764 8765 #define HTT_DLPAGER_STATS_MAX_HIST 10 8766 #define HTT_DLPAGER_ASYNC_LOCKED_PAGE_COUNT_M 0x000000FF 8767 #define HTT_DLPAGER_ASYNC_LOCKED_PAGE_COUNT_S 0 8768 #define HTT_DLPAGER_SYNC_LOCKED_PAGE_COUNT_M 0x0000FF00 8769 #define HTT_DLPAGER_SYNC_LOCKED_PAGE_COUNT_S 8 8770 #define HTT_DLPAGER_TOTAL_LOCKED_PAGES_M 0x0000FFFF 8771 #define HTT_DLPAGER_TOTAL_LOCKED_PAGES_S 0 8772 #define HTT_DLPAGER_TOTAL_FREE_PAGES_M 0xFFFF0000 8773 #define HTT_DLPAGER_TOTAL_FREE_PAGES_S 16 8774 #define HTT_DLPAGER_LAST_LOCKED_PAGE_IDX_M 0x0000FFFF 8775 #define HTT_DLPAGER_LAST_LOCKED_PAGE_IDX_S 0 8776 #define HTT_DLPAGER_LAST_UNLOCKED_PAGE_IDX_M 0xFFFF0000 8777 #define HTT_DLPAGER_LAST_UNLOCKED_PAGE_IDX_S 16 8778 8779 #define HTT_DLPAGER_ASYNC_LOCK_PAGE_COUNT_GET(_var) \ 8780 (((_var) & HTT_DLPAGER_ASYNC_LOCKED_PAGE_COUNT_M) >> \ 8781 HTT_DLPAGER_ASYNC_LOCKED_PAGE_COUNT_S) 8782 #define HTT_STATS_DLPAGER_STATS_DL_PAGER_STATS_ASYNC_LOCK_GET(_var) \ 8783 HTT_DLPAGER_ASYNC_LOCK_PAGE_COUNT_GET(_var) 8784 8785 8786 #define HTT_DLPAGER_ASYNC_LOCK_PAGE_COUNT_SET(_var, _val) \ 8787 do { \ 8788 HTT_CHECK_SET_VAL(HTT_DLPAGER_ASYNC_LOCKED_PAGE_COUNT, _val); \ 8789 ((_var) &= ~(HTT_DLPAGER_ASYNC_LOCKED_PAGE_COUNT_M));\ 8790 ((_var) |= ((_val) << HTT_DLPAGER_ASYNC_LOCKED_PAGE_COUNT_S)); \ 8791 } while (0) 8792 8793 #define HTT_DLPAGER_SYNC_LOCK_PAGE_COUNT_GET(_var) \ 8794 (((_var) & HTT_DLPAGER_SYNC_LOCKED_PAGE_COUNT_M) >> \ 8795 HTT_DLPAGER_SYNC_LOCKED_PAGE_COUNT_S) 8796 #define HTT_STATS_DLPAGER_STATS_DL_PAGER_STATS_SYNC_LOCK_GET(_var) \ 8797 HTT_DLPAGER_SYNC_LOCK_PAGE_COUNT_GET(_var) 8798 8799 #define HTT_DLPAGER_SYNC_LOCK_PAGE_COUNT_SET(_var, _val) \ 8800 do { \ 8801 HTT_CHECK_SET_VAL(HTT_DLPAGER_SYNC_LOCKED_PAGE_COUNT, _val); \ 8802 ((_var) &= ~(HTT_DLPAGER_SYNC_LOCKED_PAGE_COUNT_M));\ 8803 ((_var) |= ((_val) << HTT_DLPAGER_SYNC_LOCKED_PAGE_COUNT_S)); \ 8804 } while (0) 8805 8806 #define HTT_DLPAGER_TOTAL_LOCKED_PAGES_GET(_var) \ 8807 (((_var) & HTT_DLPAGER_TOTAL_LOCKED_PAGES_M) >> \ 8808 HTT_DLPAGER_TOTAL_LOCKED_PAGES_S) 8809 #define HTT_STATS_DLPAGER_STATS_DL_PAGER_STATS_TOTAL_LOCKED_PAGES_GET(_var) \ 8810 HTT_DLPAGER_TOTAL_LOCKED_PAGES_GET(_var) 8811 8812 #define HTT_DLPAGER_TOTAL_LOCKED_PAGES_SET(_var, _val) \ 8813 do { \ 8814 HTT_CHECK_SET_VAL(HTT_DLPAGER_TOTAL_LOCKED_PAGES, _val); \ 8815 ((_var) &= ~(HTT_DLPAGER_TOTAL_LOCKED_PAGES_M)); \ 8816 ((_var) |= ((_val) << HTT_DLPAGER_TOTAL_LOCKED_PAGES_S)); \ 8817 } while (0) 8818 8819 #define HTT_DLPAGER_TOTAL_FREE_PAGES_GET(_var) \ 8820 (((_var) & HTT_DLPAGER_TOTAL_FREE_PAGES_M) >> \ 8821 HTT_DLPAGER_TOTAL_FREE_PAGES_S) 8822 #define HTT_STATS_DLPAGER_STATS_DL_PAGER_STATS_TOTAL_FREE_PAGES_GET(_var) \ 8823 HTT_DLPAGER_TOTAL_FREE_PAGES_GET(_var) 8824 8825 #define HTT_DLPAGER_TOTAL_FREE_PAGES_SET(_var, _val) \ 8826 do { \ 8827 HTT_CHECK_SET_VAL(HTT_DLPAGER_TOTAL_FREE_PAGES, _val); \ 8828 ((_var) &= ~(HTT_DLPAGER_TOTAL_FREE_PAGES_M)); \ 8829 ((_var) |= ((_val) << HTT_DLPAGER_TOTAL_FREE_PAGES_S)); \ 8830 } while (0) 8831 8832 #define HTT_DLPAGER_LAST_LOCKED_PAGE_IDX_GET(_var) \ 8833 (((_var) & HTT_DLPAGER_LAST_LOCKED_PAGE_IDX_M) >> \ 8834 HTT_DLPAGER_LAST_LOCKED_PAGE_IDX_S) 8835 #define HTT_STATS_DLPAGER_STATS_DL_PAGER_STATS_LAST_LOCKED_PAGE_IDX_GET(_var) \ 8836 HTT_DLPAGER_LAST_LOCKED_PAGE_IDX_GET(_var) 8837 8838 #define HTT_DLPAGER_LAST_LOCKED_PAGE_IDX_SET(_var, _val) \ 8839 do { \ 8840 HTT_CHECK_SET_VAL(HTT_DLPAGER_LAST_LOCKED_PAGE_IDX, _val); \ 8841 ((_var) &= ~(HTT_DLPAGER_LAST_LOCKED_PAGE_IDX_M)); \ 8842 ((_var) |= ((_val) << HTT_DLPAGER_LAST_LOCKED_PAGE_IDX_S)); \ 8843 } while (0) 8844 8845 #define HTT_DLPAGER_LAST_UNLOCKED_PAGE_IDX_GET(_var) \ 8846 (((_var) & HTT_DLPAGER_LAST_UNLOCKED_PAGE_IDX_M) >> \ 8847 HTT_DLPAGER_LAST_UNLOCKED_PAGE_IDX_S) 8848 #define HTT_STATS_DLPAGER_STATS_DL_PAGER_STATS_LAST_UNLOCKED_PAGE_IDX_GET(_var) \ 8849 HTT_DLPAGER_LAST_UNLOCKED_PAGE_IDX_GET(_var) 8850 8851 #define HTT_DLPAGER_LAST_UNLOCKED_PAGE_IDX_SET(_var, _val) \ 8852 do { \ 8853 HTT_CHECK_SET_VAL(HTT_DLPAGER_LAST_UNLOCKED_PAGE_IDX, _val); \ 8854 ((_var) &= ~(HTT_DLPAGER_LAST_UNLOCKED_PAGE_IDX_M)); \ 8855 ((_var) |= ((_val) << HTT_DLPAGER_LAST_UNLOCKED_PAGE_IDX_S)); \ 8856 } while (0) 8857 8858 enum { 8859 HTT_STATS_PAGE_LOCKED = 0, 8860 HTT_STATS_PAGE_UNLOCKED = 1, 8861 HTT_STATS_NUM_PAGE_LOCK_STATES 8862 }; 8863 8864 /* dlPagerStats structure 8865 * Number of lock/unlock pages with last 10 lock/unlock occurrences are recorded */ 8866 typedef struct{ 8867 /** msg_dword_1 bitfields: 8868 * async_lock : 8, 8869 * sync_lock : 8, 8870 * reserved : 16; 8871 */ 8872 union { 8873 struct { 8874 A_UINT32 async_lock: 8, 8875 sync_lock: 8, 8876 reserved1: 16; 8877 8878 }; 8879 A_UINT32 msg_dword_1; 8880 }; 8881 /** mst_dword_2 bitfields: 8882 * total_locked_pages : 16, 8883 * total_free_pages : 16; 8884 */ 8885 union { 8886 struct { 8887 A_UINT32 total_locked_pages: 16, 8888 total_free_pages: 16; 8889 }; 8890 A_UINT32 msg_dword_2; 8891 }; 8892 /** msg_dword_3 bitfields: 8893 * last_locked_page_idx : 16, 8894 * last_unlocked_page_idx : 16; 8895 */ 8896 union { 8897 struct { 8898 A_UINT32 last_locked_page_idx: 16, 8899 last_unlocked_page_idx: 16; 8900 }; 8901 A_UINT32 msg_dword_3; 8902 }; 8903 8904 struct { 8905 A_UINT32 page_num; 8906 A_UINT32 num_of_pages; 8907 /** timestamp is in microsecond units, from SoC timer clock */ 8908 A_UINT32 timestamp_lsbs; 8909 A_UINT32 timestamp_msbs; 8910 } last_pages_info[HTT_STATS_NUM_PAGE_LOCK_STATES][HTT_DLPAGER_STATS_MAX_HIST]; 8911 } htt_dl_pager_stats_tlv; 8912 8913 /* NOTE: 8914 * This structure is for documentation, and cannot be safely used directly. 8915 * Instead, use the constituent TLV structures to fill/parse. 8916 * STATS_TYPE : HTT_DBG_EXT_STATS_DLPAGER_STATS 8917 * TLV_TAGS: 8918 * - HTT_STATS_DLPAGER_STATS_TAG 8919 */ 8920 typedef struct { 8921 htt_tlv_hdr_t tlv_hdr; 8922 htt_dl_pager_stats_tlv dl_pager_stats; 8923 } htt_stats_dlpager_stats_tlv; 8924 /* preserve old name alias for new name consistent with the tag name */ 8925 typedef htt_stats_dlpager_stats_tlv htt_dlpager_stats_t; 8926 8927 8928 /*======= PHY STATS ====================*/ 8929 /* 8930 * STATS TYPE : HTT_DBG_EXT_PHY_COUNTERS_AND_PHY_STATS 8931 * TLV_TAGS: 8932 * - HTT_STATS_PHY_COUNTERS_TAG 8933 * - HTT_STATS_PHY_STATS_TAG 8934 */ 8935 8936 #define HTT_MAX_RX_PKT_CNT 8 8937 #define HTT_MAX_RX_PKT_CRC_PASS_CNT 8 8938 #define HTT_MAX_PER_BLK_ERR_CNT 20 8939 #define HTT_MAX_RX_OTA_ERR_CNT 14 8940 #define HTT_MAX_RX_PKT_CNT_EXT 4 8941 #define HTT_MAX_RX_PKT_CRC_PASS_CNT_EXT 4 8942 #define HTT_MAX_RX_PKT_MU_CNT 14 8943 #define HTT_MAX_TX_PKT_CNT 10 8944 #define HTT_MAX_PHY_TX_ABORT_CNT 10 8945 8946 typedef enum { 8947 HTT_STATS_CHANNEL_HALF_RATE = 0x0001, /* Half rate */ 8948 HTT_STATS_CHANNEL_QUARTER_RATE = 0x0002, /* Quarter rate */ 8949 HTT_STATS_CHANNEL_DFS = 0x0004, /* Enable radar event reporting */ 8950 HTT_STATS_CHANNEL_HOME = 0x0008, /* Home channel */ 8951 HTT_STATS_CHANNEL_PASSIVE_SCAN = 0x0010, /*Passive Scan */ 8952 HTT_STATS_CHANNEL_DFS_SAP_NOT_UP = 0x0020, /* set when VDEV_START_REQUEST, clear when VDEV_UP */ 8953 HTT_STATS_CHANNEL_PASSIVE_SCAN_CAL = 0x0040, /* need to do passive scan calibration to avoid "spikes" */ 8954 HTT_STATS_CHANNEL_DFS_SAP_UP = 0x0080, /* DFS master */ 8955 HTT_STATS_CHANNEL_DFS_CFREQ2 = 0x0100, /* Enable radar event reporting for sec80 in VHT80p80 */ 8956 HTT_STATS_CHANNEL_DTIM_SYNTH = 0x0200, /* Enable DTIM */ 8957 HTT_STATS_CHANNEL_FORCE_GAIN = 0x0400, /* Force gain mmode (only used for FTM) */ 8958 HTT_STATS_CHANNEL_PERFORM_NF_CAL = 0x0800, /* Perform NF cal in channel change (only used for FTM) */ 8959 HTT_STATS_CHANNEL_165_MODE_0 = 0x1000, /* 165 MHz mode 0 */ 8960 HTT_STATS_CHANNEL_165_MODE_1 = 0x2000, /* 165 MHz mode 1 */ 8961 HTT_STATS_CHANNEL_165_MODE_2 = 0x3000, /* 165 MHz mode 2 */ 8962 HTT_STATS_CHANNEL_165_MODE_MASK = 0x3000, /* 165 MHz 2-bit mode mask */ 8963 } HTT_STATS_CHANNEL_FLAGS; 8964 8965 typedef enum { 8966 HTT_STATS_RF_MODE_MIN = 0, 8967 HTT_STATS_RF_MODE_PHYA_ONLY = 0, // only PHYA is active 8968 HTT_STATS_RF_MODE_DBS = 1, // PHYA/5G and PHYB/2G 8969 HTT_STATS_RF_MODE_SBS = 2, // PHYA/5G and PHYB/5G in HL/NPR; PHYA0/5G and PHYA1/5G in HK 8970 HTT_STATS_RF_MODE_PHYB_ONLY = 3, // only PHYB is active 8971 HTT_STATS_RF_MODE_DBS_SBS = 4, // PHYA0/5G, PHYA1/5G and PHYB/2G in HK (the 2 5G are in different channel) 8972 HTT_STATS_RF_MODE_DBS_OR_SBS = 5, // PHYA0/5G, PHYA1/5G and PHYB/5G or 2G in HK 8973 HTT_STATS_RF_MODE_INVALID = 0xff, 8974 } HTT_STATS_RF_MODE; 8975 8976 typedef enum { 8977 HTT_STATS_RESET_CAUSE_FIRST_RESET = 0x00000001, /* First reset by application */ 8978 HTT_STATS_RESET_CAUSE_ERROR = 0x00000002, /* Triggered due to error */ 8979 HTT_STATS_RESET_CAUSE_DEEP_SLEEP = 0x00000004, /* Reset after deep sleep */ 8980 HTT_STATS_RESET_CAUSE_FULL_RESET = 0x00000008, /* Full reset without any optimizations */ 8981 HTT_STATS_RESET_CAUSE_CHANNEL_CHANGE = 0x00000010, /* For normal channel change */ 8982 HTT_STATS_RESET_CAUSE_BAND_CHANGE = 0x00000020, /* Triggered due to band change */ 8983 HTT_STATS_RESET_CAUSE_DO_CAL = 0x00000040, /* Triggered due to calibrations */ 8984 HTT_STATS_RESET_CAUSE_MCI_ERROR = 0x00000080, /* Triggered due to MCI ERROR */ 8985 HTT_STATS_RESET_CAUSE_CHWIDTH_CHANGE = 0x00000100, /* Triggered due to channel width change */ 8986 HTT_STATS_RESET_CAUSE_WARM_RESTORE_CAL = 0x00000200, /* Triggered due to warm reset we want to just restore calibrations */ 8987 HTT_STATS_RESET_CAUSE_COLD_RESTORE_CAL = 0x00000400, /* Triggered due to cold reset we want to just restore calibrations */ 8988 HTT_STATS_RESET_CAUSE_PHY_WARM_RESET = 0x00000800, /* Triggered due to phy warm reset we want to just restore calibrations */ 8989 HTT_STATS_RESET_CAUSE_M3_SSR = 0x00001000, /* Triggered due to SSR Restart */ 8990 HTT_STATS_RESET_CAUSE_FORCE_CAL = 0x00002000, /* Reset to force the calibration */ 8991 /* 0x00004000, 0x00008000 reserved */ 8992 HTT_STATS_NO_RESET_CHANNEL_CHANGE = 0x00010000, /* No reset, normal channel change */ 8993 HTT_STATS_NO_RESET_BAND_CHANGE = 0x00020000, /* No reset, channel change across band */ 8994 HTT_STATS_NO_RESET_CHWIDTH_CHANGE = 0x00040000, /* No reset, channel change across channel width */ 8995 HTT_STATS_NO_RESET_CHAINMASK_CHANGE = 0x00080000, /* No reset, chainmask change */ 8996 HTT_STATS_RESET_CAUSE_PHY_WARM_RESET_UCODE_TRIG = 0x00100000, /* Triggered due to phy warm reset we want to just restore calibrations */ 8997 HTT_STATS_RESET_CAUSE_PHY_OFF_TIMEOUT_RESET = 0x00200000, /* Reset ucode because phy off ack timeout*/ 8998 HTT_STATS_RESET_CAUSE_LMAC_RESET_UMAC_NOC_ERR = 0x00400000, /* LMAC reset triggered due to NOC Address/Slave error originating at LMAC */ 8999 HTT_STATS_NO_RESET_SCAN_BACK_TO_SAME_HOME_CHANNEL_CHANGE = 0x00800000, /* No reset, scan to home channel change */ 9000 } HTT_STATS_RESET_CAUSE; 9001 9002 typedef enum { 9003 HTT_CHANNEL_RATE_FULL, 9004 HTT_CHANNEL_RATE_HALF, 9005 HTT_CHANNEL_RATE_QUARTER, 9006 9007 HTT_CHANNEL_RATE_COUNT 9008 } HTT_CHANNEL_RATE; 9009 9010 typedef enum { 9011 HTT_PHY_BW_IDX_20MHz = 0, 9012 HTT_PHY_BW_IDX_40MHz = 1, 9013 HTT_PHY_BW_IDX_80MHz = 2, 9014 HTT_PHY_BW_IDX_80Plus80 = 3, 9015 HTT_PHY_BW_IDX_160MHz = 4, 9016 HTT_PHY_BW_IDX_10MHz = 5, 9017 HTT_PHY_BW_IDX_5MHz = 6, 9018 HTT_PHY_BW_IDX_165MHz = 7, 9019 9020 } HTT_PHY_BW_IDX; 9021 9022 typedef enum { 9023 HTT_WHAL_CONFIG_NONE = 0x00000000, 9024 HTT_WHAL_CONFIG_NF_WAR = 0x00000001, 9025 HTT_WHAL_CONFIG_CAL_WAR = 0x00000002, 9026 HTT_WHAL_CONFIG_DO_NF_CAL = 0x00000004, 9027 HTT_WHAL_CONFIG_SET_WAIT_FOR_NF_CAL = 0x00000008, 9028 HTT_WHAL_CONFIG_FORCED_TX_PWR = 0x00000010, 9029 HTT_WHAL_CONFIG_FORCED_GAIN_IDX = 0x00000020, 9030 HTT_WHAL_CONFIG_FORCED_PER_CHAIN = 0x00000040, 9031 } HTT_WHAL_CONFIG; 9032 9033 typedef struct { 9034 htt_tlv_hdr_t tlv_hdr; 9035 /** number of RXTD OFDMA OTA error counts except power surge and drop */ 9036 A_UINT32 rx_ofdma_timing_err_cnt; 9037 /** rx_cck_fail_cnt: 9038 * number of cck error counts due to rx reception failure because of 9039 * timing error in cck 9040 */ 9041 A_UINT32 rx_cck_fail_cnt; 9042 /** number of times tx abort initiated by mac */ 9043 A_UINT32 mactx_abort_cnt; 9044 /** number of times rx abort initiated by mac */ 9045 A_UINT32 macrx_abort_cnt; 9046 /** number of times tx abort initiated by phy */ 9047 A_UINT32 phytx_abort_cnt; 9048 /** number of times rx abort initiated by phy */ 9049 A_UINT32 phyrx_abort_cnt; 9050 /** number of rx deferred count initiated by phy */ 9051 A_UINT32 phyrx_defer_abort_cnt; 9052 /** number of sizing events generated at LSTF */ 9053 A_UINT32 rx_gain_adj_lstf_event_cnt; /* a.k.a sizing1 */ 9054 /** number of sizing events generated at non-legacy LTF */ 9055 A_UINT32 rx_gain_adj_non_legacy_cnt; /* a.k.a sizing2 */ 9056 /** rx_pkt_cnt - 9057 * Received EOP (end-of-packet) count per packet type; 9058 * [0] = 11a; [1] = 11b; [2] = 11n; [3] = 11ac; [4] = 11ax; [5] = GF 9059 * [6] = EHT; [7]=RSVD; [6] = Applicable only for BE 9060 */ 9061 A_UINT32 rx_pkt_cnt[HTT_MAX_RX_PKT_CNT]; 9062 /** rx_pkt_crc_pass_cnt - 9063 * Received EOP (end-of-packet) count per packet type; 9064 * [0] = 11a; [1] = 11b; [2] = 11n; [3] = 11ac; [4] = 11ax; [5] = GF 9065 * [6] = EHT; [7]=RSVD; [6] = Applicable only for BE 9066 */ 9067 A_UINT32 rx_pkt_crc_pass_cnt[HTT_MAX_RX_PKT_CRC_PASS_CNT]; 9068 /** per_blk_err_cnt - 9069 * Error count per error source; 9070 * [0] = unknown; [1] = LSIG; [2] = HTSIG; [3] = VHTSIG; [4] = HESIG; 9071 * [5] = RXTD_OTA; [6] = RXTD_FATAL; [7] = DEMF; [8] = ROBE; 9072 * [9] = PMI; [10] = TXFD; [11] = TXTD; [12] = PHYRF 9073 * [13-19]=RSVD 9074 */ 9075 A_UINT32 per_blk_err_cnt[HTT_MAX_PER_BLK_ERR_CNT]; 9076 /** rx_ota_err_cnt - 9077 * RXTD OTA (over-the-air) error count per error reason; 9078 * [0] = voting fail; [1] = weak det fail; [2] = strong sig fail; 9079 * [3] = cck fail; [4] = power surge; [5] = power drop; 9080 * [6] = btcf timing timeout error; [7] = btcf packet detect error; 9081 * [8] = coarse timing timeout error 9082 * [9-13]=RSVD 9083 */ 9084 A_UINT32 rx_ota_err_cnt[HTT_MAX_RX_OTA_ERR_CNT]; 9085 /** rx_pkt_cnt_ext - 9086 * Received EOP (end-of-packet) count per packet type for BE; 9087 * [0] = WUR; [1] = AZ; [2-3]=RVSD 9088 */ 9089 A_UINT32 rx_pkt_cnt_ext[HTT_MAX_RX_PKT_CNT_EXT]; 9090 /** rx_pkt_crc_pass_cnt_ext - 9091 * Received EOP (end-of-packet) count per packet type for BE; 9092 * [0] = WUR; [1] = AZ; [2-3]=RVSD 9093 */ 9094 A_UINT32 rx_pkt_crc_pass_cnt_ext[HTT_MAX_RX_PKT_CRC_PASS_CNT_EXT]; 9095 /** rx_pkt_mu_cnt - 9096 * RX MU MIMO+OFDMA packet count per packet type for BE; 9097 * [0] = 11ax OFDMA; [1] = 11ax OFDMA+MUMIMO; [2] = 11be OFDMA; 9098 * [3] = 11be OFDMA+MUMIMO; [4] = 11ax MIMO; [5] = 11be MIMO; 9099 * [6] = 11ax OFDMA; [7] = 11ax OFDMA+MUMIMO; [8] = 11be OFDMA; 9100 * [9] = 11be OFDMA+MUMIMO; [10] = 11ax MIMO; [11] = 11be MIMO; 9101 * [12-13]=RSVD 9102 */ 9103 A_UINT32 rx_pkt_mu_cnt[HTT_MAX_RX_PKT_MU_CNT]; 9104 /** tx_pkt_cnt - 9105 * num of transfered packet count per packet type; 9106 * [0] = 11a; [1] = 11b; [2] = 11n; [3] = 11ac; [4] = 11ax; [5] = GF; 9107 * [6]= EHT; [7] = WUR; [8] = AZ; [9]=RSVD; [6-8] = Applicable only for BE 9108 */ 9109 A_UINT32 tx_pkt_cnt[HTT_MAX_TX_PKT_CNT]; 9110 /** phy_tx_abort_cnt - 9111 * phy tx abort after each tlv; 9112 * [0] = PRE-PHY desc tlv; [1] = PHY desc tlv; [2] = LSIGA tlv; 9113 * [3] = LSIGB tlv; [4] = Per User tlv; [5] = HESIGB tlv; 9114 * [6] = Service tlv; [7] = Tx Packet End tlv; [8-9]=RSVD; 9115 */ 9116 A_UINT32 phy_tx_abort_cnt[HTT_MAX_PHY_TX_ABORT_CNT]; 9117 } htt_stats_phy_counters_tlv; 9118 /* preserve old name alias for new name consistent with the tag name */ 9119 typedef htt_stats_phy_counters_tlv htt_phy_counters_tlv; 9120 9121 #define HTT_STATS_ANI_MODE_M 0x000000ff 9122 #define HTT_STATS_ANI_MODE_S 0 9123 9124 #define HTT_STATS_ANI_MODE_GET(_var) \ 9125 (((_var) & HTT_STATS_ANI_MODE_M) >> \ 9126 HTT_STATS_ANI_MODE_S) 9127 9128 #define HTT_STATS_ANI_MODE_SET(_var, _val) \ 9129 do { \ 9130 HTT_CHECK_SET_VAL(HTT_STATS_ANI_MODE, _val); \ 9131 ((_var) |= ((_val) << HTT_STATS_ANI_MODE_S)); \ 9132 } while (0) 9133 9134 typedef struct { 9135 htt_tlv_hdr_t tlv_hdr; 9136 /** per chain hw noise floor values in dBm */ 9137 A_INT32 nf_chain[HTT_STATS_MAX_CHAINS]; 9138 /** number of false radars detected */ 9139 A_UINT32 false_radar_cnt; 9140 /** number of channel switches happened due to radar detection */ 9141 A_UINT32 radar_cs_cnt; 9142 /** ani_level - 9143 * ANI level (noise interference) corresponds to the channel 9144 * the desense levels range from -5 to 15 in dB units, 9145 * higher values indicating more noise interference. 9146 */ 9147 A_INT32 ani_level; 9148 /** running time in minutes since FW boot */ 9149 A_UINT32 fw_run_time; 9150 /** per chain runtime noise floor values in dBm */ 9151 A_INT32 runTime_nf_chain[HTT_STATS_MAX_CHAINS]; 9152 9153 /** DFS SW based progressive stats - start **/ 9154 9155 /* current AP operating bandwidth (refer to WLAN_PHY_MODE) */ 9156 A_UINT32 current_OBW; 9157 /* current AP device bandwidth (refer to WLAN_PHY_MODE) */ 9158 A_UINT32 current_DBW; 9159 /* last_radar_type: last detected radar type 9160 * This last_radar_type field contains a value whose meaning is not 9161 * exposed to the host; this field is only provided for debug purposes. 9162 */ 9163 A_UINT32 last_radar_type; 9164 /* dfs_reg_domain: curent DFS regulatory domain 9165 * This dfs_reg_domain field contains a value whose meaning is not 9166 * exposed to the host; this field is only provided for debug purposes. 9167 */ 9168 A_UINT32 dfs_reg_domain; 9169 /* radar_mask_bit: Radar mask setting programmed in HW registers. 9170 * Each bit represents a 20 MHz portion of the channel. 9171 * Bit 0 represents the highest 20 MHz portion within the channel. 9172 * For example... 9173 * For a 80 MHz channel, bit0 = highest 20 MHz, bit3 = lowest 20 MHz 9174 * For a 320 MHz channel, bit0 = highest 20 MHz, bit15 = lowest 20 MHz 9175 */ 9176 A_UINT32 radar_mask_bit; 9177 /* DFS radar rssi threshold (units = dBm) */ 9178 A_INT32 radar_rssi; 9179 /* DFS global flags (refer to IEEE80211_CHAN_* defines) */ 9180 A_UINT32 radar_dfs_flags; 9181 /* band center frequency of operating bandwidth (units = MHz) */ 9182 A_UINT32 band_center_frequency_OBW; 9183 /* band center frequency of device bandwidth (units = MHz) */ 9184 A_UINT32 band_center_frequency_DBW; 9185 9186 /** DFS SW based progressive stats - end **/ 9187 9188 /* BIT [ 7 : 0] :- ani_mode 9189 * BIT [31 : 8] :- reserved 9190 * 9191 * ani_mode: 9192 * 1 for static ANI 9193 * 0 for dynamic ANI 9194 * 0xFF for ANI disabled 9195 */ 9196 union { 9197 A_UINT32 dword__ani_mode; 9198 struct { 9199 A_UINT32 9200 ani_mode: 8, 9201 reserved: 24; 9202 }; 9203 }; 9204 } htt_stats_phy_stats_tlv; 9205 /* preserve old name alias for new name consistent with the tag name */ 9206 typedef htt_stats_phy_stats_tlv htt_phy_stats_tlv; 9207 9208 9209 #define HTT_STATS_PHY_RESET_CAL_DATA_COMPRESSED_M 0x00000001 9210 #define HTT_STATS_PHY_RESET_CAL_DATA_COMPRESSED_S 0 9211 #define HTT_STATS_PHY_RESET_CAL_DATA_COMPRESSED_GET(_var) \ 9212 (((_var) & HTT_STATS_PHY_RESET_CAL_DATA_COMPRESSED_M) >> \ 9213 HTT_STATS_PHY_RESET_CAL_DATA_COMPRESSED_S) 9214 #define HTT_STATS_PHY_RESET_CAL_DATA_COMPRESSED_SET(_var, _val) \ 9215 do { \ 9216 HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_CAL_DATA_COMPRESSED, _val); \ 9217 ((_var) |= ((_val) << STATS_PHY_RESET_CAL_DATA_COMPRESSED_S)); \ 9218 } while (0) 9219 #define HTT_STATS_PHY_RESET_CAL_DATA_SOURCE_M 0x00000006 9220 #define HTT_STATS_PHY_RESET_CAL_DATA_SOURCE_S 1 9221 #define HTT_STATS_PHY_RESET_CAL_DATA_SOURCE_GET(_var) \ 9222 (((_var) & HTT_STATS_PHY_RESET_CAL_DATA_SOURCE_M) >> \ 9223 HTT_STATS_PHY_RESET_CAL_DATA_SOURCE_S) 9224 #define HTT_STATS_PHY_RESET_CAL_DATA_SOURCE_SET(_var, _val) \ 9225 do { \ 9226 HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_CAL_DATA_SOURCE, _val); \ 9227 ((_var) |= ((_val) << STATS_PHY_RESET_CAL_DATA_SOURCE_S)); \ 9228 } while (0) 9229 #define HTT_STATS_PHY_RESET_XTALCAL_M 0x00000008 9230 #define HTT_STATS_PHY_RESET_XTALCAL_S 3 9231 #define HTT_STATS_PHY_RESET_XTALCAL_GET(_var) \ 9232 (((_var) & HTT_STATS_PHY_RESET_XTALCAL_M) >> \ 9233 HTT_STATS_PHY_RESET_XTALCAL_S) 9234 #define HTT_STATS_PHY_RESET_XTALCAL_SET(_var, _val) \ 9235 do { \ 9236 HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_XTALCAL, _val); \ 9237 ((_var) |= ((_val) << STATS_PHY_RESET_XTALCAL_S)); \ 9238 } while (0) 9239 #define HTT_STATS_PHY_RESET_TPCCAL2GOPC_M 0x00000010 9240 #define HTT_STATS_PHY_RESET_TPCCAL2GOPC_S 4 9241 #define HTT_STATS_PHY_RESET_TPCCAL2GOPC_GET(_var) \ 9242 (((_var) & HTT_STATS_PHY_RESET_TPCCAL2GOPC_M) >> \ 9243 HTT_STATS_PHY_RESET_TPCCAL2GOPC_S) 9244 #define HTT_STATS_PHY_RESET_TPCCAL2GOPC_SET(_var, _val) \ 9245 do { \ 9246 HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_TPCCAL2GOPC, _val); \ 9247 ((_var) |= ((_val) << STATS_PHY_RESET_TPCCAL2GOPC_S)); \ 9248 } while (0) 9249 #define HTT_STATS_PHY_RESET_TPCCAL2GFPC_M 0x00000020 9250 #define HTT_STATS_PHY_RESET_TPCCAL2GFPC_S 5 9251 #define HTT_STATS_PHY_RESET_TPCCAL2GFPC_GET(_var) \ 9252 (((_var) & HTT_STATS_PHY_RESET_TPCCAL2GFPC_M) >> \ 9253 HTT_STATS_PHY_RESET_TPCCAL2GFPC_S) 9254 #define HTT_STATS_PHY_RESET_TPCCAL2GFPC_SET(_var, _val) \ 9255 do { \ 9256 HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_TPCCAL2GFPC, _val); \ 9257 ((_var) |= ((_val) << STATS_PHY_RESET_TPCCAL2GFPC_S)); \ 9258 } while (0) 9259 #define HTT_STATS_PHY_RESET_TPCCAL5GOPC_M 0x00000040 9260 #define HTT_STATS_PHY_RESET_TPCCAL5GOPC_S 6 9261 #define HTT_STATS_PHY_RESET_TPCCAL5GOPC_GET(_var) \ 9262 (((_var) & HTT_STATS_PHY_RESET_TPCCAL5GOPC_M) >> \ 9263 HTT_STATS_PHY_RESET_TPCCAL5GOPC_S) 9264 #define HTT_STATS_PHY_RESET_TPCCAL5GOPC_SET(_var, _val) \ 9265 do { \ 9266 HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_TPCCAL5GOPC, _val); \ 9267 ((_var) |= ((_val) << STATS_PHY_RESET_TPCCAL5GOPC_S)); \ 9268 } while (0) 9269 #define HTT_STATS_PHY_RESET_TPCCAL5GFPC_M 0x00000080 9270 #define HTT_STATS_PHY_RESET_TPCCAL5GFPC_S 7 9271 #define HTT_STATS_PHY_RESET_TPCCAL5GFPC_GET(_var) \ 9272 (((_var) & HTT_STATS_PHY_RESET_TPCCAL5GFPC_M) >> \ 9273 HTT_STATS_PHY_RESET_TPCCAL5GFPC_S) 9274 #define HTT_STATS_PHY_RESET_TPCCAL5GFPC_SET(_var, _val) \ 9275 do { \ 9276 HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_TPCCAL5GFPC, _val); \ 9277 ((_var) |= ((_val) << STATS_PHY_RESET_TPCCAL5GFPC_S)); \ 9278 } while (0) 9279 #define HTT_STATS_PHY_RESET_TPCCAL6GOPC_M 0x00000100 9280 #define HTT_STATS_PHY_RESET_TPCCAL6GOPC_S 8 9281 #define HTT_STATS_PHY_RESET_TPCCAL6GOPC_GET(_var) \ 9282 (((_var) & HTT_STATS_PHY_RESET_TPCCAL6GOPC_M) >> \ 9283 HTT_STATS_PHY_RESET_TPCCAL6GOPC_S) 9284 #define HTT_STATS_PHY_RESET_TPCCAL6GOPC_SET(_var, _val) \ 9285 do { \ 9286 HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_TPCCAL6GOPC, _val); \ 9287 ((_var) |= ((_val) << STATS_PHY_RESET_TPCCAL6GOPC_S)); \ 9288 } while (0) 9289 #define HTT_STATS_PHY_RESET_TPCCAL6GFPC_M 0x00000200 9290 #define HTT_STATS_PHY_RESET_TPCCAL6GFPC_S 9 9291 #define HTT_STATS_PHY_RESET_TPCCAL6GFPC_GET(_var) \ 9292 (((_var) & HTT_STATS_PHY_RESET_TPCCAL6GFPC_M) >> \ 9293 HTT_STATS_PHY_RESET_TPCCAL6GFPC_S) 9294 #define HTT_STATS_PHY_RESET_TPCCAL6GFPC_SET(_var, _val) \ 9295 do { \ 9296 HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_TPCCAL6GFPC, _val); \ 9297 ((_var) |= ((_val) << STATS_PHY_RESET_TPCCAL6GFPC_S)); \ 9298 } while (0) 9299 #define HTT_STATS_PHY_RESET_RXGAINCAL2G_M 0x00000400 9300 #define HTT_STATS_PHY_RESET_RXGAINCAL2G_S 10 9301 #define HTT_STATS_PHY_RESET_RXGAINCAL2G_GET(_var) \ 9302 (((_var) & HTT_STATS_PHY_RESET_RXGAINCAL2G_M) >> \ 9303 HTT_STATS_PHY_RESET_RXGAINCAL2G_S) 9304 #define HTT_STATS_PHY_RESET_RXGAINCAL2G_SET(_var, _val) \ 9305 do { \ 9306 HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_RXGAINCAL2G, _val); \ 9307 ((_var) |= ((_val) << STATS_PHY_RESET_RXGAINCAL2G_S)); \ 9308 } while (0) 9309 #define HTT_STATS_PHY_RESET_RXGAINCAL5G_M 0x00000800 9310 #define HTT_STATS_PHY_RESET_RXGAINCAL5G_S 11 9311 #define HTT_STATS_PHY_RESET_RXGAINCAL5G_GET(_var) \ 9312 (((_var) & HTT_STATS_PHY_RESET_RXGAINCAL5G_M) >> \ 9313 HTT_STATS_PHY_RESET_RXGAINCAL5G_S) 9314 #define HTT_STATS_PHY_RESET_RXGAINCAL5G_SET(_var, _val) \ 9315 do { \ 9316 HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_RXGAINCAL5G, _val); \ 9317 ((_var) |= ((_val) << STATS_PHY_RESET_RXGAINCAL5G_S)); \ 9318 } while (0) 9319 #define HTT_STATS_PHY_RESET_RXGAINCAL6G_M 0x00001000 9320 #define HTT_STATS_PHY_RESET_RXGAINCAL6G_S 12 9321 #define HTT_STATS_PHY_RESET_RXGAINCAL6G_GET(_var) \ 9322 (((_var) & HTT_STATS_PHY_RESET_RXGAINCAL6G_M) >> \ 9323 HTT_STATS_PHY_RESET_RXGAINCAL6G_S) 9324 #define HTT_STATS_PHY_RESET_RXGAINCAL6G_SET(_var, _val) \ 9325 do { \ 9326 HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_RXGAINCAL6G, _val); \ 9327 ((_var) |= ((_val) << STATS_PHY_RESET_RXGAINCAL6G_S)); \ 9328 } while (0) 9329 #define HTT_STATS_PHY_RESET_AOACAL2G_M 0x00002000 9330 #define HTT_STATS_PHY_RESET_AOACAL2G_S 13 9331 #define HTT_STATS_PHY_RESET_AOACAL2G_GET(_var) \ 9332 (((_var) & HTT_STATS_PHY_RESET_AOACAL2G_M) >> \ 9333 HTT_STATS_PHY_RESET_AOACAL2G_S) 9334 #define HTT_STATS_PHY_RESET_AOACAL2G_SET(_var, _val) \ 9335 do { \ 9336 HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_AOACAL2G, _val); \ 9337 ((_var) |= ((_val) << STATS_PHY_RESET_AOACAL2G_S)); \ 9338 } while (0) 9339 #define HTT_STATS_PHY_RESET_AOACAL5G_M 0x00004000 9340 #define HTT_STATS_PHY_RESET_AOACAL5G_S 14 9341 #define HTT_STATS_PHY_RESET_AOACAL5G_GET(_var) \ 9342 (((_var) & HTT_STATS_PHY_RESET_AOACAL5G_M) >> \ 9343 HTT_STATS_PHY_RESET_AOACAL5G_S) 9344 #define HTT_STATS_PHY_RESET_AOACAL5G_SET(_var, _val) \ 9345 do { \ 9346 HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_AOACAL5G, _val); \ 9347 ((_var) |= ((_val) << STATS_PHY_RESET_AOACAL5G_S)); \ 9348 } while (0) 9349 #define HTT_STATS_PHY_RESET_AOACAL6G_M 0x00008000 9350 #define HTT_STATS_PHY_RESET_AOACAL6G_S 15 9351 #define HTT_STATS_PHY_RESET_AOACAL6G_GET(_var) \ 9352 (((_var) & HTT_STATS_PHY_RESET_AOACAL6G_M) >> \ 9353 HTT_STATS_PHY_RESET_AOACAL6G_S) 9354 #define HTT_STATS_PHY_RESET_AOACAL6G_SET(_var, _val) \ 9355 do { \ 9356 HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_AOACAL6G, _val); \ 9357 ((_var) |= ((_val) << STATS_PHY_RESET_AOACAL6G_S)); \ 9358 } while (0) 9359 #define HTT_STATS_PHY_RESET_XTAL_FROM_OTP_M 0x00010000 9360 #define HTT_STATS_PHY_RESET_XTAL_FROM_OTP_S 16 9361 #define HTT_STATS_PHY_RESET_XTAL_FROM_OTP_GET(_var) \ 9362 (((_var) & HTT_STATS_PHY_RESET_XTAL_FROM_OTP_M) >> \ 9363 HTT_STATS_PHY_RESET_XTAL_FROM_OTP_S) 9364 #define HTT_STATS_PHY_RESET_XTAL_FROM_OTP_SET(_var, _val) \ 9365 do { \ 9366 HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_XTAL_FROM_OTP, _val); \ 9367 ((_var) |= ((_val) << STATS_PHY_RESET_XTAL_FROM_OTP_S)); \ 9368 } while (0) 9369 9370 #define HTT_STATS_PHY_RESET_GLUT_LINEARITY_M 0x000000FF 9371 #define HTT_STATS_PHY_RESET_GLUT_LINEARITY_S 0 9372 #define HTT_STATS_PHY_RESET_GLUT_LINEARITY_GET(_var) \ 9373 (((_var) & HTT_STATS_PHY_RESET_GLUT_LINEARITY_M) >> \ 9374 HTT_STATS_PHY_RESET_GLUT_LINEARITY_S) 9375 #define HTT_STATS_PHY_RESET_GLUT_LINEARITY_SET(_var, _val) \ 9376 do { \ 9377 HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_GLUT_LINEARITY, _val); \ 9378 ((_var) |= ((_val) << STATS_PHY_RESET_GLUT_LINEARITY_S)); \ 9379 } while (0) 9380 #define HTT_STATS_PHY_RESET_PLUT_LINEARITY_M 0x0000FF00 9381 #define HTT_STATS_PHY_RESET_PLUT_LINEARITY_S 8 9382 #define HTT_STATS_PHY_RESET_PLUT_LINEARITY_GET(_var) \ 9383 (((_var) & HTT_STATS_PHY_RESET_PLUT_LINEARITY_M) >> \ 9384 HTT_STATS_PHY_RESET_PLUT_LINEARITY_S) 9385 #define HTT_STATS_PHY_RESET_PLUT_LINEARITY_SET(_var, _val) \ 9386 do { \ 9387 HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_PLUT_LINEARITY, _val); \ 9388 ((_var) |= ((_val) << STATS_PHY_RESET_PLUT_LINEARITY_S)); \ 9389 } while (0) 9390 #define HTT_STATS_PHY_RESET_WLANDRIVERMODE_M 0x00FF0000 9391 #define HTT_STATS_PHY_RESET_WLANDRIVERMODE_S 16 9392 #define HTT_STATS_PHY_RESET_WLANDRIVERMODE_GET(_var) \ 9393 (((_var) & HTT_STATS_PHY_RESET_WLANDRIVERMODE_M) >> \ 9394 HTT_STATS_PHY_RESET_WLANDRIVERMODE_S) 9395 #define HTT_STATS_PHY_RESET_WLANDRIVERMODE_SET(_var, _val) \ 9396 do { \ 9397 HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_WLANDRIVERMODE, _val); \ 9398 ((_var) |= ((_val) << STATS_PHY_RESET_WLANDRIVERMODE_S)); \ 9399 } while (0) 9400 9401 9402 typedef struct { 9403 htt_tlv_hdr_t tlv_hdr; 9404 /** current pdev_id */ 9405 A_UINT32 pdev_id; 9406 /** current channel information */ 9407 A_UINT32 chan_mhz; 9408 /** center_freq1, center_freq2 in mhz */ 9409 A_UINT32 chan_band_center_freq1; 9410 A_UINT32 chan_band_center_freq2; 9411 /** chan_phy_mode - WLAN_PHY_MODE enum type */ 9412 A_UINT32 chan_phy_mode; 9413 /** chan_flags follows HTT_STATS_CHANNEL_FLAGS enum */ 9414 A_UINT32 chan_flags; 9415 /** channel Num updated to virtual phybase */ 9416 A_UINT32 chan_num; 9417 9418 /** Cause for the phy reset - HTT_STATS_RESET_CAUSE */ 9419 A_UINT32 reset_cause; 9420 /** Cause for the previous phy reset */ 9421 A_UINT32 prev_reset_cause; 9422 /** source for the phywarm reset - HTT_STATS_RESET_CAUSE */ 9423 A_UINT32 phy_warm_reset_src; 9424 /** rxGain Table selection mode - register settings 9425 * 0 - Auto, 1/2 - Forced with and without BT override respectively 9426 */ 9427 A_UINT32 rx_gain_tbl_mode; 9428 /** current xbar value - perchain analog to digital idx mapping */ 9429 A_UINT32 xbar_val; 9430 /** Flag to indicate forced calibration */ 9431 A_UINT32 force_calibration; 9432 /** current RF mode (e.g. SBS/DBS) - follows HTT_STATS_RF_MODE enum */ 9433 A_UINT32 phyrf_mode; 9434 9435 /* PDL phyInput stats */ 9436 /** homechannel flag 9437 * 1- Homechan, 0 - scan channel 9438 */ 9439 A_UINT32 phy_homechan; 9440 /** Tx and Rx chainmask */ 9441 A_UINT32 phy_tx_ch_mask; 9442 A_UINT32 phy_rx_ch_mask; 9443 /** INI masks - to decide the INI registers to be loaded on a reset */ 9444 A_UINT32 phybb_ini_mask; 9445 A_UINT32 phyrf_ini_mask; 9446 9447 /** DFS,ADFS/Spectral scan enable masks */ 9448 A_UINT32 phy_dfs_en_mask; 9449 A_UINT32 phy_sscan_en_mask; 9450 A_UINT32 phy_synth_sel_mask; 9451 A_UINT32 phy_adfs_freq; 9452 9453 /** CCK FIR settings 9454 * register settings - filter coefficients for Iqs conversion 9455 * [31:24] = FIR_COEFF_3_0 9456 * [23:16] = FIR_COEFF_2_0 9457 * [15:8] = FIR_COEFF_1_0 9458 * [7:0] = FIR_COEFF_0_0 9459 */ 9460 A_UINT32 cck_fir_settings; 9461 /** dynamic primary channel index 9462 * primary 20MHz channel index on the current channel BW 9463 */ 9464 A_UINT32 phy_dyn_pri_chan; 9465 9466 /** 9467 * Current CCA detection threshold 9468 * dB above noisefloor req for CCA 9469 * Register settings for all subbands 9470 */ 9471 A_UINT32 cca_thresh; 9472 /** 9473 * status for dynamic CCA adjustment 9474 * 0-disabled, 1-enabled 9475 */ 9476 A_UINT32 dyn_cca_status; 9477 /** RXDEAF Register value 9478 * rxdesense_thresh_sw - VREG Register 9479 * rxdesense_thresh_hw - PHY Register 9480 */ 9481 A_UINT32 rxdesense_thresh_sw; 9482 A_UINT32 rxdesense_thresh_hw; 9483 /** Current PHY Bandwidth - 9484 * values are specified by the HTT_PHY_BW_IDX enum type 9485 */ 9486 A_UINT32 phy_bw_code; 9487 /** Current channel operating rate - 9488 * values are specified by the HTT_CHANNEL_RATE enum type 9489 */ 9490 A_UINT32 phy_rate_mode; 9491 /** current channel operating band 9492 * 0 - 5G; 1 - 2G; 2 -6G 9493 */ 9494 A_UINT32 phy_band_code; 9495 /** microcode processor virtual phy base address - 9496 * provided only for debug 9497 */ 9498 A_UINT32 phy_vreg_base; 9499 /** microcode processor virtual phy base ext address - 9500 * provided only for debug 9501 */ 9502 A_UINT32 phy_vreg_base_ext; 9503 /** HW LUT table configuration for home/scan channel - 9504 * provided only for debug 9505 */ 9506 A_UINT32 cur_table_index; 9507 /** SW configuration flag for PHY reset and Calibrations - 9508 * values are specified by the HTT_WHAL_CONFIG enum type 9509 */ 9510 A_UINT32 whal_config_flag; 9511 /** nfcal_iteration_counts: 9512 * iteration count for Home/Scan/Periodic Noise Floor calibrations 9513 * nfcal_iteration_counts[0] - home NF iteration counter 9514 * nfcal_iteration_counts[1] - scan NF iteration counter 9515 * nfcal_iteration_counts[2] - periodic NF iteration counter 9516 * These counters are not reset automatically; they are only reset 9517 * when explicitly requested by the host. 9518 */ 9519 A_UINT32 nfcal_iteration_counts[3]; 9520 9521 /** Below union indicates the merge status for different cal */ 9522 union { 9523 A_UINT32 calmerge_stats; 9524 struct { 9525 A_UINT32 CalData_Compressed:1, 9526 CalDataSource:2, 9527 xtalcal:1, 9528 tpccal2GFPC:1, 9529 tpccal2GOPC:1, 9530 tpccal5GFPC:1, 9531 tpccal5GOPC:1, 9532 tpccal6GFPC:1, 9533 tpccal6GOPC:1, 9534 rxgaincal2G:1, 9535 rxgaincal5G:1, 9536 rxgaincal6G:1, 9537 aoacal2G:1, 9538 aoacal5G:1, 9539 aoacal6G:1, 9540 XTAL_from_OTP:1, 9541 rsvd1:15; 9542 }; 9543 }; 9544 /** Below union lets us know of any non-linearity in plut/glut 9545 * and the mode we are in 9546 */ 9547 union { 9548 A_UINT32 misc_stats; 9549 struct { 9550 A_UINT32 GLUT_linearity:8, 9551 PLUT_linearity:8, 9552 WlanDriverMode:8, 9553 rsvd2:8; 9554 }; 9555 }; 9556 /** BoardId fetched from OTP */ 9557 A_UINT32 BoardIDfromOTP; 9558 } htt_stats_phy_reset_stats_tlv; 9559 /* preserve old name alias for new name consistent with the tag name */ 9560 typedef htt_stats_phy_reset_stats_tlv htt_phy_reset_stats_tlv; 9561 9562 typedef struct { 9563 htt_tlv_hdr_t tlv_hdr; 9564 9565 /** current pdev_id */ 9566 A_UINT32 pdev_id; 9567 /** ucode PHYOFF pass/failure count */ 9568 A_UINT32 cf_active_low_fail_cnt; 9569 A_UINT32 cf_active_low_pass_cnt; 9570 9571 /** PHYOFF count attempted through ucode VREG */ 9572 A_UINT32 phy_off_through_vreg_cnt; 9573 9574 /** Force calibration count */ 9575 A_UINT32 force_calibration_cnt; 9576 9577 /** phyoff count during rfmode switch */ 9578 A_UINT32 rf_mode_switch_phy_off_cnt; 9579 9580 /** Temperature based recalibration count */ 9581 A_UINT32 temperature_recal_cnt; 9582 } htt_stats_phy_reset_counters_tlv; 9583 /* preserve old name alias for new name consistent with the tag name */ 9584 typedef htt_stats_phy_reset_counters_tlv htt_phy_reset_counters_tlv; 9585 9586 /* Considering 320 MHz maximum 16 power levels */ 9587 #define HTT_MAX_CH_PWR_INFO_SIZE 16 9588 9589 #define HTT_PHY_TPC_STATS_CTL_REGION_GRP_M 0x000000ff 9590 #define HTT_PHY_TPC_STATS_CTL_REGION_GRP_S 0 9591 9592 #define HTT_PHY_TPC_STATS_CTL_REGION_GRP_GET(_var) \ 9593 (((_var) & HTT_PHY_TPC_STATS_CTL_REGION_GRP_M) >> \ 9594 HTT_PHY_TPC_STATS_CTL_REGION_GRP_S) 9595 /* provide properly-named macro */ 9596 #define HTT_STATS_PHY_TPC_STATS_CTL_REGION_GRP_GET(_var) \ 9597 HTT_PHY_TPC_STATS_CTL_REGION_GRP_GET(_var) 9598 #define HTT_PHY_TPC_STATS_CTL_REGION_GRP_SET(_var, _val) \ 9599 do { \ 9600 HTT_CHECK_SET_VAL(HTT_PHY_TPC_STATS_CTL_REGION_GRP, _val); \ 9601 ((_var) &= ~(HTT_PHY_TPC_STATS_CTL_REGION_GRP_M)); \ 9602 ((_var) |= ((_val) << HTT_PHY_TPC_STATS_CTL_REGION_GRP_S)); \ 9603 } while (0) 9604 9605 #define HTT_PHY_TPC_STATS_SUB_BAND_INDEX_M 0x0000ff00 9606 #define HTT_PHY_TPC_STATS_SUB_BAND_INDEX_S 8 9607 9608 #define HTT_PHY_TPC_STATS_SUB_BAND_INDEX_GET(_var) \ 9609 (((_var) & HTT_PHY_TPC_STATS_SUB_BAND_INDEX_M) >> \ 9610 HTT_PHY_TPC_STATS_SUB_BAND_INDEX_S) 9611 /* provide properly-named macro */ 9612 #define HTT_STATS_PHY_TPC_STATS_SUB_BAND_INDEX_GET(_var) \ 9613 HTT_PHY_TPC_STATS_SUB_BAND_INDEX_GET(_var) 9614 #define HTT_PHY_TPC_STATS_SUB_BAND_INDEX_SET(_var, _val) \ 9615 do { \ 9616 HTT_CHECK_SET_VAL(HTT_PHY_TPC_STATS_SUB_BAND_INDEX, _val); \ 9617 ((_var) &= ~(HTT_PHY_TPC_STATS_SUB_BAND_INDEX_M)); \ 9618 ((_var) |= ((_val) << HTT_PHY_TPC_STATS_SUB_BAND_INDEX_S)); \ 9619 } while (0) 9620 9621 #define HTT_PHY_TPC_STATS_AG_CAP_EXT2_ENABLED_M 0x00ff0000 9622 #define HTT_PHY_TPC_STATS_AG_CAP_EXT2_ENABLED_S 16 9623 9624 #define HTT_PHY_TPC_STATS_AG_CAP_EXT2_ENABLED_GET(_var) \ 9625 (((_var) & HTT_PHY_TPC_STATS_AG_CAP_EXT2_ENABLED_M) >> \ 9626 HTT_PHY_TPC_STATS_AG_CAP_EXT2_ENABLED_S) 9627 /* provide properly-named macro */ 9628 #define HTT_STATS_PHY_TPC_STATS_ARRAY_GAIN_CAP_EXT2_ENABLED_GET(_var) \ 9629 HTT_PHY_TPC_STATS_AG_CAP_EXT2_ENABLED_GET(_var) 9630 #define HTT_PHY_TPC_STATS_AG_CAP_EXT2_ENABLED_SET(_var, _val) \ 9631 do { \ 9632 HTT_CHECK_SET_VAL(HTT_PHY_TPC_STATS_AG_CAP_EXT2_ENABLED, _val); \ 9633 ((_var) &= ~(HTT_PHY_TPC_STATS_AG_CAP_EXT2_ENABLED_M)); \ 9634 ((_var) |= ((_val) << HTT_PHY_TPC_STATS_AG_CAP_EXT2_ENABLED_S)); \ 9635 } while (0) 9636 9637 #define HTT_PHY_TPC_STATS_CTL_FLAG_M 0xff000000 9638 #define HTT_PHY_TPC_STATS_CTL_FLAG_S 24 9639 9640 #define HTT_PHY_TPC_STATS_CTL_FLAG_GET(_var) \ 9641 (((_var) & HTT_PHY_TPC_STATS_CTL_FLAG_M) >> \ 9642 HTT_PHY_TPC_STATS_CTL_FLAG_S) 9643 /* provide properly-named macro */ 9644 #define HTT_STATS_PHY_TPC_STATS_CTL_FLAG_GET(_var) \ 9645 HTT_PHY_TPC_STATS_CTL_FLAG_GET(_var) 9646 #define HTT_PHY_TPC_STATS_CTL_FLAG_SET(_var, _val) \ 9647 do { \ 9648 HTT_CHECK_SET_VAL(HTT_PHY_TPC_STATS_CTL_FLAG, _val); \ 9649 ((_var) &= ~(HTT_PHY_TPC_STATS_CTL_FLAG_M)); \ 9650 ((_var) |= ((_val) << HTT_PHY_TPC_STATS_CTL_FLAG_S)); \ 9651 } while (0) 9652 9653 typedef struct { 9654 htt_tlv_hdr_t tlv_hdr; 9655 9656 /** current pdev_id */ 9657 A_UINT32 pdev_id; 9658 9659 /** Tranmsit power control scaling related configurations */ 9660 A_UINT32 tx_power_scale; 9661 A_UINT32 tx_power_scale_db; 9662 9663 /** Minimum negative tx power supported by the target */ 9664 A_INT32 min_negative_tx_power; 9665 9666 /** current configured CTL domain */ 9667 A_UINT32 reg_ctl_domain; 9668 9669 /** Regulatory power information for the current channel */ 9670 A_INT32 max_reg_allowed_power[HTT_STATS_MAX_CHAINS]; 9671 A_INT32 max_reg_allowed_power_6g[HTT_STATS_MAX_CHAINS]; 9672 /** channel max regulatory power in 0.5dB */ 9673 A_UINT32 twice_max_rd_power; 9674 9675 /** current channel and home channel's maximum possible tx power */ 9676 A_INT32 max_tx_power; 9677 A_INT32 home_max_tx_power; 9678 9679 /** channel's Power Spectral Density */ 9680 A_UINT32 psd_power; 9681 /** channel's EIRP power */ 9682 A_UINT32 eirp_power; 9683 /** 6G channel power mode 9684 * 0-LPI, 1-SP, 2-VLPI and 3-SP_CLIENT power mode 9685 */ 9686 A_UINT32 power_type_6ghz; 9687 9688 /** sub-band channels and corresponding Tx-power */ 9689 A_UINT32 sub_band_cfreq[HTT_MAX_CH_PWR_INFO_SIZE]; 9690 A_UINT32 sub_band_txpower[HTT_MAX_CH_PWR_INFO_SIZE]; 9691 9692 /** array_gain_cap: 9693 * CTL Array Gain cap, units are dB 9694 * The lower-triangular portion of this square matrix is stored, i.e. 9695 * array element 0 stores matrix element (0,0) 9696 * array element 1 stores matrix element (1,0) 9697 * array element 2 stores matrix element (1,1) 9698 * array element 3 stores matrix element (2,0) 9699 * ... 9700 * array element 35 stores matrix element (7,7) 9701 */ 9702 A_INT32 array_gain_cap[HTT_STATS_MAX_CHAINS * ((HTT_STATS_MAX_CHAINS/2)+1)]; 9703 union { 9704 struct { 9705 A_UINT32 9706 ctl_region_grp:8, /** Group to which the ctl region belongs */ 9707 sub_band_index:8, /** Frequency subband index */ 9708 /** Array Gain Cap Ext2 feature enablement status */ 9709 array_gain_cap_ext2_enabled:8, 9710 /** ctl_flag: 9711 * 1st bit ULOFDMA supported 9712 * 2nd bit DLOFDMA shared Exception supported 9713 */ 9714 ctl_flag:8; 9715 }; 9716 A_UINT32 ctl_args; 9717 }; 9718 /** max_reg_only_allowed_power: 9719 * units = 0.25dBm 9720 */ 9721 A_INT32 max_reg_only_allowed_power[HTT_STATS_MAX_CHAINS]; 9722 9723 /** number of PPDUs transmitted for each number of tx chains */ 9724 A_UINT32 tx_num_chains[HTT_STATS_MAX_CHAINS]; 9725 9726 /** tx_power: 9727 * Number of PPDUs transmitted with each power level >= 0 dBm. 9728 * tx_power[0]: number of PPDUs with tx power in the [0 dBm, 1 dBm) range 9729 * tx_power[1]: number of PPDUs with tx power in the [1 dBm, 2 dBm) range 9730 * ... 9731 * tx_power[30]: number of PPDUs with tx power in the [30 dBm, 31 dBm) range 9732 * tx_power[31]: number of PPDUs with tx power >= 31 dBm 9733 */ 9734 A_UINT32 tx_power[HTT_MAX_POWER_LEVEL]; 9735 9736 /** tx_power_neg: 9737 * Number of PPDUs transmitted with each power level < 0 dBm. 9738 * tx_power_neg[0]: cnt of PPDUs with tx pwr in the [-1 dBm, 0 dBm) range 9739 * tx_power_neg[1]: cnt of PPDUs with tx pwr in the [-2 dBm, -1 dBm) range 9740 * ... 9741 * tx_power_neg[8]: cnt of PPDUs with tx pwr in the [-9 dBm, -8 dBm) range 9742 * tx_power_neg[9]: cnt of PPDUs with tx pwr < -9 dBm 9743 */ 9744 A_UINT32 tx_power_neg[HTT_MAX_NEGATIVE_POWER_LEVEL]; 9745 } htt_stats_phy_tpc_stats_tlv; 9746 /* preserve old name alias for new name consistent with the tag name */ 9747 typedef htt_stats_phy_tpc_stats_tlv htt_phy_tpc_stats_tlv; 9748 9749 /* NOTE: 9750 * This structure is for documentation, and cannot be safely used directly. 9751 * Instead, use the constituent TLV structures to fill/parse. 9752 */ 9753 #ifdef ATH_TARGET 9754 typedef struct { 9755 htt_stats_phy_counters_tlv phy_counters; 9756 htt_stats_phy_stats_tlv phy_stats; 9757 htt_stats_phy_reset_counters_tlv phy_reset_counters; 9758 htt_stats_phy_reset_stats_tlv phy_reset_stats; 9759 htt_stats_phy_tpc_stats_tlv phy_tpc_stats; 9760 } htt_phy_counters_and_phy_stats_t; 9761 #endif /* ATH_TARGET */ 9762 9763 /* NOTE: 9764 * This structure is for documentation, and cannot be safely used directly. 9765 * Instead, use the constituent TLV structures to fill/parse. 9766 */ 9767 #ifdef ATH_TARGET 9768 typedef struct { 9769 htt_stats_soc_txrx_stats_common_tlv soc_common_stats; 9770 htt_stats_vdev_txrx_stats_hw_stats_tlv vdev_hw_stats[1/*or more*/]; 9771 } htt_vdevs_txrx_stats_t; 9772 #endif /* ATH_TARGET */ 9773 9774 typedef struct { 9775 union { 9776 A_UINT32 word32; 9777 struct { 9778 A_UINT32 9779 success: 16, 9780 fail: 16; 9781 }; 9782 }; 9783 } htt_stats_strm_gen_mpdus_cntr_t; 9784 9785 typedef struct { 9786 /* MSDU queue identification */ 9787 union { 9788 A_UINT32 word32; 9789 struct { 9790 A_UINT32 9791 peer_id: 16, 9792 tid: 4, /* only TIDs 0-7 actually expected to be used */ 9793 htt_qtype: 4, /* refer to HTT_MSDUQ_INDEX */ 9794 reserved: 8; 9795 }; 9796 }; 9797 } htt_stats_strm_msdu_queue_id; 9798 9799 #define HTT_STATS_STRM_GEN_MPDUS_QUEUE_ID_PEER_ID_GET(word) \ 9800 ((word >> 0) & 0xffff) 9801 #define HTT_STATS_STRM_GEN_MPDUS_QUEUE_ID_TID_GET(word) \ 9802 ((word >> 16) & 0xf) 9803 #define HTT_STATS_STRM_GEN_MPDUS_QUEUE_ID_HTT_QTYPE_GET(word) \ 9804 ((word >> 20) & 0xf) 9805 9806 #define HTT_STATS_STRM_GEN_MPDUS_SVC_INTERVAL_SUCCESS_GET(word) \ 9807 ((word >> 0) & 0xffff) 9808 #define HTT_STATS_STRM_GEN_MPDUS_SVC_INTERVAL_FAIL_GET(word) \ 9809 ((word >> 16) & 0xffff) 9810 9811 #define HTT_STATS_STRM_GEN_MPDUS_BURST_SIZE_SUCCESS_GET(word) \ 9812 ((word >> 0) & 0xffff) 9813 #define HTT_STATS_STRM_GEN_MPDUS_BURST_SIZE_FAIL_GET(word) \ 9814 ((word >> 16) & 0xffff) 9815 9816 typedef struct { 9817 htt_tlv_hdr_t tlv_hdr; 9818 htt_stats_strm_msdu_queue_id queue_id; 9819 htt_stats_strm_gen_mpdus_cntr_t svc_interval; 9820 htt_stats_strm_gen_mpdus_cntr_t burst_size; 9821 } htt_stats_strm_gen_mpdus_tlv; 9822 /* preserve old name alias for new name consistent with the tag name */ 9823 typedef htt_stats_strm_gen_mpdus_tlv htt_stats_strm_gen_mpdus_tlv_t; 9824 9825 typedef struct { 9826 htt_tlv_hdr_t tlv_hdr; 9827 htt_stats_strm_msdu_queue_id queue_id; 9828 struct { 9829 union { 9830 A_UINT32 timestamp_prior__timestamp_now__word; 9831 struct { 9832 A_UINT32 9833 timestamp_prior_ms: 16, 9834 timestamp_now_ms: 16; 9835 }; 9836 }; 9837 union { 9838 A_UINT32 interval_spec__margin__word; 9839 struct { 9840 A_UINT32 9841 interval_spec_ms: 16, 9842 margin_ms: 16; 9843 }; 9844 }; 9845 } svc_interval; 9846 struct { 9847 union { 9848 A_UINT32 consumed_bytes_orig__consumed_bytes_final__word; 9849 struct { 9850 A_UINT32 9851 /* consumed_bytes_orig: 9852 * Raw count (actually estimate) of how many bytes were 9853 * removed from the MSDU queue by the GEN_MPDUS operation. 9854 */ 9855 consumed_bytes_orig: 16, 9856 /* consumed_bytes_final: 9857 * Adjusted count of removed bytes that incorporates 9858 * normalizing by the actual service interval compared to 9859 * the expected service interval. 9860 * This allows the burst size computation to be independent 9861 * of whether the target is doing GEN_MPDUS at only the 9862 * service interval, or substantially more often than the 9863 * service interval. 9864 * consumed_bytes_final = consumed_bytes_orig / 9865 * (svc_interval / ref_svc_interval) 9866 */ 9867 consumed_bytes_final: 16; 9868 }; 9869 }; 9870 union { 9871 A_UINT32 remaining_bytes__word; 9872 struct { 9873 A_UINT32 9874 remaining_bytes: 16, 9875 reserved: 16; 9876 }; 9877 }; 9878 union { 9879 A_UINT32 burst_size_spec__margin_bytes__word; 9880 struct { 9881 A_UINT32 9882 burst_size_spec: 16, 9883 margin_bytes: 16; 9884 }; 9885 }; 9886 } burst_size; 9887 } htt_stats_strm_gen_mpdus_details_tlv; 9888 /* preserve old name alias for new name consistent with the tag name */ 9889 typedef htt_stats_strm_gen_mpdus_details_tlv 9890 htt_stats_strm_gen_mpdus_details_tlv_t; 9891 9892 #define HTT_STATS_STRM_GEN_MPDUS_DETAILS_QUEUE_ID_PEER_ID_GET(word) \ 9893 ((word >> 0) & 0xffff) 9894 #define HTT_STATS_STRM_GEN_MPDUS_DETAILS_QUEUE_ID_TID_GET(word) \ 9895 ((word >> 16) & 0xf) 9896 #define HTT_STATS_STRM_GEN_MPDUS_DETAILS_QUEUE_ID_HTT_QTYPE_GET(word) \ 9897 ((word >> 20) & 0xf) 9898 9899 #define HTT_STATS_STRM_GEN_MPDUS_DETAILS_SVC_INTERVAL_TIMESTAMP_PRIOR_MS_GET(word) \ 9900 ((word >> 0) & 0xffff) 9901 #define HTT_STATS_STRM_GEN_MPDUS_DETAILS_SVC_INTERVAL_TIMESTAMP_NOW_MS_GET(word) \ 9902 ((word >> 16) & 0xffff) 9903 9904 #define HTT_STATS_STRM_GEN_MPDUS_DETAILS_SVC_INTERVAL_INTERVAL_SPEC_MS_GET(word) \ 9905 ((word >> 0) & 0xffff) 9906 #define HTT_STATS_STRM_GEN_MPDUS_DETAILS_SVC_INTERVAL_MARGIN_MS_GET(word) \ 9907 ((word >> 16) & 0xffff) 9908 9909 #define HTT_STATS_STRM_GEN_MPDUS_DETAILS_BURST_SIZE_CONSUMED_BYTES_ORIG_GET(word) \ 9910 ((word >> 0) & 0xffff) 9911 #define HTT_STATS_STRM_GEN_MPDUS_DETAILS_BURST_SIZE_CONSUMED_BYTES_FINAL_GET(word) \ 9912 ((word >> 16) & 0xffff) 9913 #define HTT_STATS_STRM_GEN_MPDUS_DETAILS_BURST_SIZE_REMAINING_BYTES_GET(word) \ 9914 ((word >> 0) & 0xffff) 9915 #define HTT_STATS_STRM_GEN_MPDUS_DETAILS_BURST_SIZE_BURST_SIZE_SPEC_GET(word) \ 9916 ((word >> 0) & 0xffff) 9917 #define HTT_STATS_STRM_GEN_MPDUS_DETAILS_BURST_SIZE_MARGIN_BYTES_GET(word) \ 9918 ((word >> 16) & 0xffff) 9919 9920 typedef struct { 9921 htt_tlv_hdr_t tlv_hdr; 9922 A_UINT32 reset_count; 9923 /** lower portion (bits 31:0) of reset time, in milliseconds */ 9924 A_UINT32 reset_time_lo_ms; 9925 /** upper portion (bits 63:32) of reset time, in milliseconds */ 9926 A_UINT32 reset_time_hi_ms; 9927 /** lower portion (bits 31:0) of disengage time, in milliseconds */ 9928 A_UINT32 disengage_time_lo_ms; 9929 /** upper portion (bits 63:32) of disengage time, in milliseconds */ 9930 A_UINT32 disengage_time_hi_ms; 9931 /** lower portion (bits 31:0) of engage time, in milliseconds */ 9932 A_UINT32 engage_time_lo_ms; 9933 /** upper portion (bits 63:32) of engage time, in milliseconds */ 9934 A_UINT32 engage_time_hi_ms; 9935 A_UINT32 disengage_count; 9936 A_UINT32 engage_count; 9937 A_UINT32 drain_dest_ring_mask; 9938 } htt_stats_dmac_reset_stats_tlv; 9939 /* preserve old name alias for new name consistent with the tag name */ 9940 typedef htt_stats_dmac_reset_stats_tlv htt_dmac_reset_stats_tlv; 9941 9942 9943 /* Support up to 640 MHz mode for future expansion */ 9944 #define HTT_PUNCTURE_STATS_MAX_SUBBAND_COUNT 32 9945 9946 #define HTT_PDEV_PUNCTURE_STATS_MAC_ID_M 0x000000ff 9947 #define HTT_PDEV_PUNCTURE_STATS_MAC_ID_S 0 9948 9949 #define HTT_PDEV_PUNCTURE_STATS_MAC_ID_GET(_var) \ 9950 (((_var) & HTT_PDEV_PUNCTURE_STATS_MAC_ID_M) >> \ 9951 HTT_PDEV_PUNCTURE_STATS_MAC_ID_S) 9952 9953 #define HTT_PDEV_PUNCTURE_STATS_MAC_ID_SET(_var, _val) \ 9954 do { \ 9955 HTT_CHECK_SET_VAL(HTT_PDEV_PUNCTURE_STATS_MAC_ID, _val); \ 9956 ((_var) |= ((_val) << HTT_PDEV_PUNCTURE_STATS_MAC_ID_S)); \ 9957 } while (0) 9958 9959 /* 9960 * TLV used to provide puncturing related stats for TX/RX and each PPDU type. 9961 */ 9962 typedef struct { 9963 htt_tlv_hdr_t tlv_hdr; 9964 9965 /** 9966 * BIT [ 7 : 0] :- mac_id 9967 * BIT [31 : 8] :- reserved 9968 */ 9969 union { 9970 struct { 9971 A_UINT32 mac_id: 8, 9972 reserved: 24; 9973 }; 9974 A_UINT32 mac_id__word; 9975 }; 9976 9977 /* 9978 * Stats direction (TX/RX). Enum value from HTT_STATS_DIRECTION. 9979 */ 9980 A_UINT32 direction; 9981 9982 /* 9983 * Preamble type. Enum value from HTT_STATS_PREAM_TYPE. 9984 * 9985 * Note that for although OFDM rates don't technically support 9986 * "puncturing", this TLV can be used to indicate the 20 MHz sub-bands 9987 * utilized for OFDM legacy duplicate packets, which are also used during 9988 * puncturing sequences. 9989 */ 9990 A_UINT32 preamble; 9991 9992 /* 9993 * Stats PPDU type. Enum value from HTT_STATS_PPDU_TYPE. 9994 */ 9995 A_UINT32 ppdu_type; 9996 9997 /* 9998 * Indicates the number of valid elements in the 9999 * "num_subbands_used_cnt" array, and must be <= 10000 * HTT_PUNCTURE_STATS_MAX_SUBBAND_COUNT. 10001 * 10002 * Also indicates how many bits in the last_used_pattern_mask may be 10003 * non-zero. 10004 */ 10005 A_UINT32 subband_count; 10006 10007 /* 10008 * The last used transmit 20 MHz subband mask. Bit 0 represents the lowest 10009 * 20 MHz subband mask, bit 1 the second lowest, and so on. 10010 * 10011 * All 32 bits are valid and will be used for expansion to higher BW modes. 10012 */ 10013 A_UINT32 last_used_pattern_mask; 10014 10015 10016 /* 10017 * Number of array elements with valid values is equal to "subband_count". 10018 * If subband_count is < HTT_PUNCTURE_STATS_MAX_SUBBAND_COUNT, the 10019 * remaining elements will be implicitly set to 0x0. 10020 * 10021 * The array index is the number of 20 MHz subbands utilized during TX/RX, 10022 * and the counter value at that index is the number of times that subband 10023 * count was used. 10024 * 10025 * The count is incremented once for each OTA PPDU transmitted / received. 10026 */ 10027 A_UINT32 num_subbands_used_cnt[HTT_PUNCTURE_STATS_MAX_SUBBAND_COUNT]; 10028 } htt_stats_pdev_puncture_stats_tlv; 10029 /* preserve old name alias for new name consistent with the tag name */ 10030 typedef htt_stats_pdev_puncture_stats_tlv htt_pdev_puncture_stats_tlv; 10031 10032 #define HTT_STATS_PDEV_PUNCTURE_STATS_MAC_ID_GET(word) ((word >> 0) & 0xff) 10033 10034 enum { 10035 HTT_STATS_CAL_PROF_COLD_BOOT = 0, 10036 HTT_STATS_CAL_PROF_FULL_CHAN_SWITCH = 1, 10037 HTT_STATS_CAL_PROF_SCAN_CHAN_SWITCH = 2, 10038 HTT_STATS_CAL_PROF_DPD_SPLIT_CAL = 3, 10039 10040 HTT_STATS_MAX_PROF_CAL = 4, 10041 }; 10042 10043 #define HTT_STATS_MAX_CAL_IDX_CNT 8 10044 typedef struct { /* DEPRECATED */ 10045 10046 htt_tlv_hdr_t tlv_hdr; 10047 10048 A_UINT8 latency_prof_name[HTT_STATS_MAX_PROF_CAL][HTT_STATS_MAX_PROF_STATS_NAME_LEN]; 10049 10050 /** To verify whether prof cal is enabled or not */ 10051 A_UINT32 enable; 10052 10053 /** current pdev_id */ 10054 A_UINT32 pdev_id; 10055 10056 /** The cnt is incremented when each time the calindex takes place */ 10057 A_UINT32 cnt[HTT_STATS_MAX_PROF_CAL][HTT_STATS_MAX_CAL_IDX_CNT]; 10058 10059 /** Minimum time taken to complete the calibration - in us */ 10060 A_UINT32 min[HTT_STATS_MAX_PROF_CAL][HTT_STATS_MAX_CAL_IDX_CNT]; 10061 10062 /** Maximum time taken to complete the calibration -in us */ 10063 A_UINT32 max[HTT_STATS_MAX_PROF_CAL][HTT_STATS_MAX_CAL_IDX_CNT]; 10064 10065 /** Time taken by the cal for its final time execution - in us */ 10066 A_UINT32 last[HTT_STATS_MAX_PROF_CAL][HTT_STATS_MAX_CAL_IDX_CNT]; 10067 10068 /** Total time taken - in us */ 10069 A_UINT32 tot[HTT_STATS_MAX_PROF_CAL][HTT_STATS_MAX_CAL_IDX_CNT]; 10070 10071 /** hist_intvl - by default will be set to 2000 us */ 10072 A_UINT32 hist_intvl[HTT_STATS_MAX_PROF_CAL][HTT_STATS_MAX_CAL_IDX_CNT]; 10073 10074 /** 10075 * If last is less than hist_intvl, then hist[0]++, 10076 * If last is less than hist_intvl << 1, then hist[1]++, 10077 * otherwise hist[2]++. 10078 */ 10079 A_UINT32 hist[HTT_STATS_MAX_PROF_CAL][HTT_STATS_MAX_CAL_IDX_CNT][HTT_INTERRUPTS_LATENCY_PROFILE_MAX_HIST]; 10080 10081 /** Pf_last will log the current no of page faults */ 10082 A_UINT32 pf_last[HTT_STATS_MAX_PROF_CAL][HTT_STATS_MAX_CAL_IDX_CNT]; 10083 10084 /** Sum of all page faults happened */ 10085 A_UINT32 pf_tot[HTT_STATS_MAX_PROF_CAL][HTT_STATS_MAX_CAL_IDX_CNT]; 10086 10087 /** If pf_last > pf_max then pf_max = pf_last */ 10088 A_UINT32 pf_max[HTT_STATS_MAX_PROF_CAL][HTT_STATS_MAX_CAL_IDX_CNT]; 10089 10090 /** 10091 * For each cal profile, only certain no of cal indices were invoked, 10092 * this member will store what all the indices got invoked per each 10093 * cal profile 10094 */ 10095 A_UINT32 enabledCalIdx[HTT_STATS_MAX_PROF_CAL][HTT_STATS_MAX_CAL_IDX_CNT]; 10096 10097 /** No of indices invoked per each cal profile */ 10098 A_UINT32 CalCnt[HTT_STATS_MAX_PROF_CAL]; 10099 } htt_stats_latency_prof_cal_stats_tlv; /* DEPRECATED */ 10100 /* preserve old name alias for new name consistent with the tag name */ 10101 typedef htt_stats_latency_prof_cal_stats_tlv htt_latency_prof_cal_stats_tlv; /* DEPRECATED */ 10102 10103 typedef struct { 10104 /** The cnt is incremented when each time the calindex takes place */ 10105 A_UINT32 cnt; 10106 10107 /** Minimum time taken to complete the calibration - in us */ 10108 A_UINT32 min; 10109 10110 /** Maximum time taken to complete the calibration -in us */ 10111 A_UINT32 max; 10112 10113 /** Time taken by the cal for its final time execution - in us */ 10114 A_UINT32 last; 10115 10116 /** Total time taken - in us */ 10117 A_UINT32 tot; 10118 10119 /** hist_intvl - in us, by default will be set to 2000 us */ 10120 A_UINT32 hist_intvl; 10121 10122 /** 10123 * If last is less than hist_intvl, then hist[0]++, 10124 * If last is less than hist_intvl << 1, then hist[1]++, 10125 * otherwise hist[2]++. 10126 */ 10127 A_UINT32 hist[HTT_INTERRUPTS_LATENCY_PROFILE_MAX_HIST]; 10128 10129 /** pf_last will log the current no of page faults */ 10130 A_UINT32 pf_last; 10131 10132 /** Sum of all page faults happened */ 10133 A_UINT32 pf_tot; 10134 10135 /** If pf_last > pf_max then pf_max = pf_last */ 10136 A_UINT32 pf_max; 10137 10138 /** 10139 * For each cal profile, only certain no of cal indices were invoked, 10140 * this member will store what all the indices got invoked per each 10141 * cal profile 10142 */ 10143 A_UINT32 enabled_cal_idx; 10144 10145 /* 10146 * NOTE: due to backwards-compatibility requirements, 10147 * no fields can be added to this struct. 10148 */ 10149 } htt_stats_latency_prof_cal_data; 10150 10151 typedef struct { 10152 10153 htt_tlv_hdr_t tlv_hdr; 10154 10155 /** To verify whether prof cal is enabled or not */ 10156 A_UINT32 enable; 10157 10158 /** current pdev_id */ 10159 A_UINT32 pdev_id; 10160 10161 /** No of indices invoked per each cal profile */ 10162 A_UINT32 cal_cnt[HTT_STATS_MAX_PROF_CAL]; 10163 10164 /** Latency Cal Profile name */ 10165 A_UINT8 latency_prof_name[HTT_STATS_MAX_PROF_CAL][HTT_STATS_MAX_PROF_STATS_NAME_LEN]; 10166 10167 /** Latency Cal data */ 10168 htt_stats_latency_prof_cal_data latency_data[HTT_STATS_MAX_PROF_CAL][HTT_STATS_MAX_CAL_IDX_CNT]; 10169 } htt_stats_latency_prof_cal_data_tlv; 10170 10171 #define HTT_ML_PEER_EXT_DETAILS_PEER_ASSOC_IPC_RECVD_M 0x0000003F 10172 #define HTT_ML_PEER_EXT_DETAILS_PEER_ASSOC_IPC_RECVD_S 0 10173 #define HTT_ML_PEER_EXT_DETAILS_SCHED_PEER_DELETE_RECVD_M 0x00000FC0 10174 #define HTT_ML_PEER_EXT_DETAILS_SCHED_PEER_DELETE_RECVD_S 6 10175 #define HTT_ML_PEER_EXT_DETAILS_MLD_AST_INDEX_M 0x0FFFF000 10176 #define HTT_ML_PEER_EXT_DETAILS_MLD_AST_INDEX_S 12 10177 10178 #define HTT_ML_PEER_EXT_DETAILS_PEER_ASSOC_IPC_RECVD_GET(_var) \ 10179 (((_var) & HTT_ML_PEER_EXT_DETAILS_PEER_ASSOC_IPC_RECVD_M) >> \ 10180 HTT_ML_PEER_EXT_DETAILS_PEER_ASSOC_IPC_RECVD_S) 10181 /* provide properly-named macro */ 10182 #define HTT_STATS_ML_PEER_EXT_DETAILS_PEER_ASSOC_IPC_RECVD_GET(_var) \ 10183 HTT_ML_PEER_EXT_DETAILS_PEER_ASSOC_IPC_RECVD_GET(_var) 10184 10185 #define HTT_ML_PEER_EXT_DETAILS_PEER_ASSOC_IPC_RECVD_SET(_var, _val) \ 10186 do { \ 10187 HTT_CHECK_SET_VAL(HTT_ML_PEER_EXT_DETAILS_PEER_ASSOC_IPC_RECVD, _val); \ 10188 ((_var) &= ~(HTT_ML_PEER_EXT_DETAILS_PEER_ASSOC_IPC_RECVD_M)); \ 10189 ((_var) |= ((_val) << HTT_ML_PEER_EXT_DETAILS_PEER_ASSOC_IPC_RECVD_S)); \ 10190 } while (0) 10191 10192 #define HTT_ML_PEER_EXT_DETAILS_SCHED_PEER_DELETE_RECVD_GET(_var) \ 10193 (((_var) & HTT_ML_PEER_EXT_DETAILS_SCHED_PEER_DELETE_RECVD_M) >> \ 10194 HTT_ML_PEER_EXT_DETAILS_SCHED_PEER_DELETE_RECVD_S) 10195 /* provide properly-named macro */ 10196 #define HTT_STATS_ML_PEER_EXT_DETAILS_SCHED_PEER_DELETE_RECVD_GET(_var) \ 10197 HTT_ML_PEER_EXT_DETAILS_SCHED_PEER_DELETE_RECVD_GET(_var) 10198 10199 #define HTT_ML_PEER_EXT_DETAILS_SCHED_PEER_DELETE_RECVD_SET(_var, _val) \ 10200 do { \ 10201 HTT_CHECK_SET_VAL(HTT_ML_PEER_EXT_DETAILS_SCHED_PEER_DELETE_RECVD, _val); \ 10202 ((_var) &= ~(HTT_ML_PEER_EXT_DETAILS_SCHED_PEER_DELETE_RECVD_M)); \ 10203 ((_var) |= ((_val) << HTT_ML_PEER_EXT_DETAILS_SCHED_PEER_DELETE_RECVD_S)); \ 10204 } while (0) 10205 10206 #define HTT_ML_PEER_EXT_DETAILS_MLD_AST_INDEX_GET(_var) \ 10207 (((_var) & HTT_ML_PEER_EXT_DETAILS_MLD_AST_INDEX_M) >> \ 10208 HTT_ML_PEER_EXT_DETAILS_MLD_AST_INDEX_S) 10209 /* provide properly-named macro */ 10210 #define HTT_STATS_ML_PEER_EXT_DETAILS_MLD_AST_INDEX_GET(_var) \ 10211 HTT_ML_PEER_EXT_DETAILS_MLD_AST_INDEX_GET(_var) 10212 10213 #define HTT_ML_PEER_EXT_DETAILS_MLD_AST_INDEX_SET(_var, _val) \ 10214 do { \ 10215 HTT_CHECK_SET_VAL(HTT_ML_PEER_EXT_DETAILS_MLD_AST_INDEX, _val); \ 10216 ((_var) &= ~(HTT_ML_PEER_EXT_DETAILS_MLD_AST_INDEX_M)); \ 10217 ((_var) |= ((_val) << HTT_ML_PEER_EXT_DETAILS_MLD_AST_INDEX_S)); \ 10218 } while (0) 10219 10220 typedef struct { 10221 htt_tlv_hdr_t tlv_hdr; 10222 union { 10223 struct { 10224 A_UINT32 peer_assoc_ipc_recvd : 6, 10225 sched_peer_delete_recvd : 6, 10226 mld_ast_index : 16, 10227 reserved : 4; 10228 }; 10229 A_UINT32 msg_dword_1; 10230 }; 10231 } htt_stats_ml_peer_ext_details_tlv; 10232 /* preserve old name alias for new name consistent with the tag name */ 10233 typedef htt_stats_ml_peer_ext_details_tlv htt_ml_peer_ext_details_tlv; 10234 10235 #define HTT_ML_LINK_INFO_VALID_M 0x00000001 10236 #define HTT_ML_LINK_INFO_VALID_S 0 10237 #define HTT_ML_LINK_INFO_ACTIVE_M 0x00000002 10238 #define HTT_ML_LINK_INFO_ACTIVE_S 1 10239 #define HTT_ML_LINK_INFO_PRIMARY_M 0x00000004 10240 #define HTT_ML_LINK_INFO_PRIMARY_S 2 10241 #define HTT_ML_LINK_INFO_ASSOC_LINK_M 0x00000008 10242 #define HTT_ML_LINK_INFO_ASSOC_LINK_S 3 10243 #define HTT_ML_LINK_INFO_CHIP_ID_M 0x00000070 10244 #define HTT_ML_LINK_INFO_CHIP_ID_S 4 10245 #define HTT_ML_LINK_INFO_IEEE_LINK_ID_M 0x00007F80 10246 #define HTT_ML_LINK_INFO_IEEE_LINK_ID_S 7 10247 #define HTT_ML_LINK_INFO_HW_LINK_ID_M 0x00038000 10248 #define HTT_ML_LINK_INFO_HW_LINK_ID_S 15 10249 #define HTT_ML_LINK_INFO_LOGICAL_LINK_ID_M 0x000C0000 10250 #define HTT_ML_LINK_INFO_LOGICAL_LINK_ID_S 18 10251 #define HTT_ML_LINK_INFO_MASTER_LINK_M 0x00100000 10252 #define HTT_ML_LINK_INFO_MASTER_LINK_S 20 10253 #define HTT_ML_LINK_INFO_ANCHOR_LINK_M 0x00200000 10254 #define HTT_ML_LINK_INFO_ANCHOR_LINK_S 21 10255 #define HTT_ML_LINK_INFO_INITIALIZED_M 0x00400000 10256 #define HTT_ML_LINK_INFO_INITIALIZED_S 22 10257 10258 #define HTT_ML_LINK_INFO_SW_PEER_ID_M 0x0000ffff 10259 #define HTT_ML_LINK_INFO_SW_PEER_ID_S 0 10260 #define HTT_ML_LINK_INFO_VDEV_ID_M 0x00ff0000 10261 #define HTT_ML_LINK_INFO_VDEV_ID_S 16 10262 10263 #define HTT_ML_LINK_INFO_VALID_GET(_var) \ 10264 (((_var) & HTT_ML_LINK_INFO_VALID_M) >> \ 10265 HTT_ML_LINK_INFO_VALID_S) 10266 /* provide properly-named macro */ 10267 #define HTT_STATS_ML_LINK_INFO_DETAILS_VALID_GET(_var) \ 10268 HTT_ML_LINK_INFO_VALID_GET(_var) 10269 10270 #define HTT_ML_LINK_INFO_VALID_SET(_var, _val) \ 10271 do { \ 10272 HTT_CHECK_SET_VAL(HTT_ML_LINK_INFO_VALID, _val); \ 10273 ((_var) &= ~(HTT_ML_LINK_INFO_VALID_M)); \ 10274 ((_var) |= ((_val) << HTT_ML_LINK_INFO_VALID_S)); \ 10275 } while (0) 10276 10277 #define HTT_ML_LINK_INFO_ACTIVE_GET(_var) \ 10278 (((_var) & HTT_ML_LINK_INFO_ACTIVE_M) >> \ 10279 HTT_ML_LINK_INFO_ACTIVE_S) 10280 /* provide properly-named macro */ 10281 #define HTT_STATS_ML_LINK_INFO_DETAILS_ACTIVE_GET(_var) \ 10282 HTT_ML_LINK_INFO_ACTIVE_GET(_var) 10283 10284 #define HTT_ML_LINK_INFO_ACTIVE_SET(_var, _val) \ 10285 do { \ 10286 HTT_CHECK_SET_VAL(HTT_ML_LINK_INFO_ACTIVE, _val); \ 10287 ((_var) &= ~(HTT_ML_LINK_INFO_ACTIVE_M)); \ 10288 ((_var) |= ((_val) << HTT_ML_LINK_INFO_ACTIVE_S)); \ 10289 } while (0) 10290 10291 #define HTT_ML_LINK_INFO_PRIMARY_GET(_var) \ 10292 (((_var) & HTT_ML_LINK_INFO_PRIMARY_M) >> \ 10293 HTT_ML_LINK_INFO_PRIMARY_S) 10294 /* provide properly-named macro */ 10295 #define HTT_STATS_ML_LINK_INFO_DETAILS_PRIMARY_GET(_var) \ 10296 HTT_ML_LINK_INFO_PRIMARY_GET(_var) 10297 10298 #define HTT_ML_LINK_INFO_PRIMARY_SET(_var, _val) \ 10299 do { \ 10300 HTT_CHECK_SET_VAL(HTT_ML_LINK_INFO_PRIMARY, _val); \ 10301 ((_var) &= ~(HTT_ML_LINK_INFO_PRIMARY_M)); \ 10302 ((_var) |= ((_val) << HTT_ML_LINK_INFO_PRIMARY_S)); \ 10303 } while (0) 10304 10305 #define HTT_ML_LINK_INFO_ASSOC_LINK_GET(_var) \ 10306 (((_var) & HTT_ML_LINK_INFO_ASSOC_LINK_M) >> \ 10307 HTT_ML_LINK_INFO_ASSOC_LINK_S) 10308 /* provide properly-named macro */ 10309 #define HTT_STATS_ML_LINK_INFO_DETAILS_ASSOC_LINK_GET(_var) \ 10310 HTT_ML_LINK_INFO_ASSOC_LINK_GET(_var) 10311 10312 #define HTT_ML_LINK_INFO_ASSOC_LINK_SET(_var, _val) \ 10313 do { \ 10314 HTT_CHECK_SET_VAL(HTT_ML_LINK_INFO_ASSOC_LINK, _val); \ 10315 ((_var) &= ~(HTT_ML_LINK_INFO_ASSOC_LINK_M)); \ 10316 ((_var) |= ((_val) << HTT_ML_LINK_INFO_ASSOC_LINK_S)); \ 10317 } while (0) 10318 10319 #define HTT_ML_LINK_INFO_CHIP_ID_GET(_var) \ 10320 (((_var) & HTT_ML_LINK_INFO_CHIP_ID_M) >> \ 10321 HTT_ML_LINK_INFO_CHIP_ID_S) 10322 /* provide properly-named macro */ 10323 #define HTT_STATS_ML_LINK_INFO_DETAILS_CHIP_ID_GET(_var) \ 10324 HTT_ML_LINK_INFO_CHIP_ID_GET(_var) 10325 10326 #define HTT_ML_LINK_INFO_CHIP_ID_SET(_var, _val) \ 10327 do { \ 10328 HTT_CHECK_SET_VAL(HTT_ML_LINK_INFO_CHIP_ID, _val); \ 10329 ((_var) &= ~(HTT_ML_LINK_INFO_CHIP_ID_M)); \ 10330 ((_var) |= ((_val) << HTT_ML_LINK_INFO_CHIP_ID_S)); \ 10331 } while (0) 10332 10333 #define HTT_ML_LINK_INFO_IEEE_LINK_ID_GET(_var) \ 10334 (((_var) & HTT_ML_LINK_INFO_IEEE_LINK_ID_M) >> \ 10335 HTT_ML_LINK_INFO_IEEE_LINK_ID_S) 10336 /* provide properly-named macro */ 10337 #define HTT_STATS_ML_LINK_INFO_DETAILS_IEEE_LINK_ID_GET(_var) \ 10338 HTT_ML_LINK_INFO_IEEE_LINK_ID_GET(_var) 10339 10340 #define HTT_ML_LINK_INFO_IEEE_LINK_ID_SET(_var, _val) \ 10341 do { \ 10342 HTT_CHECK_SET_VAL(HTT_ML_LINK_INFO_IEEE_LINK_ID, _val); \ 10343 ((_var) &= ~(HTT_ML_LINK_INFO_IEEE_LINK_ID_M)); \ 10344 ((_var) |= ((_val) << HTT_ML_LINK_INFO_IEEE_LINK_ID_S)); \ 10345 } while (0) 10346 10347 #define HTT_ML_LINK_INFO_HW_LINK_ID_GET(_var) \ 10348 (((_var) & HTT_ML_LINK_INFO_HW_LINK_ID_M) >> \ 10349 HTT_ML_LINK_INFO_HW_LINK_ID_S) 10350 /* provide properly-named macro */ 10351 #define HTT_STATS_ML_LINK_INFO_DETAILS_HW_LINK_ID_GET(_var) \ 10352 HTT_ML_LINK_INFO_HW_LINK_ID_GET(_var) 10353 10354 #define HTT_ML_LINK_INFO_HW_LINK_ID_SET(_var, _val) \ 10355 do { \ 10356 HTT_CHECK_SET_VAL(HTT_ML_LINK_INFO_HW_LINK_ID, _val); \ 10357 ((_var) &= ~(HTT_ML_LINK_INFO_HW_LINK_ID_M)); \ 10358 ((_var) |= ((_val) << HTT_ML_LINK_INFO_HW_LINK_ID_S)); \ 10359 } while (0) 10360 10361 #define HTT_ML_LINK_INFO_LOGICAL_LINK_ID_GET(_var) \ 10362 (((_var) & HTT_ML_LINK_INFO_LOGICAL_LINK_ID_M) >> \ 10363 HTT_ML_LINK_INFO_LOGICAL_LINK_ID_S) 10364 /* provide properly-named macro */ 10365 #define HTT_STATS_ML_LINK_INFO_DETAILS_LOGICAL_LINK_ID_GET(_var) \ 10366 HTT_ML_LINK_INFO_LOGICAL_LINK_ID_GET(_var) 10367 10368 #define HTT_ML_LINK_INFO_LOGICAL_LINK_ID_SET(_var, _val) \ 10369 do { \ 10370 HTT_CHECK_SET_VAL(HTT_ML_LINK_INFO_LOGICAL_LINK_ID, _val); \ 10371 ((_var) &= ~(HTT_ML_LINK_INFO_LOGICAL_LINK_ID_M)); \ 10372 ((_var) |= ((_val) << HTT_ML_LINK_INFO_LOGICAL_LINK_ID_S)); \ 10373 } while (0) 10374 10375 #define HTT_ML_LINK_INFO_MASTER_LINK_GET(_var) \ 10376 (((_var) & HTT_ML_LINK_INFO_MASTER_LINK_M) >> \ 10377 HTT_ML_LINK_INFO_MASTER_LINK_S) 10378 /* provide properly-named macro */ 10379 #define HTT_STATS_ML_LINK_INFO_DETAILS_MASTER_LINK_GET(_var) \ 10380 HTT_ML_LINK_INFO_MASTER_LINK_GET(_var) 10381 10382 #define HTT_ML_LINK_INFO_MASTER_LINK_SET(_var, _val) \ 10383 do { \ 10384 HTT_CHECK_SET_VAL(HTT_ML_LINK_INFO_MASTER_LINK, _val); \ 10385 ((_var) &= ~(HTT_ML_LINK_INFO_MASTER_LINK_M)); \ 10386 ((_var) |= ((_val) << HTT_ML_LINK_INFO_MASTER_LINK_S)); \ 10387 } while (0) 10388 10389 #define HTT_ML_LINK_INFO_ANCHOR_LINK_GET(_var) \ 10390 (((_var) & HTT_ML_LINK_INFO_ANCHOR_LINK_M) >> \ 10391 HTT_ML_LINK_INFO_ANCHOR_LINK_S) 10392 /* provide properly-named macro */ 10393 #define HTT_STATS_ML_LINK_INFO_DETAILS_ANCHOR_LINK_GET(_var) \ 10394 HTT_ML_LINK_INFO_ANCHOR_LINK_GET(_var) 10395 10396 #define HTT_ML_LINK_INFO_ANCHOR_LINK_SET(_var, _val) \ 10397 do { \ 10398 HTT_CHECK_SET_VAL(HTT_ML_LINK_INFO_ANCHOR_LINK, _val); \ 10399 ((_var) &= ~(HTT_ML_LINK_INFO_ANCHOR_LINK_M)); \ 10400 ((_var) |= ((_val) << HTT_ML_LINK_INFO_ANCHOR_LINK_S)); \ 10401 } while (0) 10402 10403 #define HTT_ML_LINK_INFO_INITIALIZED_GET(_var) \ 10404 (((_var) & HTT_ML_LINK_INFO_INITIALIZED_M) >> \ 10405 HTT_ML_LINK_INFO_INITIALIZED_S) 10406 /* provide properly-named macro */ 10407 #define HTT_STATS_ML_LINK_INFO_DETAILS_INITIALIZED_GET(_var) \ 10408 HTT_ML_LINK_INFO_INITIALIZED_GET(_var) 10409 10410 #define HTT_ML_LINK_INFO_INITIALIZED_SET(_var, _val) \ 10411 do { \ 10412 HTT_CHECK_SET_VAL(HTT_ML_LINK_INFO_INITIALIZED, _val); \ 10413 ((_var) &= ~(HTT_ML_LINK_INFO_INITIALIZED_M)); \ 10414 ((_var) |= ((_val) << HTT_ML_LINK_INFO_INITIALIZED_S)); \ 10415 } while (0) 10416 10417 #define HTT_ML_LINK_INFO_SW_PEER_ID_GET(_var) \ 10418 (((_var) & HTT_ML_LINK_INFO_SW_PEER_ID_M) >> \ 10419 HTT_ML_LINK_INFO_SW_PEER_ID_S) 10420 /* provide properly-named macro */ 10421 #define HTT_STATS_ML_LINK_INFO_DETAILS_SW_PEER_ID_GET(_var) \ 10422 HTT_ML_LINK_INFO_SW_PEER_ID_GET(_var) 10423 10424 #define HTT_ML_LINK_INFO_SW_PEER_ID_SET(_var, _val) \ 10425 do { \ 10426 HTT_CHECK_SET_VAL(HTT_ML_LINK_INFO_SW_PEER_ID, _val); \ 10427 ((_var) &= ~(HTT_ML_LINK_INFO_SW_PEER_ID_M)); \ 10428 ((_var) |= ((_val) << HTT_ML_LINK_INFO_SW_PEER_ID_S)); \ 10429 } while (0) 10430 10431 #define HTT_ML_LINK_INFO_VDEV_ID_GET(_var) \ 10432 (((_var) & HTT_ML_LINK_INFO_VDEV_ID_M) >> \ 10433 HTT_ML_LINK_INFO_VDEV_ID_S) 10434 /* provide properly-named macro */ 10435 #define HTT_STATS_ML_LINK_INFO_DETAILS_VDEV_ID_GET(_var) \ 10436 HTT_ML_LINK_INFO_VDEV_ID_GET(_var) 10437 10438 #define HTT_ML_LINK_INFO_VDEV_ID_SET(_var, _val) \ 10439 do { \ 10440 HTT_CHECK_SET_VAL(HTT_ML_LINK_INFO_VDEV_ID, _val); \ 10441 ((_var) &= ~(HTT_ML_LINK_INFO_VDEV_ID_M)); \ 10442 ((_var) |= ((_val) << HTT_ML_LINK_INFO_VDEV_ID_S)); \ 10443 } while (0) 10444 10445 typedef struct { 10446 htt_tlv_hdr_t tlv_hdr; 10447 union { 10448 struct { 10449 A_UINT32 valid : 1, 10450 active : 1, 10451 primary : 1, 10452 assoc_link : 1, 10453 chip_id : 3, 10454 ieee_link_id : 8, 10455 hw_link_id : 3, 10456 logical_link_id : 2, 10457 master_link : 1, 10458 anchor_link : 1, 10459 initialized : 1, 10460 reserved : 9; 10461 }; 10462 A_UINT32 msg_dword_1; 10463 }; 10464 10465 union { 10466 struct { 10467 A_UINT32 sw_peer_id : 16, 10468 vdev_id : 8, 10469 reserved1 : 8; 10470 }; 10471 A_UINT32 msg_dword_2; 10472 }; 10473 10474 A_UINT32 primary_tid_mask; 10475 } htt_stats_ml_link_info_details_tlv; 10476 /* preserve old name alias for new name consistent with the tag name */ 10477 typedef htt_stats_ml_link_info_details_tlv htt_ml_link_info_tlv; 10478 10479 #define HTT_ML_PEER_DETAILS_NUM_LINKS_M 0x00000003 10480 #define HTT_ML_PEER_DETAILS_NUM_LINKS_S 0 10481 #define HTT_ML_PEER_DETAILS_ML_PEER_ID_M 0x00003FFC 10482 #define HTT_ML_PEER_DETAILS_ML_PEER_ID_S 2 10483 #define HTT_ML_PEER_DETAILS_PRIMARY_LINK_IDX_M 0x0001C000 10484 #define HTT_ML_PEER_DETAILS_PRIMARY_LINK_IDX_S 14 10485 #define HTT_ML_PEER_DETAILS_PRIMARY_CHIP_ID_M 0x00060000 10486 #define HTT_ML_PEER_DETAILS_PRIMARY_CHIP_ID_S 17 10487 #define HTT_ML_PEER_DETAILS_LINK_INIT_COUNT_M 0x00380000 10488 #define HTT_ML_PEER_DETAILS_LINK_INIT_COUNT_S 19 10489 #define HTT_ML_PEER_DETAILS_NON_STR_M 0x00400000 10490 #define HTT_ML_PEER_DETAILS_NON_STR_S 22 10491 #define HTT_ML_PEER_DETAILS_IS_EMLSR_ACTIVE_M 0x00800000 10492 #define HTT_ML_PEER_DETAILS_IS_EMLSR_ACTIVE_S 23 10493 /* for backwards compatibility, retain the old EMLSR name of the bitfield */ 10494 #define HTT_ML_PEER_DETAILS_EMLSR_M HTT_ML_PEER_DETAILS_IS_EMLSR_ACTIVE_M 10495 #define HTT_ML_PEER_DETAILS_EMLSR_S HTT_ML_PEER_DETAILS_IS_EMLSR_ACTIVE_S 10496 #define HTT_ML_PEER_DETAILS_IS_STA_KO_M 0x01000000 10497 #define HTT_ML_PEER_DETAILS_IS_STA_KO_S 24 10498 #define HTT_ML_PEER_DETAILS_NUM_LOCAL_LINKS_M 0x06000000 10499 #define HTT_ML_PEER_DETAILS_NUM_LOCAL_LINKS_S 25 10500 #define HTT_ML_PEER_DETAILS_ALLOCATED_M 0x08000000 10501 #define HTT_ML_PEER_DETAILS_ALLOCATED_S 27 10502 #define HTT_ML_PEER_DETAILS_EMLSR_SUPPORT_M 0x10000000 10503 #define HTT_ML_PEER_DETAILS_EMLSR_SUPPORT_S 28 10504 10505 #define HTT_ML_PEER_DETAILS_PARTICIPATING_CHIPS_BITMAP_M 0x000000ff 10506 #define HTT_ML_PEER_DETAILS_PARTICIPATING_CHIPS_BITMAP_S 0 10507 10508 #define HTT_ML_PEER_DETAILS_NUM_LINKS_GET(_var) \ 10509 (((_var) & HTT_ML_PEER_DETAILS_NUM_LINKS_M) >> \ 10510 HTT_ML_PEER_DETAILS_NUM_LINKS_S) 10511 /* provide properly-named macro */ 10512 #define HTT_STATS_ML_PEER_DETAILS_NUM_LINKS_GET(_var) \ 10513 HTT_ML_PEER_DETAILS_NUM_LINKS_GET(_var) 10514 10515 #define HTT_ML_PEER_DETAILS_NUM_LINKS_SET(_var, _val) \ 10516 do { \ 10517 HTT_CHECK_SET_VAL(HTT_ML_PEER_DETAILS_NUM_LINKS, _val); \ 10518 ((_var) &= ~(HTT_ML_PEER_DETAILS_NUM_LINKS_M)); \ 10519 ((_var) |= ((_val) << HTT_ML_PEER_DETAILS_NUM_LINKS_S)); \ 10520 } while (0) 10521 10522 #define HTT_ML_PEER_DETAILS_ML_PEER_ID_GET(_var) \ 10523 (((_var) & HTT_ML_PEER_DETAILS_ML_PEER_ID_M) >> \ 10524 HTT_ML_PEER_DETAILS_ML_PEER_ID_S) 10525 /* provide properly-named macro */ 10526 #define HTT_STATS_ML_PEER_DETAILS_ML_PEER_ID_GET(_var) \ 10527 HTT_ML_PEER_DETAILS_ML_PEER_ID_GET(_var) 10528 10529 #define HTT_ML_PEER_DETAILS_ML_PEER_ID_SET(_var, _val) \ 10530 do { \ 10531 HTT_CHECK_SET_VAL(HTT_ML_PEER_DETAILS_ML_PEER_ID, _val); \ 10532 ((_var) &= ~(HTT_ML_PEER_DETAILS_ML_PEER_ID_M)); \ 10533 ((_var) |= ((_val) << HTT_ML_PEER_DETAILS_ML_PEER_ID_S)); \ 10534 } while (0) 10535 10536 #define HTT_ML_PEER_DETAILS_PRIMARY_LINK_IDX_GET(_var) \ 10537 (((_var) & HTT_ML_PEER_DETAILS_PRIMARY_LINK_IDX_M) >> \ 10538 HTT_ML_PEER_DETAILS_PRIMARY_LINK_IDX_S) 10539 /* provide properly-named macro */ 10540 #define HTT_STATS_ML_PEER_DETAILS_PRIMARY_LINK_IDX_GET(_var) \ 10541 HTT_ML_PEER_DETAILS_PRIMARY_LINK_IDX_GET(_var) 10542 10543 #define HTT_ML_PEER_DETAILS_PRIMARY_LINK_IDX_SET(_var, _val) \ 10544 do { \ 10545 HTT_CHECK_SET_VAL(HTT_ML_PEER_DETAILS_PRIMARY_LINK_IDX, _val); \ 10546 ((_var) &= ~(HTT_ML_PEER_DETAILS_PRIMARY_LINK_IDX_M)); \ 10547 ((_var) |= ((_val) << HTT_ML_PEER_DETAILS_PRIMARY_LINK_IDX_S)); \ 10548 } while (0) 10549 10550 #define HTT_ML_PEER_DETAILS_PRIMARY_CHIP_ID_GET(_var) \ 10551 (((_var) & HTT_ML_PEER_DETAILS_PRIMARY_CHIP_ID_M) >> \ 10552 HTT_ML_PEER_DETAILS_PRIMARY_CHIP_ID_S) 10553 /* provide properly-named macro */ 10554 #define HTT_STATS_ML_PEER_DETAILS_PRIMARY_CHIP_ID_GET(_var) \ 10555 HTT_ML_PEER_DETAILS_PRIMARY_CHIP_ID_GET(_var) 10556 10557 #define HTT_ML_PEER_DETAILS_PRIMARY_CHIP_ID_SET(_var, _val) \ 10558 do { \ 10559 HTT_CHECK_SET_VAL(HTT_ML_PEER_DETAILS_PRIMARY_CHIP_ID, _val); \ 10560 ((_var) &= ~(HTT_ML_PEER_DETAILS_PRIMARY_CHIP_ID_M)); \ 10561 ((_var) |= ((_val) << HTT_ML_PEER_DETAILS_PRIMARY_CHIP_ID_S)); \ 10562 } while (0) 10563 10564 #define HTT_ML_PEER_DETAILS_LINK_INIT_COUNT_GET(_var) \ 10565 (((_var) & HTT_ML_PEER_DETAILS_LINK_INIT_COUNT_M) >> \ 10566 HTT_ML_PEER_DETAILS_LINK_INIT_COUNT_S) 10567 /* provide properly-named macro */ 10568 #define HTT_STATS_ML_PEER_DETAILS_LINK_INIT_COUNT_GET(_var) \ 10569 HTT_ML_PEER_DETAILS_LINK_INIT_COUNT_GET(_var) 10570 10571 #define HTT_ML_PEER_DETAILS_LINK_INIT_COUNT_SET(_var, _val) \ 10572 do { \ 10573 HTT_CHECK_SET_VAL(HTT_ML_PEER_DETAILS_LINK_INIT_COUNT, _val); \ 10574 ((_var) &= ~(HTT_ML_PEER_DETAILS_LINK_INIT_COUNT_M)); \ 10575 ((_var) |= ((_val) << HTT_ML_PEER_DETAILS_LINK_INIT_COUNT_S)); \ 10576 } while (0) 10577 10578 #define HTT_ML_PEER_DETAILS_NON_STR_GET(_var) \ 10579 (((_var) & HTT_ML_PEER_DETAILS_NON_STR_M) >> \ 10580 HTT_ML_PEER_DETAILS_NON_STR_S) 10581 /* provide properly-named macro */ 10582 #define HTT_STATS_ML_PEER_DETAILS_NON_STR_GET(_var) \ 10583 HTT_ML_PEER_DETAILS_NON_STR_GET(_var) 10584 10585 #define HTT_ML_PEER_DETAILS_NON_STR_SET(_var, _val) \ 10586 do { \ 10587 HTT_CHECK_SET_VAL(HTT_ML_PEER_DETAILS_NON_STR, _val); \ 10588 ((_var) &= ~(HTT_ML_PEER_DETAILS_NON_STR_M)); \ 10589 ((_var) |= ((_val) << HTT_ML_PEER_DETAILS_NON_STR_S)); \ 10590 } while (0) 10591 10592 #define HTT_ML_PEER_DETAILS_IS_EMLSR_ACTIVE_GET(_var) \ 10593 (((_var) & HTT_ML_PEER_DETAILS_IS_EMLSR_ACTIVE_M) >> \ 10594 HTT_ML_PEER_DETAILS_IS_EMLSR_ACTIVE_S) 10595 /* provide properly-named macro */ 10596 #define HTT_STATS_ML_PEER_DETAILS_IS_EMLSR_ACTIVE_GET(_var) \ 10597 HTT_ML_PEER_DETAILS_IS_EMLSR_ACTIVE_GET(_var) 10598 10599 #define HTT_ML_PEER_DETAILS_IS_EMLSR_ACTIVE_SET(_var, _val) \ 10600 do { \ 10601 HTT_CHECK_SET_VAL(HTT_ML_PEER_DETAILS_IS_EMLSR_ACTIVE, _val); \ 10602 ((_var) &= ~(HTT_ML_PEER_DETAILS_IS_EMLSR_ACTIVE_M)); \ 10603 ((_var) |= ((_val) << HTT_ML_PEER_DETAILS_IS_EMLSR_ACTIVE_S)); \ 10604 } while (0) 10605 10606 /* start deprecated: 10607 * For backwards compatibility, retain a macro definition that uses 10608 * the old EMLSR name of the bitfield 10609 */ 10610 #define HTT_ML_PEER_DETAILS_EMLSR_GET(_var) \ 10611 (((_var) & HTT_ML_PEER_DETAILS_EMLSR_M) >> \ 10612 HTT_ML_PEER_DETAILS_EMLSR_S) 10613 #define HTT_ML_PEER_DETAILS_EMLSR_SET(_var, _val) \ 10614 do { \ 10615 HTT_CHECK_SET_VAL(HTT_ML_PEER_DETAILS_EMLSR, _val); \ 10616 ((_var) &= ~(HTT_ML_PEER_DETAILS_EMLSR_M)); \ 10617 ((_var) |= ((_val) << HTT_ML_PEER_DETAILS_EMLSR_S)); \ 10618 } while (0) 10619 /* end deprecated */ 10620 10621 #define HTT_ML_PEER_DETAILS_IS_STA_KO_GET(_var) \ 10622 (((_var) & HTT_ML_PEER_DETAILS_IS_STA_KO_M) >> \ 10623 HTT_ML_PEER_DETAILS_IS_STA_KO_S) 10624 /* provide properly-named macro */ 10625 #define HTT_STATS_ML_PEER_DETAILS_IS_STA_KO_GET(_var) \ 10626 HTT_ML_PEER_DETAILS_IS_STA_KO_GET(_var) 10627 10628 #define HTT_ML_PEER_DETAILS_IS_STA_KO_SET(_var, _val) \ 10629 do { \ 10630 HTT_CHECK_SET_VAL(HTT_ML_PEER_DETAILS_IS_STA_KO, _val); \ 10631 ((_var) &= ~(HTT_ML_PEER_DETAILS_IS_STA_KO_M)); \ 10632 ((_var) |= ((_val) << HTT_ML_PEER_DETAILS_IS_STA_KO_S)); \ 10633 } while (0) 10634 10635 #define HTT_ML_PEER_DETAILS_NUM_LOCAL_LINKS_GET(_var) \ 10636 (((_var) & HTT_ML_PEER_DETAILS_NUM_LOCAL_LINKS_M) >> \ 10637 HTT_ML_PEER_DETAILS_NUM_LOCAL_LINKS_S) 10638 /* provide properly-named macro */ 10639 #define HTT_STATS_ML_PEER_DETAILS_NUM_LOCAL_LINKS_GET(_var) \ 10640 HTT_ML_PEER_DETAILS_NUM_LOCAL_LINKS_GET(_var) 10641 10642 #define HTT_ML_PEER_DETAILS_NUM_LOCAL_LINKS_SET(_var, _val) \ 10643 do { \ 10644 HTT_CHECK_SET_VAL(HTT_ML_PEER_DETAILS_NUM_LOCAL_LINKS, _val); \ 10645 ((_var) &= ~(HTT_ML_PEER_DETAILS_NUM_LOCAL_LINKS_M)); \ 10646 ((_var) |= ((_val) << HTT_ML_PEER_DETAILS_NUM_LOCAL_LINKS_S)); \ 10647 } while (0) 10648 10649 #define HTT_ML_PEER_DETAILS_ALLOCATED_GET(_var) \ 10650 (((_var) & HTT_ML_PEER_DETAILS_ALLOCATED_M) >> \ 10651 HTT_ML_PEER_DETAILS_ALLOCATED_S) 10652 /* provide properly-named macro */ 10653 #define HTT_STATS_ML_PEER_DETAILS_ALLOCATED_GET(_var) \ 10654 HTT_ML_PEER_DETAILS_ALLOCATED_GET(_var) 10655 10656 #define HTT_ML_PEER_DETAILS_ALLOCATED_SET(_var, _val) \ 10657 do { \ 10658 HTT_CHECK_SET_VAL(HTT_ML_PEER_DETAILS_ALLOCATED, _val); \ 10659 ((_var) &= ~(HTT_ML_PEER_DETAILS_ALLOCATED_M)); \ 10660 ((_var) |= ((_val) << HTT_ML_PEER_DETAILS_ALLOCATED_S)); \ 10661 } while (0) 10662 10663 #define HTT_ML_PEER_DETAILS_EMLSR_SUPPORT_GET(_var) \ 10664 (((_var) & HTT_ML_PEER_DETAILS_EMLSR_SUPPORT_M) >> \ 10665 HTT_ML_PEER_DETAILS_EMLSR_SUPPORT_S) 10666 /* provide properly-named macro */ 10667 #define HTT_STATS_ML_PEER_DETAILS_EMLSR_SUPPORT_GET(_var) \ 10668 HTT_ML_PEER_DETAILS_EMLSR_SUPPORT_GET(_var) 10669 10670 #define HTT_ML_PEER_DETAILS_EMLSR_SUPPORT_SET(_var, _val) \ 10671 do { \ 10672 HTT_CHECK_SET_VAL(HTT_ML_PEER_DETAILS_EMLSR_SUPPORT, _val); \ 10673 ((_var) &= ~(HTT_ML_PEER_DETAILS_EMLSR_SUPPORT_M)); \ 10674 ((_var) |= ((_val) << HTT_ML_PEER_DETAILS_EMLSR_SUPPORT_S)); \ 10675 } while (0) 10676 10677 10678 #define HTT_ML_PEER_DETAILS_PARTICIPATING_CHIPS_BITMAP_GET(_var) \ 10679 (((_var) & HTT_ML_PEER_DETAILS_PARTICIPATING_CHIPS_BITMAP_M) >> \ 10680 HTT_ML_PEER_DETAILS_PARTICIPATING_CHIPS_BITMAP_S) 10681 /* provide properly-named macro */ 10682 #define HTT_STATS_ML_PEER_DETAILS_PARTICIPATING_CHIPS_BITMAP_GET(_var) \ 10683 HTT_ML_PEER_DETAILS_PARTICIPATING_CHIPS_BITMAP_GET(_var) 10684 10685 #define HTT_ML_PEER_DETAILS_PARTICIPATING_CHIPS_BITMAP_SET(_var, _val) \ 10686 do { \ 10687 HTT_CHECK_SET_VAL(HTT_ML_PEER_DETAILS_PARTICIPATING_CHIPS_BITMAP, _val); \ 10688 ((_var) &= ~(HTT_ML_PEER_DETAILS_PARTICIPATING_CHIPS_BITMAP_M)); \ 10689 ((_var) |= ((_val) << HTT_ML_PEER_DETAILS_PARTICIPATING_CHIPS_BITMAP_S)); \ 10690 } while (0) 10691 10692 typedef struct { 10693 htt_tlv_hdr_t tlv_hdr; 10694 htt_mac_addr remote_mld_mac_addr; 10695 union { 10696 struct { 10697 A_UINT32 num_links : 2, 10698 ml_peer_id : 12, 10699 primary_link_idx : 3, 10700 primary_chip_id : 2, 10701 link_init_count : 3, 10702 non_str : 1, 10703 is_emlsr_active : 1, 10704 is_sta_ko : 1, 10705 num_local_links : 2, 10706 allocated : 1, 10707 emlsr_support : 1, 10708 reserved : 3; 10709 }; 10710 struct { 10711 /* 10712 * For backwards compatibility, use a dummy union element to 10713 * retain the old "emlsr" name for the "is_emlsr_active" bitfield. 10714 */ 10715 A_UINT32 dummy1 : 23, 10716 emlsr : 1, 10717 dummy2 : 8; 10718 }; 10719 A_UINT32 msg_dword_1; 10720 }; 10721 10722 union { 10723 struct { 10724 A_UINT32 participating_chips_bitmap : 8, 10725 reserved1 : 24; 10726 }; 10727 A_UINT32 msg_dword_2; 10728 }; 10729 /* 10730 * ml_peer_flags is an opaque field that cannot be interpreted by 10731 * the host; it is only for off-line debug. 10732 */ 10733 A_UINT32 ml_peer_flags; 10734 } htt_stats_ml_peer_details_tlv; 10735 /* preserve old name alias for new name consistent with the tag name */ 10736 typedef htt_stats_ml_peer_details_tlv htt_ml_peer_details_tlv; 10737 10738 /* STATS_TYPE : HTT_DBG_EXT_STATS_ML_PEERS_INFO 10739 * TLV_TAGS: 10740 * - HTT_STATS_ML_PEER_DETAILS_TAG 10741 * - HTT_STATS_ML_LINK_INFO_DETAILS_TAG 10742 * - HTT_STATS_ML_PEER_EXT_DETAILS_TAG (multiple) 10743 */ 10744 /* NOTE: 10745 * This structure is for documentation, and cannot be safely used directly. 10746 * Instead, use the constituent TLV structures to fill/parse. 10747 */ 10748 #ifdef ATH_TARGET 10749 typedef struct _htt_ml_peer_stats { 10750 htt_stats_ml_peer_details_tlv ml_peer_details; 10751 htt_stats_ml_peer_ext_details_tlv ml_peer_ext_details; 10752 htt_stats_ml_link_info_details_tlv ml_link_info[1]; 10753 } htt_ml_peer_stats_t; 10754 #endif /* ATH_TARGET */ 10755 10756 /* 10757 * ODD Mandatory Stats are grouped together from all the existing different 10758 * stats, to form a set of stats that will be used by the ODD application to 10759 * post the stats to the cloud instead of polling for the individual stats. 10760 * This is done to avoid non-mandatory stats to be polled as the data will not 10761 * be required in the recipes derivation. 10762 * Rather than the host simply printing the ODD stats, the ODD application 10763 * will take the buffer and map it to the odd_mandatory_stats data structure. 10764 */ 10765 typedef struct { 10766 htt_tlv_hdr_t tlv_hdr; 10767 A_UINT32 hw_queued; 10768 A_UINT32 hw_reaped; 10769 A_UINT32 hw_paused; 10770 A_UINT32 hw_filt; 10771 A_UINT32 seq_posted; 10772 A_UINT32 seq_completed; 10773 A_UINT32 underrun; 10774 A_UINT32 hw_flush; 10775 A_UINT32 next_seq_posted_dsr; 10776 A_UINT32 seq_posted_isr; 10777 A_UINT32 mpdu_cnt_fcs_ok; 10778 A_UINT32 mpdu_cnt_fcs_err; 10779 A_UINT32 msdu_count_tqm; 10780 A_UINT32 mpdu_count_tqm; 10781 A_UINT32 mpdus_ack_failed; 10782 A_UINT32 num_data_ppdus_tried_ota; 10783 A_UINT32 ppdu_ok; 10784 A_UINT32 num_total_ppdus_tried_ota; 10785 A_UINT32 thermal_suspend_cnt; 10786 A_UINT32 dfs_suspend_cnt; 10787 A_UINT32 tx_abort_suspend_cnt; 10788 A_UINT32 suspended_txq_mask; 10789 A_UINT32 last_suspend_reason; 10790 A_UINT32 seq_failed_queueing; 10791 A_UINT32 seq_restarted; 10792 A_UINT32 seq_txop_repost_stop; 10793 A_UINT32 next_seq_cancel; 10794 A_UINT32 seq_min_msdu_repost_stop; 10795 A_UINT32 total_phy_err_cnt; 10796 A_UINT32 ppdu_recvd; 10797 A_UINT32 tcp_msdu_cnt; 10798 A_UINT32 tcp_ack_msdu_cnt; 10799 A_UINT32 udp_msdu_cnt; 10800 A_UINT32 fw_tx_mgmt_subtype[HTT_STATS_SUBTYPE_MAX]; 10801 A_UINT32 fw_rx_mgmt_subtype[HTT_STATS_SUBTYPE_MAX]; 10802 A_UINT32 fw_ring_mpdu_err[HTT_RX_STATS_RXDMA_MAX_ERR]; 10803 A_UINT32 urrn_stats[HTT_TX_PDEV_MAX_URRN_STATS]; 10804 A_UINT32 sifs_status[HTT_TX_PDEV_MAX_SIFS_BURST_STATS]; 10805 A_UINT32 sifs_hist_status[HTT_TX_PDEV_SIFS_BURST_HIST_STATS]; 10806 A_UINT32 rx_suspend_cnt; 10807 A_UINT32 rx_suspend_fail_cnt; 10808 A_UINT32 rx_resume_cnt; 10809 A_UINT32 rx_resume_fail_cnt; 10810 A_UINT32 hwq_beacon_cmd_result[HTT_TX_HWQ_MAX_CMD_RESULT_STATS]; 10811 A_UINT32 hwq_voice_cmd_result[HTT_TX_HWQ_MAX_CMD_RESULT_STATS]; 10812 A_UINT32 hwq_video_cmd_result[HTT_TX_HWQ_MAX_CMD_RESULT_STATS]; 10813 A_UINT32 hwq_best_effort_cmd_result[HTT_TX_HWQ_MAX_CMD_RESULT_STATS]; 10814 A_UINT32 hwq_beacon_mpdu_tried_cnt; 10815 A_UINT32 hwq_voice_mpdu_tried_cnt; 10816 A_UINT32 hwq_video_mpdu_tried_cnt; 10817 A_UINT32 hwq_best_effort_mpdu_tried_cnt; 10818 A_UINT32 hwq_beacon_mpdu_queued_cnt; 10819 A_UINT32 hwq_voice_mpdu_queued_cnt; 10820 A_UINT32 hwq_video_mpdu_queued_cnt; 10821 A_UINT32 hwq_best_effort_mpdu_queued_cnt; 10822 A_UINT32 hwq_beacon_mpdu_ack_fail_cnt; 10823 A_UINT32 hwq_voice_mpdu_ack_fail_cnt; 10824 A_UINT32 hwq_video_mpdu_ack_fail_cnt; 10825 A_UINT32 hwq_best_effort_mpdu_ack_fail_cnt; 10826 A_UINT32 pdev_resets; 10827 A_UINT32 phy_warm_reset; 10828 A_UINT32 hwsch_reset_count; 10829 A_UINT32 phy_warm_reset_ucode_trig; 10830 A_UINT32 mac_cold_reset; 10831 A_UINT32 mac_warm_reset; 10832 A_UINT32 mac_warm_reset_restore_cal; 10833 A_UINT32 phy_warm_reset_m3_ssr; 10834 A_UINT32 fw_rx_rings_reset; 10835 A_UINT32 tx_flush; 10836 A_UINT32 hwsch_dev_reset_war; 10837 A_UINT32 mac_cold_reset_restore_cal; 10838 A_UINT32 mac_only_reset; 10839 A_UINT32 mac_sfm_reset; 10840 A_UINT32 tx_ldpc; /* Number of tx PPDUs with LDPC coding */ 10841 A_UINT32 rx_ldpc; /* Number of rx PPDUs with LDPC coding */ 10842 A_UINT32 gen_mpdu_end_reason[HTT_TX_TQM_MAX_GEN_MPDU_END_REASON]; 10843 A_UINT32 list_mpdu_end_reason[HTT_TX_TQM_MAX_LIST_MPDU_END_REASON]; 10844 A_UINT32 tx_mcs[HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS + HTT_TX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS + HTT_TX_PDEV_STATS_NUM_EXTRA2_MCS_COUNTERS]; 10845 A_UINT32 tx_nss[HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS]; 10846 A_UINT32 tx_bw[HTT_TX_PDEV_STATS_NUM_BW_COUNTERS]; 10847 A_UINT32 half_tx_bw[HTT_TX_PDEV_STATS_NUM_BW_COUNTERS]; 10848 A_UINT32 quarter_tx_bw[HTT_TX_PDEV_STATS_NUM_BW_COUNTERS]; 10849 A_UINT32 tx_su_punctured_mode[HTT_TX_PDEV_STATS_NUM_PUNCTURED_MODE_COUNTERS]; 10850 A_UINT32 rx_mcs[HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS + HTT_RX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS + HTT_RX_PDEV_STATS_NUM_EXTRA2_MCS_COUNTERS]; 10851 A_UINT32 rx_nss[HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS]; 10852 A_UINT32 rx_bw[HTT_RX_PDEV_STATS_NUM_BW_COUNTERS]; 10853 A_UINT32 rx_stbc[HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS + HTT_RX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS + HTT_RX_PDEV_STATS_NUM_EXTRA2_MCS_COUNTERS]; 10854 A_UINT32 rts_cnt; 10855 A_UINT32 rts_success; 10856 } htt_stats_odd_pdev_mandatory_tlv; 10857 /* preserve old name alias for new name consistent with the tag name */ 10858 typedef htt_stats_odd_pdev_mandatory_tlv htt_odd_mandatory_pdev_stats_tlv; 10859 10860 typedef struct _htt_odd_mandatory_mumimo_pdev_stats_tlv { 10861 htt_tlv_hdr_t tlv_hdr; 10862 A_UINT32 ac_mu_mimo_tx_bw[HTT_TX_PDEV_STATS_NUM_BW_COUNTERS]; 10863 A_UINT32 ax_mu_mimo_tx_bw[HTT_TX_PDEV_STATS_NUM_BW_COUNTERS]; 10864 A_UINT32 ac_mu_mimo_tx_nss[HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS]; 10865 A_UINT32 ax_mu_mimo_tx_nss[HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS]; 10866 A_UINT32 ac_mu_mimo_tx_mcs[HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS]; 10867 A_UINT32 ax_mu_mimo_tx_mcs[HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS]; 10868 A_UINT32 ul_mumimo_rx_mcs[HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS]; 10869 A_UINT32 ul_mumimo_rx_nss[HTT_RX_PDEV_STATS_ULMUMIMO_NUM_SPATIAL_STREAMS]; 10870 A_UINT32 ul_mumimo_rx_bw[HTT_RX_PDEV_STATS_NUM_BW_COUNTERS]; 10871 A_UINT32 rx_ulmumimo_mpdu_fail[HTT_RX_PDEV_MAX_OFDMA_NUM_USER]; 10872 A_UINT32 rx_ulmumimo_mpdu_ok[HTT_RX_PDEV_MAX_OFDMA_NUM_USER]; 10873 A_UINT32 rx_ulmumimo_data_ppdu[HTT_RX_PDEV_MAX_OFDMA_NUM_USER]; 10874 } htt_dbg_odd_mandatory_mumimo_tlv; 10875 /* preserve old name alias for new name consistent with the tag name */ 10876 typedef htt_dbg_odd_mandatory_mumimo_tlv 10877 htt_odd_mandatory_mumimo_pdev_stats_tlv; 10878 10879 typedef struct _htt_odd_mandatory_muofdma_pdev_stats_tlv { 10880 htt_tlv_hdr_t tlv_hdr; 10881 A_UINT32 mu_ofdma_seq_posted; 10882 A_UINT32 ul_mu_ofdma_seq_posted; 10883 A_UINT32 ofdma_tx_mcs[HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS + HTT_TX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS + HTT_TX_PDEV_STATS_NUM_EXTRA2_MCS_COUNTERS]; 10884 A_UINT32 ofdma_tx_nss[HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS]; 10885 A_UINT32 ofdma_tx_bw[HTT_TX_PDEV_STATS_NUM_BW_COUNTERS]; 10886 A_UINT32 ofdma_tx_ldpc; 10887 A_UINT32 ul_ofdma_rx_ldpc; 10888 A_UINT32 ul_ofdma_rx_mcs[HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS + HTT_RX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS + HTT_RX_PDEV_STATS_NUM_EXTRA2_MCS_COUNTERS]; 10889 A_UINT32 ul_ofdma_rx_nss[HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS]; 10890 A_UINT32 ul_ofdma_rx_bw[HTT_TX_PDEV_STATS_NUM_BW_COUNTERS]; 10891 A_UINT32 rx_ulofdma_data_ppdu[HTT_RX_PDEV_MAX_OFDMA_NUM_USER]; 10892 A_UINT32 rx_ulofdma_mpdu_ok[HTT_RX_PDEV_MAX_OFDMA_NUM_USER]; 10893 A_UINT32 rx_ulofdma_mpdu_fail[HTT_RX_PDEV_MAX_OFDMA_NUM_USER]; 10894 A_UINT32 ax_mu_brp_sch_status[HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 10895 A_UINT32 be_mu_brp_sch_status[HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 10896 A_UINT32 ofdma_tx_ru_size[HTT_TX_PDEV_STATS_NUM_AX_RU_SIZE_COUNTERS]; 10897 A_UINT32 ofdma_ba_ru_size[HTT_TX_PDEV_STATS_NUM_AX_RU_SIZE_COUNTERS]; 10898 } htt_dbg_odd_mandatory_muofdma_tlv; 10899 /* preserve old name alias for new name consistent with the tag name */ 10900 typedef htt_dbg_odd_mandatory_muofdma_tlv 10901 htt_odd_mandatory_muofdma_pdev_stats_tlv; 10902 10903 10904 #define HTT_PDEV_SCHED_ALGO_OFDMA_STATS_MAC_ID_M 0x000000ff 10905 #define HTT_PDEV_SCHED_ALGO_OFDMA_STATS_MAC_ID_S 0 10906 10907 #define HTT_PDEV_SCHED_ALGO_OFDMA_STATS_MAC_ID_GET(_var) \ 10908 (((_var) & HTT_PDEV_SCHED_ALGO_OFDMA_STATS_MAC_ID_M) >> \ 10909 HTT_PDEV_SCHED_ALGO_OFDMA_STATS_MAC_ID_S) 10910 10911 #define HTT_PDEV_SCHED_ALGO_OFDMA_STATS_MAC_ID_SET(_var, _val) \ 10912 do { \ 10913 HTT_CHECK_SET_VAL(HTT_PDEV_SCHED_ALGO_OFDMA_STATS_MAC_ID, _val); \ 10914 ((_var) |= ((_val) << HTT_PDEV_SCHED_ALGO_OFDMA_STATS_MAC_ID_S)); \ 10915 } while (0) 10916 10917 typedef enum { 10918 HTT_STATS_SCHED_OFDMA_TXBF = 0, /* 0 */ 10919 HTT_STATS_SCHED_OFDMA_TXBF_IS_SANITY_FAILED, /* 1 */ 10920 HTT_STATS_SCHED_OFDMA_TXBF_IS_EBF_ALLOWED_FAILIED, /* 2 */ 10921 HTT_STATS_SCHED_OFDMA_TXBF_RU_ALLOC_BW_DROP_COUNT, /* 3 */ 10922 HTT_STATS_SCHED_OFDMA_TXBF_INVALID_CV_QUERY_COUNT, /* 4 */ 10923 HTT_STATS_SCHED_OFDMA_TXBF_AVG_TXTIME_LESS_THAN_TXBF_SND_THERHOLD, /* 5 */ 10924 HTT_STATS_SCHED_OFDMA_TXBF_IS_CANDIDATE_KICKED_OUT, /* 6 */ 10925 HTT_STATS_SCHED_OFDMA_TXBF_CV_IMAGE_BUF_INVALID, /* 7 */ 10926 HTT_STATS_SCHED_OFDMA_TXBF_INELIGIBILITY_MAX, 10927 } htt_stats_sched_ofdma_txbf_ineligibility_t; 10928 10929 #define HTT_MAX_NUM_CHAN_ACC_LAT_INTR 9 10930 10931 typedef struct { 10932 htt_tlv_hdr_t tlv_hdr; 10933 /** 10934 * BIT [ 7 : 0] :- mac_id 10935 * BIT [31 : 8] :- reserved 10936 */ 10937 union { 10938 struct { 10939 A_UINT32 mac_id: 8, 10940 reserved: 24; 10941 }; 10942 A_UINT32 mac_id__word; 10943 }; 10944 10945 /** Num of instances where rate based DL OFDMA status = ENABLED */ 10946 A_UINT32 rate_based_dlofdma_enabled_count[HTT_NUM_AC_WMM]; 10947 /** Num of instances where rate based DL OFDMA status = DISABLED */ 10948 A_UINT32 rate_based_dlofdma_disabled_count[HTT_NUM_AC_WMM]; 10949 /** Num of instances where rate based DL OFDMA status = PROBING */ 10950 A_UINT32 rate_based_dlofdma_probing_count[HTT_NUM_AC_WMM]; 10951 /** Num of instances where rate based DL OFDMA status = MONITORING */ 10952 A_UINT32 rate_based_dlofdma_monitoring_count[HTT_NUM_AC_WMM]; 10953 /** Num of instances where avg. channel access latency based DL OFDMA status = ENABLED */ 10954 A_UINT32 chan_acc_lat_based_dlofdma_enabled_count[HTT_NUM_AC_WMM]; 10955 /** Num of instances where avg. channel access latency based DL OFDMA status = DISABLED */ 10956 A_UINT32 chan_acc_lat_based_dlofdma_disabled_count[HTT_NUM_AC_WMM]; 10957 /** Num of instances where avg. channel access latency based DL OFDMA status = MONITORING */ 10958 A_UINT32 chan_acc_lat_based_dlofdma_monitoring_count[HTT_NUM_AC_WMM]; 10959 /** Num of instances where dl ofdma is disabled due to ru allocation failure */ 10960 A_UINT32 downgrade_to_dl_su_ru_alloc_fail[HTT_NUM_AC_WMM]; 10961 /** Num of instances where dl ofdma is disabled because we have only one user in candidate list */ 10962 A_UINT32 candidate_list_single_user_disable_ofdma[HTT_NUM_AC_WMM]; 10963 /** Num of instances where ul is chosen over dl based on qos weight not specific to OFDMA */ 10964 A_UINT32 dl_cand_list_dropped_high_ul_qos_weight[HTT_NUM_AC_WMM]; 10965 /** Num of instances where dl ofdma is disabled due to pipelining */ 10966 A_UINT32 ax_dlofdma_disabled_due_to_pipelining[HTT_NUM_AC_WMM]; 10967 /** Num of instances where dl ofdma is disabled as the tid is su only eligible */ 10968 A_UINT32 dlofdma_disabled_su_only_eligible[HTT_NUM_AC_WMM]; 10969 /** Num of instances where dl ofdma is disabled because there are no mpdus tried consecutively */ 10970 A_UINT32 dlofdma_disabled_consec_no_mpdus_tried[HTT_NUM_AC_WMM]; 10971 /** Num of instances where dl ofdma is disabled because there are consecutive mpdu failure */ 10972 A_UINT32 dlofdma_disabled_consec_no_mpdus_success[HTT_NUM_AC_WMM]; 10973 A_UINT32 txbf_ofdma_ineligibility_stat[HTT_STATS_SCHED_OFDMA_TXBF_INELIGIBILITY_MAX]; 10974 /** Average channel access latency histogram stats 10975 * 10976 * avg_chan_acc_lat_hist[0]: channel access latency is < 100 us 10977 * avg_chan_acc_lat_hist[1]: 100 us <= channel access latency < 200 us 10978 * avg_chan_acc_lat_hist[2]: 200 us <= channel access latency < 300 us 10979 * avg_chan_acc_lat_hist[3]: 300 us <= channel access latency < 400 us 10980 * avg_chan_acc_lat_hist[4]: 400 us <= channel access latency < 500 us 10981 * avg_chan_acc_lat_hist[5]: 500 us <= channel access latency < 1000 us 10982 * avg_chan_acc_lat_hist[6]: 1000 us <= channel access latency < 1500 us 10983 * avg_chan_acc_lat_hist[7]: 1500 us <= channel access latency < 2000 us 10984 * avg_chan_acc_lat_hist[8]: channel access latency is >= 2000 us 10985 */ 10986 A_UINT32 avg_chan_acc_lat_hist[HTT_MAX_NUM_CHAN_ACC_LAT_INTR]; 10987 } htt_stats_pdev_sched_algo_ofdma_stats_tlv; 10988 /* preserve old name alias for new name consistent with the tag name */ 10989 typedef htt_stats_pdev_sched_algo_ofdma_stats_tlv 10990 htt_pdev_sched_algo_ofdma_stats_tlv; 10991 10992 #define HTT_STATS_PDEV_SCHED_ALGO_OFDMA_STATS_MAC_ID_GET(word) ((word >> 0) & 0xff) 10993 10994 typedef struct { 10995 htt_tlv_hdr_t tlv_hdr; 10996 /** mac_id__word: 10997 * BIT [ 7 : 0] :- mac_id 10998 * Use the HTT_STATS_CMN_MAC_ID_GET,_SET macros to 10999 * read/write this bitfield. 11000 * BIT [31 : 8] :- reserved 11001 */ 11002 A_UINT32 mac_id__word; 11003 A_UINT32 basic_trigger_across_bss; 11004 A_UINT32 basic_trigger_within_bss; 11005 A_UINT32 bsr_trigger_across_bss; 11006 A_UINT32 bsr_trigger_within_bss; 11007 A_UINT32 mu_rts_across_bss; 11008 A_UINT32 mu_rts_within_bss; 11009 A_UINT32 ul_mumimo_trigger_across_bss; 11010 A_UINT32 ul_mumimo_trigger_within_bss; 11011 } htt_stats_pdev_mbssid_ctrl_frame_stats_tlv; 11012 /* preserve old name alias for new name consistent with the tag name */ 11013 typedef htt_stats_pdev_mbssid_ctrl_frame_stats_tlv 11014 htt_pdev_mbssid_ctrl_frame_stats_tlv; 11015 11016 typedef struct { 11017 htt_tlv_hdr_t tlv_hdr; 11018 /** 11019 * BIT [ 7 : 0] :- mac_id 11020 * Use the HTT_STATS_TDMA_MAC_ID_GET macro to extract 11021 * this bitfield. 11022 * BIT [31 : 8] :- reserved 11023 */ 11024 union { 11025 struct { 11026 A_UINT32 mac_id: 8, 11027 reserved: 24; 11028 }; 11029 A_UINT32 mac_id__word; 11030 }; 11031 11032 /** Num of Active TDMA schedules */ 11033 A_UINT32 num_tdma_active_schedules; 11034 /** Num of Reserved TDMA schedules */ 11035 A_UINT32 num_tdma_reserved_schedules; 11036 /** Num of Restricted TDMA schedules */ 11037 A_UINT32 num_tdma_restricted_schedules; 11038 /** Num of Unconfigured TDMA schedules */ 11039 A_UINT32 num_tdma_unconfigured_schedules; 11040 /** Num of TDMA slot switches */ 11041 A_UINT32 num_tdma_slot_switches; 11042 /** Num of TDMA EDCA switches */ 11043 A_UINT32 num_tdma_edca_switches; 11044 } htt_stats_pdev_tdma_tlv; 11045 /* preserve old name alias for new name consistent with the tag name */ 11046 typedef htt_stats_pdev_tdma_tlv htt_pdev_tdma_stats_tlv; 11047 11048 #define HTT_STATS_TDMA_MAC_ID_M 0x000000ff 11049 #define HTT_STATS_TDMA_MAC_ID_S 0 11050 11051 #define HTT_STATS_TDMA_MAC_ID_GET(_var) \ 11052 (((_var) & HTT_STATS_TDMA_MAC_ID_M) >> \ 11053 HTT_STATS_TDMA_MAC_ID_S) 11054 /* provide properly-named macro */ 11055 #define HTT_STATS_PDEV_TDMA_MAC_ID_GET(_var) \ 11056 HTT_STATS_TDMA_MAC_ID_GET(_var) 11057 11058 /*======= Bandwidth Manager stats ====================*/ 11059 11060 #define HTT_BW_MGR_STATS_MAC_ID_M 0x000000ff 11061 #define HTT_BW_MGR_STATS_MAC_ID_S 0 11062 11063 #define HTT_BW_MGR_STATS_PRI20_IDX_M 0x0000ff00 11064 #define HTT_BW_MGR_STATS_PRI20_IDX_S 8 11065 11066 #define HTT_BW_MGR_STATS_PRI20_FREQ_M 0xffff0000 11067 #define HTT_BW_MGR_STATS_PRI20_FREQ_S 16 11068 11069 #define HTT_BW_MGR_STATS_CENTER_FREQ1_M 0x0000ffff 11070 #define HTT_BW_MGR_STATS_CENTER_FREQ1_S 0 11071 11072 #define HTT_BW_MGR_STATS_CENTER_FREQ2_M 0xffff0000 11073 #define HTT_BW_MGR_STATS_CENTER_FREQ2_S 16 11074 11075 #define HTT_BW_MGR_STATS_CHAN_PHY_MODE_M 0x000000ff 11076 #define HTT_BW_MGR_STATS_CHAN_PHY_MODE_S 0 11077 11078 #define HTT_BW_MGR_STATS_STATIC_PATTERN_M 0x00ffff00 11079 #define HTT_BW_MGR_STATS_STATIC_PATTERN_S 8 11080 11081 #define HTT_BW_MGR_STATS_MAC_ID_GET(_var) \ 11082 (((_var) & HTT_BW_MGR_STATS_MAC_ID_M) >> \ 11083 HTT_BW_MGR_STATS_MAC_ID_S) 11084 11085 #define HTT_BW_MGR_STATS_MAC_ID_SET(_var, _val) \ 11086 do { \ 11087 HTT_CHECK_SET_VAL(HTT_BW_MGR_STATS_MAC_ID, _val); \ 11088 ((_var) |= ((_val) << HTT_BW_MGR_STATS_MAC_ID_S)); \ 11089 } while (0) 11090 11091 11092 #define HTT_BW_MGR_STATS_PRI20_IDX_GET(_var) \ 11093 (((_var) & HTT_BW_MGR_STATS_PRI20_IDX_M) >> \ 11094 HTT_BW_MGR_STATS_PRI20_IDX_S) 11095 11096 #define HTT_BW_MGR_STATS_PRI20_IDX_SET(_var, _val) \ 11097 do { \ 11098 HTT_CHECK_SET_VAL(HTT_BW_MGR_STATS_PRI20_IDX, _val); \ 11099 ((_var) |= ((_val) << HTT_BW_MGR_STATS_PRI20_IDX_S)); \ 11100 } while (0) 11101 11102 11103 #define HTT_BW_MGR_STATS_PRI20_FREQ_GET(_var) \ 11104 (((_var) & HTT_BW_MGR_STATS_PRI20_FREQ_M) >> \ 11105 HTT_BW_MGR_STATS_PRI20_FREQ_S) 11106 11107 #define HTT_BW_MGR_STATS_PRI20_FREQ_SET(_var, _val) \ 11108 do { \ 11109 HTT_CHECK_SET_VAL(HTT_BW_MGR_STATS_PRI20_FREQ, _val); \ 11110 ((_var) |= ((_val) << HTT_BW_MGR_STATS_PRI20_FREQ_S)); \ 11111 } while (0) 11112 11113 11114 #define HTT_BW_MGR_STATS_CENTER_FREQ1_GET(_var) \ 11115 (((_var) & HTT_BW_MGR_STATS_CENTER_FREQ1_M) >> \ 11116 HTT_BW_MGR_STATS_CENTER_FREQ1_S) 11117 11118 #define HTT_BW_MGR_STATS_CENTER_FREQ1_SET(_var, _val) \ 11119 do { \ 11120 HTT_CHECK_SET_VAL(HTT_BW_MGR_STATS_CENTER_FREQ1, _val); \ 11121 ((_var) |= ((_val) << HTT_BW_MGR_STATS_CENTER_FREQ1_S)); \ 11122 } while (0) 11123 11124 11125 #define HTT_BW_MGR_STATS_CENTER_FREQ2_GET(_var) \ 11126 (((_var) & HTT_BW_MGR_STATS_CENTER_FREQ2_M) >> \ 11127 HTT_BW_MGR_STATS_CENTER_FREQ2_S) 11128 11129 #define HTT_BW_MGR_STATS_CENTER_FREQ2_SET(_var, _val) \ 11130 do { \ 11131 HTT_CHECK_SET_VAL(HTT_BW_MGR_STATS_CENTER_FREQ2, _val); \ 11132 ((_var) |= ((_val) << HTT_BW_MGR_STATS_CENTER_FREQ2_S)); \ 11133 } while (0) 11134 11135 11136 #define HTT_BW_MGR_STATS_CHAN_PHY_MODE_GET(_var) \ 11137 (((_var) & HTT_BW_MGR_STATS_CHAN_PHY_MODE_M) >> \ 11138 HTT_BW_MGR_STATS_CHAN_PHY_MODE_S) 11139 11140 #define HTT_BW_MGR_STATS_CHAN_PHY_MODE_SET(_var, _val) \ 11141 do { \ 11142 HTT_CHECK_SET_VAL(HTT_BW_MGR_STATS_CHAN_PHY_MODE, _val); \ 11143 ((_var) |= ((_val) << HTT_BW_MGR_STATS_CHAN_PHY_MODE_S)); \ 11144 } while (0) 11145 11146 11147 #define HTT_BW_MGR_STATS_STATIC_PATTERN_GET(_var) \ 11148 (((_var) & HTT_BW_MGR_STATS_STATIC_PATTERN_M) >> \ 11149 HTT_BW_MGR_STATS_STATIC_PATTERN_S) 11150 11151 #define HTT_BW_MGR_STATS_STATIC_PATTERN_SET(_var, _val) \ 11152 do { \ 11153 HTT_CHECK_SET_VAL(HTT_BW_MGR_STATS_STATIC_PATTERN, _val); \ 11154 ((_var) |= ((_val) << HTT_BW_MGR_STATS_STATIC_PATTERN_S)); \ 11155 } while (0) 11156 11157 11158 typedef struct { 11159 htt_tlv_hdr_t tlv_hdr; 11160 11161 /* BIT [ 7 : 0] :- mac_id 11162 * BIT [ 15 : 8] :- pri20_index 11163 * BIT [ 31 : 16] :- pri20_freq in Mhz 11164 */ 11165 A_UINT32 mac_id__pri20_idx__freq; 11166 11167 /* BIT [ 15 : 0] :- centre_freq1 11168 * BIT [ 31 : 16] :- centre_freq2 11169 */ 11170 A_UINT32 centre_freq1__freq2; 11171 11172 /* BIT [ 7 : 0] :- channel_phy_mode 11173 * BIT [ 23 : 8] :- static_pattern 11174 */ 11175 A_UINT32 phy_mode__static_pattern; 11176 } htt_stats_pdev_bw_mgr_stats_tlv; 11177 /* preserve old name alias for new name consistent with the tag name */ 11178 typedef htt_stats_pdev_bw_mgr_stats_tlv htt_pdev_bw_mgr_stats_tlv; 11179 11180 11181 /* STATS_TYPE : HTT_DBG_EXT_STATS_PDEV_BW_MGR 11182 * TLV_TAGS: 11183 * - HTT_STATS_PDEV_BW_MGR_STATS_TAG 11184 */ 11185 /* NOTE: 11186 * This structure is for documentation, and cannot be safely used directly. 11187 * Instead, use the constituent TLV structures to fill/parse. 11188 */ 11189 #ifdef ATH_TARGET 11190 typedef struct { 11191 htt_stats_pdev_bw_mgr_stats_tlv bw_mgr_tlv; 11192 } htt_pdev_bw_mgr_stats_t; 11193 #endif /* ATH_TARGET */ 11194 11195 11196 /*============= start MLO UMAC SSR stats ============= { */ 11197 11198 typedef enum { 11199 HTT_MLO_UMAC_SSR_DBG_POINT_INVALID = 0, 11200 HTT_MLO_UMAC_SSR_DBG_POINT_PRE_RESET_DISABLE_RXDMA_PREFETCH, 11201 HTT_MLO_UMAC_SSR_DBG_POINT_PRE_RESET_PMACS_HWMLOS, 11202 HTT_MLO_UMAC_SSR_DBG_POINT_PRE_RESET_GLOBAL_WSI, 11203 HTT_MLO_UMAC_SSR_DBG_POINT_PRE_RESET_PMACS_DMAC, 11204 HTT_MLO_UMAC_SSR_DBG_POINT_PRE_RESET_TCL, 11205 HTT_MLO_UMAC_SSR_DBG_POINT_PRE_RESET_TQM, 11206 HTT_MLO_UMAC_SSR_DBG_POINT_PRE_RESET_WBM, 11207 HTT_MLO_UMAC_SSR_DBG_POINT_PRE_RESET_REO, 11208 HTT_MLO_UMAC_SSR_DBG_POINT_PRE_RESET_HOST, 11209 HTT_MLO_UMAC_SSR_DBG_POINT_RESET_PREREQUISITES, 11210 HTT_MLO_UMAC_SSR_DBG_POINT_RESET_PRE_RING_RESET, 11211 HTT_MLO_UMAC_SSR_DBG_POINT_RESET_APPLY_SOFT_RESET, 11212 HTT_MLO_UMAC_SSR_DBG_POINT_RESET_POST_RING_RESET, 11213 HTT_MLO_UMAC_SSR_DBG_POINT_RESET_FW_TQM_CMDQS, 11214 HTT_MLO_UMAC_SSR_DBG_POINT_POST_RESET_HOST, 11215 HTT_MLO_UMAC_SSR_DBG_POINT_POST_RESET_UMAC_INTERRUPTS, 11216 HTT_MLO_UMAC_SSR_DBG_POINT_POST_RESET_WBM, 11217 HTT_MLO_UMAC_SSR_DBG_POINT_POST_RESET_REO, 11218 HTT_MLO_UMAC_SSR_DBG_POINT_POST_RESET_TQM, 11219 HTT_MLO_UMAC_SSR_DBG_POINT_POST_RESET_PMACS_DMAC, 11220 HTT_MLO_UMAC_SSR_DBG_POINT_POST_RESET_TQM_SYNC_CMD, 11221 HTT_MLO_UMAC_SSR_DBG_POINT_POST_RESET_GLOBAL_WSI, 11222 HTT_MLO_UMAC_SSR_DBG_POINT_POST_RESET_PMACS_HWMLOS, 11223 HTT_MLO_UMAC_SSR_DBG_POINT_POST_RESET_ENABLE_RXDMA_PREFETCH, 11224 HTT_MLO_UMAC_SSR_DBG_POINT_POST_RESET_TCL, 11225 HTT_MLO_UMAC_SSR_DBG_POINT_POST_RESET_HOST_ENQ, 11226 HTT_MLO_UMAC_SSR_DBG_POINT_POST_RESET_VERIFY_UMAC_RECOVERED, 11227 /* The below debug point values are reserved for future expansion. */ 11228 HTT_MLO_UMAC_SSR_DBG_POINT_RESERVED28, 11229 HTT_MLO_UMAC_SSR_DBG_POINT_RESERVED29, 11230 HTT_MLO_UMAC_SSR_DBG_POINT_RESERVED30, 11231 HTT_MLO_UMAC_SSR_DBG_POINT_RESERVED31, 11232 HTT_MLO_UMAC_SSR_DBG_POINT_RESERVED32, 11233 HTT_MLO_UMAC_SSR_DBG_POINT_RESERVED33, 11234 HTT_MLO_UMAC_SSR_DBG_POINT_RESERVED34, 11235 HTT_MLO_UMAC_SSR_DBG_POINT_RESERVED35, 11236 HTT_MLO_UMAC_SSR_DBG_POINT_RESERVED36, 11237 HTT_MLO_UMAC_SSR_DBG_POINT_RESERVED37, 11238 HTT_MLO_UMAC_SSR_DBG_POINT_RESERVED38, 11239 HTT_MLO_UMAC_SSR_DBG_POINT_RESERVED39, 11240 HTT_MLO_UMAC_SSR_DBG_POINT_RESERVED40, 11241 /* 11242 * Due to backwards compatibility requirements, no futher DBG_POINT values 11243 * can be added (but the above reserved values can be repurposed). 11244 */ 11245 HTT_MLO_UMAC_SSR_DBG_POINT_MAX, 11246 } HTT_MLO_UMAC_SSR_DBG_POINTS; 11247 11248 typedef enum { 11249 HTT_MLO_UMAC_RECOVERY_HANDSHAKE_INVALID = 0, 11250 HTT_MLO_UMAC_RECOVERY_HANDSHAKE_DO_PRE_RESET, 11251 HTT_MLO_UMAC_RECOVERY_HANDSHAKE_DO_POST_RESET_START, 11252 HTT_MLO_UMAC_RECOVERY_HANDSHAKE_DO_POST_RESET_COMPLETE, 11253 /* The below recovery handshake values are reserved for future expansion. */ 11254 HTT_MLO_UMAC_RECOVERY_HANDSHAKE_RESERVED4, 11255 HTT_MLO_UMAC_RECOVERY_HANDSHAKE_RESERVED5, 11256 HTT_MLO_UMAC_RECOVERY_HANDSHAKE_RESERVED6, 11257 HTT_MLO_UMAC_RECOVERY_HANDSHAKE_RESERVED7, 11258 HTT_MLO_UMAC_RECOVERY_HANDSHAKE_RESERVED8, 11259 /* 11260 * Due to backwards compatibility requirements, no futher 11261 * RECOVERY_HANDSHAKE values can be added (but the above 11262 * reserved values can be repurposed). 11263 */ 11264 HTT_MLO_UMAC_RECOVERY_HANDSHAKE_COUNT, 11265 } HTT_MLO_UMAC_RECOVERY_HANDSHAKES; 11266 11267 typedef struct { 11268 htt_tlv_hdr_t tlv_hdr; 11269 A_UINT32 start_ms; 11270 A_UINT32 end_ms; 11271 A_UINT32 delta_ms; 11272 A_UINT32 reserved; 11273 A_UINT32 footprint; /* holds a HTT_MLO_UMAC_SSR_DBG_POINTS value */ 11274 A_UINT32 tqm_hw_tstamp; 11275 } htt_stats_mlo_umac_ssr_dbg_tlv; 11276 /* preserve old name alias for new name consistent with the tag name */ 11277 typedef htt_stats_mlo_umac_ssr_dbg_tlv htt_mlo_umac_ssr_dbg_tlv; 11278 11279 typedef struct { 11280 A_UINT32 last_mlo_htt_handshake_delta_ms; 11281 A_UINT32 max_mlo_htt_handshake_delta_ms; 11282 union { 11283 A_UINT32 umac_recovery_done_mask; 11284 struct { 11285 A_UINT32 pre_reset_disable_rxdma_prefetch : 1, 11286 pre_reset_pmacs_hwmlos : 1, 11287 pre_reset_global_wsi : 1, 11288 pre_reset_pmacs_dmac : 1, 11289 pre_reset_tcl : 1, 11290 pre_reset_tqm : 1, 11291 pre_reset_wbm : 1, 11292 pre_reset_reo : 1, 11293 pre_reset_host : 1, 11294 reset_prerequisites : 1, 11295 reset_pre_ring_reset : 1, 11296 reset_apply_soft_reset : 1, 11297 reset_post_ring_reset : 1, 11298 reset_fw_tqm_cmdqs : 1, 11299 post_reset_host : 1, 11300 post_reset_umac_interrupts : 1, 11301 post_reset_wbm : 1, 11302 post_reset_reo : 1, 11303 post_reset_tqm : 1, 11304 post_reset_pmacs_dmac : 1, 11305 post_reset_tqm_sync_cmd : 1, 11306 post_reset_global_wsi : 1, 11307 post_reset_pmacs_hwmlos : 1, 11308 post_reset_enable_rxdma_prefetch : 1, 11309 post_reset_tcl : 1, 11310 post_reset_host_enq : 1, 11311 post_reset_verify_umac_recovered : 1, 11312 reserved : 5; 11313 } done_mask; 11314 }; 11315 } htt_mlo_umac_ssr_mlo_stats_t; 11316 11317 typedef struct { 11318 htt_tlv_hdr_t tlv_hdr; 11319 htt_mlo_umac_ssr_mlo_stats_t mlo; 11320 } htt_stats_mlo_umac_ssr_mlo_tlv; 11321 /* preserve old name alias for new name consistent with the tag name */ 11322 typedef htt_stats_mlo_umac_ssr_mlo_tlv htt_mlo_umac_ssr_mlo_stats_tlv; 11323 11324 /* dword0 - b'0 - PRE_RESET_DISABLE_RXDMA_PREFETCH */ 11325 #define HTT_UMAC_RECOVERY_DONE_PRE_RESET_DISABLE_RXDMA_PREFETCH_M 0x1 11326 #define HTT_UMAC_RECOVERY_DONE_PRE_RESET_DISABLE_RXDMA_PREFETCH_S 0 11327 #define HTT_UMAC_RECOVERY_DONE_PRE_RESET_DISABLE_RXDMA_PREFETCH_GET(word0) \ 11328 (((word0) & HTT_UMAC_RECOVERY_DONE_PRE_RESET_DISABLE_RXDMA_PREFETCH_M) >> \ 11329 HTT_UMAC_RECOVERY_DONE_PRE_RESET_DISABLE_RXDMA_PREFETCH_S) 11330 /* provide properly-named macro */ 11331 #define HTT_STATS_MLO_UMAC_SSR_MLO_MLO_PRE_RESET_DISABLE_RXDMA_PREFETCH_GET(word) \ 11332 HTT_UMAC_RECOVERY_DONE_PRE_RESET_DISABLE_RXDMA_PREFETCH_GET(word) 11333 #define HTT_UMAC_RECOVERY_DONE_PRE_RESET_DISABLE_RXDMA_PREFETCH_SET(word0, _val) \ 11334 do { \ 11335 HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_PRE_RESET_DISABLE_RXDMA_PREFETCH, _val); \ 11336 ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_PRE_RESET_DISABLE_RXDMA_PREFETCH_S));\ 11337 } while (0) 11338 11339 /* dword0 - b'1 - PRE_RESET_PMACS_HWMLOS */ 11340 #define HTT_UMAC_RECOVERY_DONE_PRE_RESET_PMACS_HWMLOS_M 0x2 11341 #define HTT_UMAC_RECOVERY_DONE_PRE_RESET_PMACS_HWMLOS_S 1 11342 #define HTT_UMAC_RECOVERY_DONE_PRE_RESET_PMACS_HWMLOS_GET(word0) \ 11343 (((word0) & HTT_UMAC_RECOVERY_DONE_PRE_RESET_PMACS_HWMLOS_M) >> \ 11344 HTT_UMAC_RECOVERY_DONE_PRE_RESET_PMACS_HWMLOS_S) 11345 /* provide properly-named macro */ 11346 #define HTT_STATS_MLO_UMAC_SSR_MLO_MLO_PRE_RESET_PMACS_HWMLOS_GET(word) \ 11347 HTT_UMAC_RECOVERY_DONE_PRE_RESET_PMACS_HWMLOS_GET(word) 11348 #define HTT_UMAC_RECOVERY_DONE_PRE_RESET_PMACS_HWMLOS_SET(word0, _val) \ 11349 do { \ 11350 HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_PRE_RESET_PMACS_HWMLOS, _val); \ 11351 ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_PRE_RESET_PMACS_HWMLOS_S));\ 11352 } while (0) 11353 11354 /* dword0 - b'2 - PRE_RESET_GLOBAL_WSI */ 11355 #define HTT_UMAC_RECOVERY_DONE_PRE_RESET_GLOBAL_WSI_M 0x4 11356 #define HTT_UMAC_RECOVERY_DONE_PRE_RESET_GLOBAL_WSI_S 2 11357 #define HTT_UMAC_RECOVERY_DONE_PRE_RESET_GLOBAL_WSI_GET(word0) \ 11358 (((word0) & HTT_UMAC_RECOVERY_DONE_PRE_RESET_GLOBAL_WSI_M) >> \ 11359 HTT_UMAC_RECOVERY_DONE_PRE_RESET_GLOBAL_WSI_S) 11360 /* provide properly-named macro */ 11361 #define HTT_STATS_MLO_UMAC_SSR_MLO_MLO_PRE_RESET_GLOBAL_WSI_GET(word) \ 11362 HTT_UMAC_RECOVERY_DONE_PRE_RESET_GLOBAL_WSI_GET(word) 11363 #define HTT_UMAC_RECOVERY_DONE_PRE_RESET_GLOBAL_WSI_SET(word0, _val) \ 11364 do { \ 11365 HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_PRE_RESET_GLOBAL_WSI, _val); \ 11366 ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_PRE_RESET_GLOBAL_WSI_S));\ 11367 } while (0) 11368 11369 /* dword0 - b'3 - PRE_RESET_PMACS_DMAC */ 11370 #define HTT_UMAC_RECOVERY_DONE_PRE_RESET_PMACS_DMAC_M 0x8 11371 #define HTT_UMAC_RECOVERY_DONE_PRE_RESET_PMACS_DMAC_S 3 11372 #define HTT_UMAC_RECOVERY_DONE_PRE_RESET_PMACS_DMAC_GET(word0) \ 11373 (((word0) & HTT_UMAC_RECOVERY_DONE_PRE_RESET_PMACS_DMAC_M) >> \ 11374 HTT_UMAC_RECOVERY_DONE_PRE_RESET_PMACS_DMAC_S) 11375 /* provide properly-named macro */ 11376 #define HTT_STATS_MLO_UMAC_SSR_MLO_MLO_PRE_RESET_PMACS_DMAC_GET(word) \ 11377 HTT_UMAC_RECOVERY_DONE_PRE_RESET_PMACS_DMAC_GET(word) 11378 #define HTT_UMAC_RECOVERY_DONE_PRE_RESET_PMACS_DMAC_SET(word0, _val) \ 11379 do { \ 11380 HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_PRE_RESET_PMACS_DMAC, _val); \ 11381 ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_PRE_RESET_PMACS_DMAC_S));\ 11382 } while (0) 11383 11384 /* dword0 - b'4 - PRE_RESET_TCL */ 11385 #define HTT_UMAC_RECOVERY_DONE_PRE_RESET_TCL_M 0x10 11386 #define HTT_UMAC_RECOVERY_DONE_PRE_RESET_TCL_S 4 11387 #define HTT_UMAC_RECOVERY_DONE_PRE_RESET_TCL_GET(word0) \ 11388 (((word0) & HTT_UMAC_RECOVERY_DONE_PRE_RESET_TCL_M) >> \ 11389 HTT_UMAC_RECOVERY_DONE_PRE_RESET_TCL_S) 11390 /* provide properly-named macro */ 11391 #define HTT_STATS_MLO_UMAC_SSR_MLO_MLO_PRE_RESET_TCL_GET(word) \ 11392 HTT_UMAC_RECOVERY_DONE_PRE_RESET_TCL_GET(word) 11393 #define HTT_UMAC_RECOVERY_DONE_PRE_RESET_TCL_SET(word0, _val) \ 11394 do { \ 11395 HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_PRE_RESET_TCL, _val); \ 11396 ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_PRE_RESET_TCL_S));\ 11397 } while (0) 11398 11399 /* dword0 - b'5 - PRE_RESET_TQM */ 11400 #define HTT_UMAC_RECOVERY_DONE_PRE_RESET_TQM_M 0x20 11401 #define HTT_UMAC_RECOVERY_DONE_PRE_RESET_TQM_S 5 11402 #define HTT_UMAC_RECOVERY_DONE_PRE_RESET_TQM_GET(word0) \ 11403 (((word0) & HTT_UMAC_RECOVERY_DONE_PRE_RESET_TQM_M) >> \ 11404 HTT_UMAC_RECOVERY_DONE_PRE_RESET_TQM_S) 11405 /* provide properly-named macro */ 11406 #define HTT_STATS_MLO_UMAC_SSR_MLO_MLO_PRE_RESET_TQM_GET(word) \ 11407 HTT_UMAC_RECOVERY_DONE_PRE_RESET_TQM_GET(word) 11408 #define HTT_UMAC_RECOVERY_DONE_PRE_RESET_TQM_SET(word0, _val) \ 11409 do { \ 11410 HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_PRE_RESET_TQM, _val); \ 11411 ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_PRE_RESET_TQM_S));\ 11412 } while (0) 11413 11414 /* dword0 - b'6 - PRE_RESET_WBM */ 11415 #define HTT_UMAC_RECOVERY_DONE_PRE_RESET_WBM_M 0x40 11416 #define HTT_UMAC_RECOVERY_DONE_PRE_RESET_WBM_S 6 11417 #define HTT_UMAC_RECOVERY_DONE_PRE_RESET_WBM_GET(word0) \ 11418 (((word0) & HTT_UMAC_RECOVERY_DONE_PRE_RESET_WBM_M) >> \ 11419 HTT_UMAC_RECOVERY_DONE_PRE_RESET_WBM_S) 11420 /* provide properly-named macro */ 11421 #define HTT_STATS_MLO_UMAC_SSR_MLO_MLO_PRE_RESET_WBM_GET(word) \ 11422 HTT_UMAC_RECOVERY_DONE_PRE_RESET_WBM_GET(word) 11423 #define HTT_UMAC_RECOVERY_DONE_PRE_RESET_WBM_SET(word0, _val) \ 11424 do { \ 11425 HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_PRE_RESET_WBM, _val); \ 11426 ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_PRE_RESET_WBM_S));\ 11427 } while (0) 11428 11429 /* dword0 - b'7 - PRE_RESET_REO */ 11430 #define HTT_UMAC_RECOVERY_DONE_PRE_RESET_REO_M 0x80 11431 #define HTT_UMAC_RECOVERY_DONE_PRE_RESET_REO_S 7 11432 #define HTT_UMAC_RECOVERY_DONE_PRE_RESET_REO_GET(word0) \ 11433 (((word0) & HTT_UMAC_RECOVERY_DONE_PRE_RESET_REO_M) >> \ 11434 HTT_UMAC_RECOVERY_DONE_PRE_RESET_REO_S) 11435 /* provide properly-named macro */ 11436 #define HTT_STATS_MLO_UMAC_SSR_MLO_MLO_PRE_RESET_REO_GET(word) \ 11437 HTT_UMAC_RECOVERY_DONE_PRE_RESET_REO_GET(word) 11438 #define HTT_UMAC_RECOVERY_DONE_PRE_RESET_REO_SET(word0, _val) \ 11439 do { \ 11440 HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_PRE_RESET_REO, _val); \ 11441 ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_PRE_RESET_REO_S));\ 11442 } while (0) 11443 11444 /* dword0 - b'8 - PRE_RESET_HOST */ 11445 #define HTT_UMAC_RECOVERY_DONE_PRE_RESET_HOST_M 0x100 11446 #define HTT_UMAC_RECOVERY_DONE_PRE_RESET_HOST_S 8 11447 #define HTT_UMAC_RECOVERY_DONE_PRE_RESET_HOST_GET(word0) \ 11448 (((word0) & HTT_UMAC_RECOVERY_DONE_PRE_RESET_HOST_M) >> \ 11449 HTT_UMAC_RECOVERY_DONE_PRE_RESET_HOST_S) 11450 /* provide properly-named macro */ 11451 #define HTT_STATS_MLO_UMAC_SSR_MLO_MLO_PRE_RESET_HOST_GET(word) \ 11452 HTT_UMAC_RECOVERY_DONE_PRE_RESET_HOST_GET(word) 11453 #define HTT_UMAC_RECOVERY_DONE_PRE_RESET_HOST_SET(word0, _val) \ 11454 do { \ 11455 HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_PRE_RESET_HOST, _val); \ 11456 ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_PRE_RESET_HOST_S));\ 11457 } while (0) 11458 11459 /* dword0 - b'9 - RESET_PREREQUISITES */ 11460 #define HTT_UMAC_RECOVERY_DONE_RESET_PREREQUISITES_M 0x200 11461 #define HTT_UMAC_RECOVERY_DONE_RESET_PREREQUISITES_S 9 11462 #define HTT_UMAC_RECOVERY_DONE_RESET_PREREQUISITES_GET(word0) \ 11463 (((word0) & HTT_UMAC_RECOVERY_DONE_RESET_PREREQUISITES_M) >> \ 11464 HTT_UMAC_RECOVERY_DONE_RESET_PREREQUISITES_S) 11465 /* provide properly-named macro */ 11466 #define HTT_STATS_MLO_UMAC_SSR_MLO_MLO_RESET_PREREQUISITES_GET(word) \ 11467 HTT_UMAC_RECOVERY_DONE_RESET_PREREQUISITES_GET(word) 11468 #define HTT_UMAC_RECOVERY_DONE_RESET_PREREQUISITES_SET(word0, _val) \ 11469 do { \ 11470 HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_RESET_PREREQUISITES, _val); \ 11471 ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_RESET_PREREQUISITES_S));\ 11472 } while (0) 11473 11474 /* dword0 - b'10 - RESET_PRE_RING_RESET */ 11475 #define HTT_UMAC_RECOVERY_DONE_RESET_PRE_RING_RESET_M 0x400 11476 #define HTT_UMAC_RECOVERY_DONE_RESET_PRE_RING_RESET_S 10 11477 #define HTT_UMAC_RECOVERY_DONE_RESET_PRE_RING_RESET_GET(word0) \ 11478 (((word0) & HTT_UMAC_RECOVERY_DONE_RESET_PRE_RING_RESET_M) >> \ 11479 HTT_UMAC_RECOVERY_DONE_RESET_PRE_RING_RESET_S) 11480 /* provide properly-named macro */ 11481 #define HTT_STATS_MLO_UMAC_SSR_MLO_MLO_RESET_PRE_RING_RESET_GET(word) \ 11482 HTT_UMAC_RECOVERY_DONE_RESET_PRE_RING_RESET_GET(word) 11483 #define HTT_UMAC_RECOVERY_DONE_RESET_PRE_RING_RESET_SET(word0, _val) \ 11484 do { \ 11485 HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_RESET_PRE_RING_RESET, _val); \ 11486 ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_RESET_PRE_RING_RESET_S));\ 11487 } while (0) 11488 11489 /* dword0 - b'11 - RESET_APPLY_SOFT_RESET */ 11490 #define HTT_UMAC_RECOVERY_DONE_RESET_APPLY_SOFT_RESET_M 0x800 11491 #define HTT_UMAC_RECOVERY_DONE_RESET_APPLY_SOFT_RESET_S 11 11492 #define HTT_UMAC_RECOVERY_DONE_RESET_APPLY_SOFT_RESET_GET(word0) \ 11493 (((word0) & HTT_UMAC_RECOVERY_DONE_RESET_APPLY_SOFT_RESET_M) >> \ 11494 HTT_UMAC_RECOVERY_DONE_RESET_APPLY_SOFT_RESET_S) 11495 /* provide properly-named macro */ 11496 #define HTT_STATS_MLO_UMAC_SSR_MLO_MLO_RESET_APPLY_SOFT_RESET_GET(word) \ 11497 HTT_UMAC_RECOVERY_DONE_RESET_APPLY_SOFT_RESET_GET(word) 11498 #define HTT_UMAC_RECOVERY_DONE_RESET_APPLY_SOFT_RESET_SET(word0, _val) \ 11499 do { \ 11500 HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_RESET_APPLY_SOFT_RESET, _val); \ 11501 ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_RESET_APPLY_SOFT_RESET_S));\ 11502 } while (0) 11503 11504 /* dword0 - b'12 - RESET_POST_RING_RESET */ 11505 #define HTT_UMAC_RECOVERY_DONE_RESET_POST_RING_RESET_M 0x1000 11506 #define HTT_UMAC_RECOVERY_DONE_RESET_POST_RING_RESET_S 12 11507 #define HTT_UMAC_RECOVERY_DONE_RESET_POST_RING_RESET_GET(word0) \ 11508 (((word0) & HTT_UMAC_RECOVERY_DONE_RESET_POST_RING_RESET_M) >> \ 11509 HTT_UMAC_RECOVERY_DONE_RESET_POST_RING_RESET_S) 11510 /* provide properly-named macro */ 11511 #define HTT_STATS_MLO_UMAC_SSR_MLO_MLO_RESET_POST_RING_RESET_GET(word) \ 11512 HTT_UMAC_RECOVERY_DONE_RESET_POST_RING_RESET_GET(word) 11513 #define HTT_UMAC_RECOVERY_DONE_RESET_POST_RING_RESET_SET(word0, _val) \ 11514 do { \ 11515 HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_RESET_POST_RING_RESET, _val); \ 11516 ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_RESET_POST_RING_RESET_S));\ 11517 } while (0) 11518 11519 /* dword0 - b'13 - RESET_FW_TQM_CMDQS */ 11520 #define HTT_UMAC_RECOVERY_DONE_RESET_FW_TQM_CMDQS_M 0x2000 11521 #define HTT_UMAC_RECOVERY_DONE_RESET_FW_TQM_CMDQS_S 13 11522 #define HTT_UMAC_RECOVERY_DONE_RESET_FW_TQM_CMDQS_GET(word0) \ 11523 (((word0) & HTT_UMAC_RECOVERY_DONE_RESET_FW_TQM_CMDQS_M) >> \ 11524 HTT_UMAC_RECOVERY_DONE_RESET_FW_TQM_CMDQS_S) 11525 /* provide properly-named macro */ 11526 #define HTT_STATS_MLO_UMAC_SSR_MLO_MLO_RESET_FW_TQM_CMDQS_GET(word) \ 11527 HTT_UMAC_RECOVERY_DONE_RESET_FW_TQM_CMDQS_GET(word) 11528 #define HTT_UMAC_RECOVERY_DONE_RESET_FW_TQM_CMDQS_SET(word0, _val) \ 11529 do { \ 11530 HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_RESET_FW_TQM_CMDQS, _val); \ 11531 ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_RESET_FW_TQM_CMDQS_S));\ 11532 } while (0) 11533 11534 /* dword0 - b'14 - POST_RESET_HOST */ 11535 #define HTT_UMAC_RECOVERY_DONE_POST_RESET_HOST_M 0x4000 11536 #define HTT_UMAC_RECOVERY_DONE_POST_RESET_HOST_S 14 11537 #define HTT_UMAC_RECOVERY_DONE_POST_RESET_HOST_GET(word0) \ 11538 (((word0) & HTT_UMAC_RECOVERY_DONE_POST_RESET_HOST_M) >> \ 11539 HTT_UMAC_RECOVERY_DONE_POST_RESET_HOST_S) 11540 /* provide properly-named macro */ 11541 #define HTT_STATS_MLO_UMAC_SSR_MLO_MLO_POST_RESET_HOST_GET(word) \ 11542 HTT_UMAC_RECOVERY_DONE_POST_RESET_HOST_GET(word) 11543 #define HTT_UMAC_RECOVERY_DONE_POST_RESET_HOST_SET(word0, _val) \ 11544 do { \ 11545 HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_POST_RESET_HOST, _val); \ 11546 ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_POST_RESET_HOST_S));\ 11547 } while (0) 11548 11549 /* dword0 - b'15 - POST_RESET_UMAC_INTERRUPTS */ 11550 #define HTT_UMAC_RECOVERY_DONE_POST_RESET_UMAC_INTERRUPTS_M 0x8000 11551 #define HTT_UMAC_RECOVERY_DONE_POST_RESET_UMAC_INTERRUPTS_S 15 11552 #define HTT_UMAC_RECOVERY_DONE_POST_RESET_UMAC_INTERRUPTS_GET(word0) \ 11553 (((word0) & HTT_UMAC_RECOVERY_DONE_POST_RESET_UMAC_INTERRUPTS_M) >> \ 11554 HTT_UMAC_RECOVERY_DONE_POST_RESET_UMAC_INTERRUPTS_S) 11555 /* provide properly-named macro */ 11556 #define HTT_STATS_MLO_UMAC_SSR_MLO_MLO_POST_RESET_UMAC_INTERRUPTS_GET(word) \ 11557 HTT_UMAC_RECOVERY_DONE_POST_RESET_UMAC_INTERRUPTS_GET(word) 11558 #define HTT_UMAC_RECOVERY_DONE_POST_RESET_UMAC_INTERRUPTS_SET(word0, _val) \ 11559 do { \ 11560 HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_POST_RESET_UMAC_INTERRUPTS, _val); \ 11561 ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_POST_RESET_UMAC_INTERRUPTS_S));\ 11562 } while (0) 11563 11564 /* dword0 - b'16 - POST_RESET_WBM */ 11565 #define HTT_UMAC_RECOVERY_DONE_POST_RESET_WBM_M 0x10000 11566 #define HTT_UMAC_RECOVERY_DONE_POST_RESET_WBM_S 16 11567 #define HTT_UMAC_RECOVERY_DONE_POST_RESET_WBM_GET(word0) \ 11568 (((word0) & HTT_UMAC_RECOVERY_DONE_POST_RESET_WBM_M) >> \ 11569 HTT_UMAC_RECOVERY_DONE_POST_RESET_WBM_S) 11570 /* provide properly-named macro */ 11571 #define HTT_STATS_MLO_UMAC_SSR_MLO_MLO_POST_RESET_WBM_GET(word) \ 11572 HTT_UMAC_RECOVERY_DONE_POST_RESET_WBM_GET(word) 11573 #define HTT_UMAC_RECOVERY_DONE_POST_RESET_WBM_SET(word0, _val) \ 11574 do { \ 11575 HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_POST_RESET_WBM, _val); \ 11576 ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_POST_RESET_WBM_S));\ 11577 } while (0) 11578 11579 /* dword0 - b'17 - POST_RESET_REO */ 11580 #define HTT_UMAC_RECOVERY_DONE_POST_RESET_REO_M 0x20000 11581 #define HTT_UMAC_RECOVERY_DONE_POST_RESET_REO_S 17 11582 #define HTT_UMAC_RECOVERY_DONE_POST_RESET_REO_GET(word0) \ 11583 (((word0) & HTT_UMAC_RECOVERY_DONE_POST_RESET_REO_M) >> \ 11584 HTT_UMAC_RECOVERY_DONE_POST_RESET_REO_S) 11585 /* provide properly-named macro */ 11586 #define HTT_STATS_MLO_UMAC_SSR_MLO_MLO_POST_RESET_REO_GET(word) \ 11587 HTT_UMAC_RECOVERY_DONE_POST_RESET_REO_GET(word) 11588 #define HTT_UMAC_RECOVERY_DONE_POST_RESET_REO_SET(word0, _val) \ 11589 do { \ 11590 HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_POST_RESET_REO, _val); \ 11591 ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_POST_RESET_REO_S));\ 11592 } while (0) 11593 11594 /* dword0 - b'18 - POST_RESET_TQM */ 11595 #define HTT_UMAC_RECOVERY_DONE_POST_RESET_TQM_M 0x40000 11596 #define HTT_UMAC_RECOVERY_DONE_POST_RESET_TQM_S 18 11597 #define HTT_UMAC_RECOVERY_DONE_POST_RESET_TQM_GET(word0) \ 11598 (((word0) & HTT_UMAC_RECOVERY_DONE_POST_RESET_TQM_M) >> \ 11599 HTT_UMAC_RECOVERY_DONE_POST_RESET_TQM_S) 11600 /* provide properly-named macro */ 11601 #define HTT_STATS_MLO_UMAC_SSR_MLO_MLO_POST_RESET_TQM_GET(word) \ 11602 HTT_UMAC_RECOVERY_DONE_POST_RESET_TQM_GET(word) 11603 #define HTT_UMAC_RECOVERY_DONE_POST_RESET_TQM_SET(word0, _val) \ 11604 do { \ 11605 HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_POST_RESET_TQM, _val); \ 11606 ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_POST_RESET_TQM_S));\ 11607 } while (0) 11608 11609 /* dword0 - b'19 - POST_RESET_PMACS_DMAC */ 11610 #define HTT_UMAC_RECOVERY_DONE_POST_RESET_PMACS_DMAC_M 0x80000 11611 #define HTT_UMAC_RECOVERY_DONE_POST_RESET_PMACS_DMAC_S 19 11612 #define HTT_UMAC_RECOVERY_DONE_POST_RESET_PMACS_DMAC_GET(word0) \ 11613 (((word0) & HTT_UMAC_RECOVERY_DONE_POST_RESET_PMACS_DMAC_M) >> \ 11614 HTT_UMAC_RECOVERY_DONE_POST_RESET_PMACS_DMAC_S) 11615 /* provide properly-named macro */ 11616 #define HTT_STATS_MLO_UMAC_SSR_MLO_MLO_POST_RESET_PMACS_DMAC_GET(word) \ 11617 HTT_UMAC_RECOVERY_DONE_POST_RESET_PMACS_DMAC_GET(word) 11618 #define HTT_UMAC_RECOVERY_DONE_POST_RESET_PMACS_DMAC_SET(word0, _val) \ 11619 do { \ 11620 HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_POST_RESET_PMACS_DMAC, _val); \ 11621 ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_POST_RESET_PMACS_DMAC_S));\ 11622 } while (0) 11623 11624 /* dword0 - b'20 - POST_RESET_TQM_SYNC_CMD */ 11625 #define HTT_UMAC_RECOVERY_DONE_POST_RESET_TQM_SYNC_CMD_M 0x100000 11626 #define HTT_UMAC_RECOVERY_DONE_POST_RESET_TQM_SYNC_CMD_S 20 11627 #define HTT_UMAC_RECOVERY_DONE_POST_RESET_TQM_SYNC_CMD_GET(word0) \ 11628 (((word0) & HTT_UMAC_RECOVERY_DONE_POST_RESET_TQM_SYNC_CMD_M) >> \ 11629 HTT_UMAC_RECOVERY_DONE_POST_RESET_TQM_SYNC_CMD_S) 11630 /* provide properly-named macro */ 11631 #define HTT_STATS_MLO_UMAC_SSR_MLO_MLO_POST_RESET_TQM_SYNC_CMD_GET(word) \ 11632 HTT_UMAC_RECOVERY_DONE_POST_RESET_TQM_SYNC_CMD_GET(word) 11633 #define HTT_UMAC_RECOVERY_DONE_POST_RESET_TQM_SYNC_CMD_SET(word0, _val) \ 11634 do { \ 11635 HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_POST_RESET_TQM_SYNC_CMD, _val); \ 11636 ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_POST_RESET_TQM_SYNC_CMD_S));\ 11637 } while (0) 11638 11639 /* dword0 - b'21 - POST_RESET_GLOBAL_WSI */ 11640 #define HTT_UMAC_RECOVERY_DONE_POST_RESET_GLOBAL_WSI_M 0x200000 11641 #define HTT_UMAC_RECOVERY_DONE_POST_RESET_GLOBAL_WSI_S 21 11642 #define HTT_UMAC_RECOVERY_DONE_POST_RESET_GLOBAL_WSI_GET(word0) \ 11643 (((word0) & HTT_UMAC_RECOVERY_DONE_POST_RESET_GLOBAL_WSI_M) >> \ 11644 HTT_UMAC_RECOVERY_DONE_POST_RESET_GLOBAL_WSI_S) 11645 /* provide properly-named macro */ 11646 #define HTT_STATS_MLO_UMAC_SSR_MLO_MLO_POST_RESET_GLOBAL_WSI_GET(word) \ 11647 HTT_UMAC_RECOVERY_DONE_POST_RESET_GLOBAL_WSI_GET(word) 11648 #define HTT_UMAC_RECOVERY_DONE_POST_RESET_GLOBAL_WSI_SET(word0, _val) \ 11649 do { \ 11650 HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_POST_RESET_GLOBAL_WSI, _val); \ 11651 ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_POST_RESET_GLOBAL_WSI_S));\ 11652 } while (0) 11653 11654 /* dword0 - b'22 - POST_RESET_PMACS_HWMLOS */ 11655 #define HTT_UMAC_RECOVERY_DONE_POST_RESET_PMACS_HWMLOS_M 0x400000 11656 #define HTT_UMAC_RECOVERY_DONE_POST_RESET_PMACS_HWMLOS_S 22 11657 #define HTT_UMAC_RECOVERY_DONE_POST_RESET_PMACS_HWMLOS_GET(word0) \ 11658 (((word0) & HTT_UMAC_RECOVERY_DONE_POST_RESET_PMACS_HWMLOS_M) >> \ 11659 HTT_UMAC_RECOVERY_DONE_POST_RESET_PMACS_HWMLOS_S) 11660 /* provide properly-named macro */ 11661 #define HTT_STATS_MLO_UMAC_SSR_MLO_MLO_POST_RESET_PMACS_HWMLOS_GET(word) \ 11662 HTT_UMAC_RECOVERY_DONE_POST_RESET_PMACS_HWMLOS_GET(word) 11663 #define HTT_UMAC_RECOVERY_DONE_POST_RESET_PMACS_HWMLOS_SET(word0, _val) \ 11664 do { \ 11665 HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_POST_RESET_PMACS_HWMLOS, _val); \ 11666 ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_POST_RESET_PMACS_HWMLOS_S));\ 11667 } while (0) 11668 11669 /* dword0 - b'23 - POST_RESET_ENABLE_RXDMA_PREFETCH */ 11670 #define HTT_UMAC_RECOVERY_DONE_POST_RESET_ENABLE_RXDMA_PREFETCH_M 0x800000 11671 #define HTT_UMAC_RECOVERY_DONE_POST_RESET_ENABLE_RXDMA_PREFETCH_S 23 11672 #define HTT_UMAC_RECOVERY_DONE_POST_RESET_ENABLE_RXDMA_PREFETCH_GET(word0) \ 11673 (((word0) & HTT_UMAC_RECOVERY_DONE_POST_RESET_ENABLE_RXDMA_PREFETCH_M) >> \ 11674 HTT_UMAC_RECOVERY_DONE_POST_RESET_ENABLE_RXDMA_PREFETCH_S) 11675 /* provide properly-named macro */ 11676 #define HTT_STATS_MLO_UMAC_SSR_MLO_MLO_POST_RESET_ENABLE_RXDMA_PREFETCH_GET(word) \ 11677 HTT_UMAC_RECOVERY_DONE_POST_RESET_ENABLE_RXDMA_PREFETCH_GET(word) 11678 #define HTT_UMAC_RECOVERY_DONE_POST_RESET_ENABLE_RXDMA_PREFETCH_SET(word0, _val) \ 11679 do { \ 11680 HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_POST_RESET_ENABLE_RXDMA_PREFETCH, _val); \ 11681 ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_POST_RESET_ENABLE_RXDMA_PREFETCH_S));\ 11682 } while (0) 11683 11684 /* dword0 - b'24 - POST_RESET_TCL */ 11685 #define HTT_UMAC_RECOVERY_DONE_POST_RESET_TCL_M 0x1000000 11686 #define HTT_UMAC_RECOVERY_DONE_POST_RESET_TCL_S 24 11687 #define HTT_UMAC_RECOVERY_DONE_POST_RESET_TCL_GET(word0) \ 11688 (((word0) & HTT_UMAC_RECOVERY_DONE_POST_RESET_TCL_M) >> \ 11689 HTT_UMAC_RECOVERY_DONE_POST_RESET_TCL_S) 11690 /* provide properly-named macro */ 11691 #define HTT_STATS_MLO_UMAC_SSR_MLO_MLO_POST_RESET_TCL_GET(word) \ 11692 HTT_UMAC_RECOVERY_DONE_POST_RESET_TCL_GET(word) 11693 #define HTT_UMAC_RECOVERY_DONE_POST_RESET_TCL_SET(word0, _val) \ 11694 do { \ 11695 HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_POST_RESET_TCL, _val); \ 11696 ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_POST_RESET_TCL_S));\ 11697 } while (0) 11698 11699 /* dword0 - b'25 - POST_RESET_HOST_ENQ */ 11700 #define HTT_UMAC_RECOVERY_DONE_POST_RESET_HOST_ENQ_M 0x2000000 11701 #define HTT_UMAC_RECOVERY_DONE_POST_RESET_HOST_ENQ_S 25 11702 #define HTT_UMAC_RECOVERY_DONE_POST_RESET_HOST_ENQ_GET(word0) \ 11703 (((word0) & HTT_UMAC_RECOVERY_DONE_POST_RESET_HOST_ENQ_M) >> \ 11704 HTT_UMAC_RECOVERY_DONE_POST_RESET_HOST_ENQ_S) 11705 /* provide properly-named macro */ 11706 #define HTT_STATS_MLO_UMAC_SSR_MLO_MLO_POST_RESET_HOST_ENQ_GET(word) \ 11707 HTT_UMAC_RECOVERY_DONE_POST_RESET_HOST_ENQ_GET(word) 11708 #define HTT_UMAC_RECOVERY_DONE_POST_RESET_HOST_ENQ_SET(word0, _val) \ 11709 do { \ 11710 HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_POST_RESET_HOST_ENQ, _val); \ 11711 ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_POST_RESET_HOST_ENQ_S));\ 11712 } while (0) 11713 11714 /* dword0 - b'26 - POST_RESET_VERIFY_UMAC_RECOVERED */ 11715 #define HTT_UMAC_RECOVERY_DONE_POST_RESET_VERIFY_UMAC_RECOVERED_M 0x4000000 11716 #define HTT_UMAC_RECOVERY_DONE_POST_RESET_VERIFY_UMAC_RECOVERED_S 26 11717 #define HTT_UMAC_RECOVERY_DONE_POST_RESET_VERIFY_UMAC_RECOVERED_GET(word0) \ 11718 (((word0) & HTT_UMAC_RECOVERY_DONE_POST_RESET_VERIFY_UMAC_RECOVERED_M) >> \ 11719 HTT_UMAC_RECOVERY_DONE_POST_RESET_VERIFY_UMAC_RECOVERED_S) 11720 /* provide properly-named macro */ 11721 #define HTT_STATS_MLO_UMAC_SSR_MLO_MLO_POST_RESET_VERIFY_UMAC_RECOVERED_GET(word) \ 11722 HTT_UMAC_RECOVERY_DONE_POST_RESET_VERIFY_UMAC_RECOVERED_GET(word) 11723 #define HTT_UMAC_RECOVERY_DONE_POST_RESET_VERIFY_UMAC_RECOVERED_SET(word0, _val) \ 11724 do { \ 11725 HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_POST_RESET_VERIFY_UMAC_RECOVERED, _val); \ 11726 ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_POST_RESET_VERIFY_UMAC_RECOVERED_S));\ 11727 } while (0) 11728 11729 typedef struct { 11730 htt_tlv_hdr_t tlv_hdr; 11731 A_UINT32 last_trigger_request_ms; 11732 A_UINT32 last_start_ms; 11733 A_UINT32 last_start_disengage_umac_ms; 11734 A_UINT32 last_enter_ssr_platform_thread_ms; 11735 A_UINT32 last_exit_ssr_platform_thread_ms; 11736 A_UINT32 last_start_engage_umac_ms; 11737 A_UINT32 last_done_successful_ms; 11738 A_UINT32 post_reset_tqm_sync_cmd_completion_ms; 11739 A_UINT32 htt_sync_mlo_initiate_umac_recovery_ms; 11740 A_UINT32 htt_sync_do_pre_reset_ms; 11741 A_UINT32 htt_sync_do_post_reset_start_ms; 11742 A_UINT32 htt_sync_do_post_reset_complete_ms; 11743 } htt_stats_mlo_umac_ssr_kpi_tstmp_tlv; 11744 /* preserve old name alias for new name consistent with the tag name */ 11745 typedef htt_stats_mlo_umac_ssr_kpi_tstmp_tlv 11746 htt_mlo_umac_ssr_kpi_tstamp_stats_tlv; 11747 11748 typedef struct { 11749 htt_tlv_hdr_t tlv_hdr; 11750 A_UINT32 htt_sync_start_ms; 11751 A_UINT32 htt_sync_delta_ms; 11752 A_UINT32 post_t2h_start_ms; 11753 A_UINT32 post_t2h_delta_ms; 11754 A_UINT32 post_t2h_msg_read_shmem_ms; 11755 A_UINT32 post_t2h_msg_write_shmem_ms; 11756 A_UINT32 post_t2h_msg_send_msg_to_host_ms; 11757 } htt_stats_mlo_umac_ssr_handshake_tlv; 11758 /* preserve old name alias for new name consistent with the tag name */ 11759 typedef htt_stats_mlo_umac_ssr_handshake_tlv 11760 htt_mlo_umac_htt_handshake_stats_tlv; 11761 11762 #ifdef ATH_TARGET 11763 typedef struct { 11764 /* 11765 * Note that the host cannot use this struct directly, but instead needs 11766 * to use the TLV header within each element of each of the arrays in 11767 * this struct to determine where the subsequent item resides. 11768 */ 11769 htt_stats_mlo_umac_ssr_dbg_tlv dbg_point[HTT_MLO_UMAC_SSR_DBG_POINT_MAX]; 11770 htt_stats_mlo_umac_ssr_handshake_tlv htt_handshakes[HTT_MLO_UMAC_RECOVERY_HANDSHAKE_COUNT]; 11771 } htt_mlo_umac_ssr_kpi_delta_stats_t; 11772 #endif /* ATH_TARGET */ 11773 11774 #ifdef ATH_TARGET 11775 typedef struct { 11776 /* 11777 * Since each item within htt_mlo_umac_ssr_kpi_delta_stats_t has its own 11778 * TLV header, and since no additional fields are added in this struct 11779 * beyond the htt_mlo_umac_ssr_kpi_delta_stats_t info, no additional 11780 * TLV header is needed. 11781 * 11782 * Note that the host cannot use this struct directly, but instead needs 11783 * to use the TLV header within each item inside the 11784 * htt_mlo_umac_ssr_kpi_delta_stats_t to determine where the subsequent 11785 * item resides. 11786 */ 11787 htt_mlo_umac_ssr_kpi_delta_stats_t kpi_delta; 11788 } htt_mlo_umac_ssr_kpi_delta_stats_tlv; 11789 #endif /* ATH_TARGET */ 11790 11791 typedef struct { 11792 A_UINT32 last_e2e_delta_ms; 11793 A_UINT32 max_e2e_delta_ms; 11794 A_UINT32 per_handshake_max_allowed_delta_ms; 11795 /* Total done count */ 11796 A_UINT32 total_success_runs_cnt; 11797 A_UINT32 umac_recovery_in_progress; 11798 /* Count of Disengaged in Pre reset */ 11799 A_UINT32 umac_disengaged_count; 11800 /* Count of UMAC Soft/Control Reset */ 11801 A_UINT32 umac_soft_reset_count; 11802 /* Count of Engaged in Post reset */ 11803 A_UINT32 umac_engaged_count; 11804 } htt_mlo_umac_ssr_common_stats_t; 11805 11806 typedef struct { 11807 htt_tlv_hdr_t tlv_hdr; 11808 htt_mlo_umac_ssr_common_stats_t cmn; 11809 } htt_stats_mlo_umac_ssr_cmn_tlv; 11810 /* preserve old name alias for new name consistent with the tag name */ 11811 typedef htt_stats_mlo_umac_ssr_cmn_tlv htt_mlo_umac_ssr_common_stats_tlv; 11812 11813 typedef struct { 11814 A_UINT32 trigger_requests_count; 11815 A_UINT32 trigger_count_for_umac_hang; 11816 A_UINT32 trigger_count_for_mlo_target_recovery_mode1; 11817 A_UINT32 trigger_count_for_unknown_signature; 11818 A_UINT32 total_trig_dropped; 11819 A_UINT32 trigger_count_for_unit_test_direct_trigger; 11820 A_UINT32 trigger_count_for_tx_de_wdg_dummy_frame_tout; 11821 A_UINT32 trigger_count_for_peer_delete_wdg_dummy_frame_tout; 11822 A_UINT32 trigger_count_for_reo_hang; 11823 A_UINT32 trigger_count_for_tqm_hang; 11824 A_UINT32 trigger_count_for_tcl_hang; 11825 A_UINT32 trigger_count_for_wbm_hang; 11826 } htt_mlo_umac_ssr_trigger_stats_t; 11827 11828 typedef struct { 11829 htt_tlv_hdr_t tlv_hdr; 11830 htt_mlo_umac_ssr_trigger_stats_t trigger; 11831 } htt_stats_mlo_umac_ssr_trigger_tlv; 11832 /* preserve old name alias for new name consistent with the tag name */ 11833 typedef htt_stats_mlo_umac_ssr_trigger_tlv htt_mlo_umac_ssr_trigger_stats_tlv; 11834 11835 #ifdef ATH_TARGET 11836 typedef struct { 11837 /* 11838 * Note that the host cannot use this struct directly, but instead needs 11839 * to use the TLV header within each element to determine where the 11840 * subsequent element resides. 11841 */ 11842 htt_mlo_umac_ssr_kpi_delta_stats_tlv kpi_delta_tlv; 11843 htt_stats_mlo_umac_ssr_kpi_tstmp_tlv kpi_tstamp_tlv; 11844 } htt_mlo_umac_ssr_kpi_stats_t; 11845 #endif /* ATH_TARGET */ 11846 11847 #ifdef ATH_TARGET 11848 typedef struct { 11849 /* 11850 * Since the embedded sub-struct within htt_mlo_umac_ssr_kpi_stats_tlv 11851 * has its own TLV header, and since no additional fields are added in 11852 * this struct beyond the htt_mlo_umac_ssr_kpi_stats_t info, no additional 11853 * TLV header is needed. 11854 * 11855 * Note that the host cannot use this struct directly, but instead needs 11856 * to use the TLV header within the htt_mlo_umac_ssr_kpi_stats_t sub-struct 11857 * to determine how much data is present for this struct. 11858 */ 11859 htt_mlo_umac_ssr_kpi_stats_t kpi; 11860 } htt_mlo_umac_ssr_kpi_stats_tlv; 11861 #endif /* ATH_TARGET */ 11862 11863 #ifdef ATH_TARGET 11864 typedef struct { 11865 /* 11866 * Note that the host cannot use this struct directly, but instead needs 11867 * to use the TLV header within each element to determine where the 11868 * subsequent element resides. 11869 */ 11870 htt_stats_mlo_umac_ssr_trigger_tlv trigger_tlv; 11871 htt_mlo_umac_ssr_kpi_stats_tlv kpi_tlv; 11872 htt_stats_mlo_umac_ssr_mlo_tlv mlo_tlv; 11873 htt_stats_mlo_umac_ssr_cmn_tlv cmn_tlv; 11874 } htt_mlo_umac_ssr_stats_tlv; 11875 #endif /* ATH_TARGET */ 11876 11877 /*============= end MLO UMAC SSR stats ============= } */ 11878 11879 typedef struct { 11880 A_UINT32 total_done; 11881 A_UINT32 trigger_requests_count; 11882 A_UINT32 total_trig_dropped; 11883 A_UINT32 umac_disengaged_count; 11884 A_UINT32 umac_soft_reset_count; 11885 A_UINT32 umac_engaged_count; 11886 A_UINT32 last_trigger_request_ms; 11887 A_UINT32 last_start_ms; 11888 A_UINT32 last_start_disengage_umac_ms; 11889 A_UINT32 last_enter_ssr_platform_thread_ms; 11890 A_UINT32 last_exit_ssr_platform_thread_ms; 11891 A_UINT32 last_start_engage_umac_ms; 11892 A_UINT32 last_done_successful_ms; 11893 A_UINT32 last_e2e_delta_ms; 11894 A_UINT32 max_e2e_delta_ms; 11895 A_UINT32 trigger_count_for_umac_hang; 11896 A_UINT32 trigger_count_for_mlo_quick_ssr; 11897 A_UINT32 trigger_count_for_unknown_signature; 11898 A_UINT32 post_reset_tqm_sync_cmd_completion_ms; 11899 A_UINT32 htt_sync_mlo_initiate_umac_recovery_ms; 11900 A_UINT32 htt_sync_do_pre_reset_ms; 11901 A_UINT32 htt_sync_do_post_reset_start_ms; 11902 A_UINT32 htt_sync_do_post_reset_complete_ms; 11903 } htt_umac_ssr_stats_t; 11904 11905 typedef struct { 11906 htt_tlv_hdr_t tlv_hdr; 11907 htt_umac_ssr_stats_t stats; 11908 } htt_stats_umac_ssr_tlv; 11909 /* preserve old name alias for new name consistent with the tag name */ 11910 typedef htt_stats_umac_ssr_tlv htt_umac_ssr_stats_tlv; 11911 11912 typedef struct { 11913 htt_tlv_hdr_t tlv_hdr; 11914 A_UINT32 svc_class_id; 11915 /* codel_drops: 11916 * How many times have MSDU queues belonging to this service class 11917 * dropped their head MSDU due to the queue's latency being above 11918 * the CoDel latency limit specified for the service class throughout 11919 * the full CoDel latency statistics collection window. 11920 */ 11921 A_UINT32 codel_drops; 11922 /* codel_no_drops: 11923 * How many times have MSDU queues belonging to this service class 11924 * completed a CoDel latency statistics collection window and 11925 * concluded that no head MSDU drop is needed, due to the MSDU queue's 11926 * latency being under the limit specified for the service class at 11927 * some point during the window. 11928 */ 11929 A_UINT32 codel_no_drops; 11930 } htt_stats_codel_svc_class_tlv; 11931 /* preserve old name alias for new name consistent with the tag name */ 11932 typedef htt_stats_codel_svc_class_tlv htt_codel_svc_class_stats_tlv; 11933 11934 #define HTT_CODEL_MSDUQ_STATS_TX_FLOW_NUM_M 0x0000FFFF 11935 #define HTT_CODEL_MSDUQ_STATS_TX_FLOW_NUM_S 0 11936 11937 #define HTT_CODEL_MSDUQ_STATS_TX_FLOW_NUM_GET(_var) \ 11938 (((_var) & HTT_CODEL_MSDUQ_STATS_TX_FLOW_NUM_M) >> \ 11939 HTT_CODEL_MSDUQ_STATS_TX_FLOW_NUM_S) 11940 #define HTT_CODEL_MSDUQ_STATS_TX_FLOW_NUM_SET(_var, _val) \ 11941 do { \ 11942 HTT_CHECK_SET_VAL(HTT_CODEL_MSDUQ_STATS_TX_FLOW_NUM, _val); \ 11943 ((_var) |= ((_val) << HTT_CODEL_MSDUQ_STATS_TX_FLOW_NUM_S)); \ 11944 } while (0) 11945 11946 #define HTT_CODEL_MSDUQ_STATS_SVC_CLASS_ID_M 0x00FF0000 11947 #define HTT_CODEL_MSDUQ_STATS_SVC_CLASS_ID_S 16 11948 11949 #define HTT_CODEL_MSDUQ_STATS_SVC_CLASS_ID_GET(_var) \ 11950 (((_var) & HTT_CODEL_MSDUQ_STATS_SVC_CLASS_ID_M) >> \ 11951 HTT_CODEL_MSDUQ_STATS_SVC_CLASS_ID_S) 11952 #define HTT_CODEL_MSDUQ_STATS_SVC_CLASS_ID_SET(_var, _val) \ 11953 do { \ 11954 HTT_CHECK_SET_VAL(HTT_CODEL_MSDUQ_STATS_SVC_CLASS_ID, _val); \ 11955 ((_var) |= ((_val) << HTT_CODEL_MSDUQ_STATS_SVC_CLASS_ID_S)); \ 11956 } while (0) 11957 11958 #define HTT_CODEL_MSDUQ_STATS_DROPS_M 0x0000FFFF 11959 #define HTT_CODEL_MSDUQ_STATS_DROPS_S 0 11960 11961 #define HTT_CODEL_MSDUQ_STATS_DROPS_GET(_var) \ 11962 (((_var) & HTT_CODEL_MSDUQ_STATS_DROPS_M) >> \ 11963 HTT_CODEL_MSDUQ_STATS_DROPS_S) 11964 #define HTT_CODEL_MSDUQ_STATS_DROPS_SET(_var, _val) \ 11965 do { \ 11966 HTT_CHECK_SET_VAL(HTT_CODEL_MSDUQ_STATS_DROPS, _val); \ 11967 ((_var) |= ((_val) << HTT_CODEL_MSDUQ_STATS_DROPS_S)); \ 11968 } while (0) 11969 11970 #define HTT_CODEL_MSDUQ_STATS_NO_DROPS_M 0xFFFF0000 11971 #define HTT_CODEL_MSDUQ_STATS_NO_DROPS_S 16 11972 11973 #define HTT_CODEL_MSDUQ_STATS_NO_DROPS_GET(_var) \ 11974 (((_var) & HTT_CODEL_MSDUQ_STATS_NO_DROPS_M) >> \ 11975 HTT_CODEL_MSDUQ_STATS_NO_DROPS_S) 11976 #define HTT_CODEL_MSDUQ_STATS_NO_DROPS_SET(_var, _val) \ 11977 do { \ 11978 HTT_CHECK_SET_VAL(HTT_CODEL_MSDUQ_STATS_NO_DROPS, _val); \ 11979 ((_var) |= ((_val) << HTT_CODEL_MSDUQ_STATS_NO_DROPS_S)); \ 11980 } while (0) 11981 11982 typedef struct { 11983 htt_tlv_hdr_t tlv_hdr; 11984 union { 11985 A_UINT32 id__word; 11986 struct { 11987 A_UINT32 tx_flow_num: 16, /* FW's MSDU queue ID */ 11988 svc_class_id: 8, 11989 reserved: 8; 11990 }; 11991 }; 11992 union { 11993 A_UINT32 stats__word; 11994 struct { 11995 A_UINT32 11996 codel_drops: 16, 11997 codel_no_drops: 16; 11998 }; 11999 }; 12000 } htt_stats_codel_msduq_tlv; 12001 /* preserve old name alias for new name consistent with the tag name */ 12002 typedef htt_stats_codel_msduq_tlv htt_codel_msduq_stats_tlv; 12003 12004 /*===================== start MLO stats ====================*/ 12005 12006 typedef struct { 12007 htt_tlv_hdr_t tlv_hdr; 12008 A_UINT32 pref_link_num_sec_link_sched; 12009 A_UINT32 pref_link_num_pref_link_timeout; 12010 A_UINT32 pref_link_num_pref_link_sch_delay_ipc; 12011 A_UINT32 pref_link_num_pref_link_timeout_ipc; 12012 } htt_stats_mlo_sched_stats_tlv; 12013 /* preserve old name alias for new name consistent with the tag name */ 12014 typedef htt_stats_mlo_sched_stats_tlv htt_mlo_sched_stats_tlv; 12015 12016 /* STATS_TYPE : HTT_DBG_MLO_SCHED_STATS 12017 * TLV_TAGS: 12018 * - HTT_STATS_MLO_SCHED_STATS_TAG 12019 */ 12020 /* NOTE: 12021 * This structure is for documentation, and cannot be safely used directly. 12022 * Instead, use the constituent TLV structures to fill/parse. 12023 */ 12024 #ifdef ATH_TARGET 12025 typedef struct _htt_mlo_sched_stats { 12026 htt_stats_mlo_sched_stats_tlv preferred_link_stats; 12027 } htt_mlo_sched_stats_t; 12028 #endif /* ATH_TARGET */ 12029 12030 #define HTT_STATS_HWMLO_MAX_LINKS 6 12031 #define HTT_STATS_MLO_MAX_IPC_RINGS 7 12032 12033 typedef struct { 12034 htt_tlv_hdr_t tlv_hdr; 12035 A_UINT32 mlo_ipc_ring_full_cnt[HTT_STATS_HWMLO_MAX_LINKS][HTT_STATS_MLO_MAX_IPC_RINGS]; 12036 } htt_stats_pdev_mlo_ipc_stats_tlv; 12037 /* preserve old name alias for new name consistent with the tag name */ 12038 typedef htt_stats_pdev_mlo_ipc_stats_tlv htt_pdev_mlo_ipc_stats_tlv; 12039 12040 /* STATS_TYPE : HTT_DBG_MLO_IPC_STATS 12041 * TLV_TAGS: 12042 * - HTT_STATS_PDEV_MLO_IPC_STATS_TAG 12043 */ 12044 /* NOTE: 12045 * This structure is for documentation, and cannot be safely used directly. 12046 * Instead, use the constituent TLV structures to fill/parse. 12047 */ 12048 #ifdef ATH_TARGET 12049 typedef struct _htt_mlo_ipc_stats { 12050 htt_stats_pdev_mlo_ipc_stats_tlv mlo_ipc_stats; 12051 } htt_pdev_mlo_ipc_stats_t; 12052 #endif /* ATH_TARGET */ 12053 12054 /*===================== end MLO stats ======================*/ 12055 12056 typedef enum { 12057 HTT_CTRL_PATH_STATS_CAL_TYPE_ADC = 0x0, 12058 HTT_CTRL_PATH_STATS_CAL_TYPE_DAC = 0x1, 12059 HTT_CTRL_PATH_STATS_CAL_TYPE_PROCESS = 0x2, 12060 HTT_CTRL_PATH_STATS_CAL_TYPE_NOISE_FLOOR = 0x3, 12061 HTT_CTRL_PATH_STATS_CAL_TYPE_RXDCO = 0x4, 12062 HTT_CTRL_PATH_STATS_CAL_TYPE_COMB_TXLO_TXIQ_RXIQ = 0x5, 12063 HTT_CTRL_PATH_STATS_CAL_TYPE_TXLO = 0x6, 12064 HTT_CTRL_PATH_STATS_CAL_TYPE_TXIQ = 0x7, 12065 HTT_CTRL_PATH_STATS_CAL_TYPE_RXIQ = 0x8, 12066 HTT_CTRL_PATH_STATS_CAL_TYPE_IM2 = 0x9, 12067 HTT_CTRL_PATH_STATS_CAL_TYPE_LNA = 0xa, 12068 HTT_CTRL_PATH_STATS_CAL_TYPE_DPD_LP_RXDCO = 0xb, 12069 HTT_CTRL_PATH_STATS_CAL_TYPE_DPD_LP_RXIQ = 0xc, 12070 HTT_CTRL_PATH_STATS_CAL_TYPE_DPD_MEMORYLESS = 0xd, 12071 HTT_CTRL_PATH_STATS_CAL_TYPE_DPD_MEMORY = 0xe, 12072 HTT_CTRL_PATH_STATS_CAL_TYPE_IBF = 0xf, 12073 HTT_CTRL_PATH_STATS_CAL_TYPE_PDET_AND_PAL = 0x10, 12074 HTT_CTRL_PATH_STATS_CAL_TYPE_RXDCO_IQ = 0x11, 12075 HTT_CTRL_PATH_STATS_CAL_TYPE_RXDCO_DTIM = 0x12, 12076 HTT_CTRL_PATH_STATS_CAL_TYPE_TPC_CAL = 0x13, 12077 HTT_CTRL_PATH_STATS_CAL_TYPE_DPD_TIMEREQ = 0x14, 12078 HTT_CTRL_PATH_STATS_CAL_TYPE_BWFILTER = 0x15, 12079 HTT_CTRL_PATH_STATS_CAL_TYPE_PEF = 0x16, 12080 HTT_CTRL_PATH_STATS_CAL_TYPE_PADROOP = 0x17, 12081 HTT_CTRL_PATH_STATS_CAL_TYPE_SELFCALTPC = 0x18, 12082 HTT_CTRL_PATH_STATS_CAL_TYPE_RXSPUR = 0x19, 12083 12084 /* add new cal types above this line */ 12085 HTT_CTRL_PATH_STATS_CAL_TYPE_INVALID = 0xFF 12086 } htt_ctrl_path_stats_cal_type_ids; 12087 12088 #define HTT_RETURN_STRING(str) case ((str)): return (A_UINT8 *)(# str); 12089 12090 #define HTT_GET_BITS(_val, _index, _num_bits) \ 12091 (((_val) >> (_index)) & ((1 << (_num_bits)) - 1)) 12092 12093 #define HTT_CTRL_PATH_CALIBRATION_STATS_CAL_TYPE_GET(cal_info) \ 12094 HTT_GET_BITS(cal_info, 0, 8) 12095 12096 /* 12097 * Used by some hosts to print names of cal type, based on 12098 * htt_ctrl_path_cal_type_ids values specified in 12099 * htt_ctrl_path_calibration_stats_struct in ctrl_path_stats event msg. 12100 */ 12101 #ifdef HTT_CTRL_PATH_STATS_CAL_TYPE_STRINGS 12102 static INLINE A_UINT8 *htt_ctrl_path_cal_type_id_to_name(A_UINT32 cal_type_id) 12103 { 12104 switch (cal_type_id) 12105 { 12106 HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_ADC); 12107 HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_DAC); 12108 HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_PROCESS); 12109 HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_NOISE_FLOOR); 12110 HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_RXDCO); 12111 HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_COMB_TXLO_TXIQ_RXIQ); 12112 HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_TXLO); 12113 HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_TXIQ); 12114 HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_RXIQ); 12115 HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_IM2); 12116 HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_LNA); 12117 HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_DPD_LP_RXDCO); 12118 HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_DPD_LP_RXIQ); 12119 HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_DPD_MEMORYLESS); 12120 HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_DPD_MEMORY); 12121 HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_IBF); 12122 HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_PDET_AND_PAL); 12123 HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_RXDCO_IQ); 12124 HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_RXDCO_DTIM); 12125 HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_TPC_CAL); 12126 HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_DPD_TIMEREQ); 12127 HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_BWFILTER); 12128 HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_PEF); 12129 HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_PADROOP); 12130 HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_SELFCALTPC); 12131 HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_RXSPUR); 12132 } 12133 12134 return (A_UINT8 *) "HTT_CTRL_PATH_STATS_CAL_TYPE_UNKNOWN"; 12135 } 12136 #endif /* HTT_CTRL_PATH_STATS_CAL_TYPE_STRINGS */ 12137 12138 /*===================== Start GTX stats ====================*/ 12139 #define HTT_NUM_MCS_PER_NSS 16 12140 typedef struct { 12141 htt_tlv_hdr_t tlv_hdr; 12142 A_UINT32 gtx_enabled; /* shows whether Green Tx feature is enabled */ 12143 A_INT32 mcs_tpc_min[HTT_NUM_MCS_PER_NSS]; /* shows current MCS's minimum TPC in 0.25dBm units */ 12144 A_INT32 mcs_tpc_max[HTT_NUM_MCS_PER_NSS]; /* shows current MCS's maximum TPC in 0.25dBm units */ 12145 A_UINT32 mcs_tpc_diff[HTT_NUM_MCS_PER_NSS]; /* shows current MCS's difference between maximum and minimum TPC in 0.25dB unit*/ 12146 } htt_stats_gtx_tlv; 12147 /*===================== End GTX stats ====================*/ 12148 12149 #endif /* __HTT_STATS_H__ */ 12150