1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * Copyright(c) 2023 Huawei
4  * CXL Specification rev 3.0 Setion 8.2.7 (CPMU Register Interface)
5  */
6 #ifndef CXL_PMU_H
7 #define CXL_PMU_H
8 #include <linux/device.h>
9 
10 enum cxl_pmu_type {
11 	CXL_PMU_MEMDEV,
12 };
13 
14 #define CXL_PMU_REGMAP_SIZE 0xe00 /* Table 8-32 CXL 3.0 specification */
15 struct cxl_pmu {
16 	struct device dev;
17 	void __iomem *base;
18 	int assoc_id;
19 	int index;
20 	enum cxl_pmu_type type;
21 };
22 
23 #define to_cxl_pmu(dev) container_of(dev, struct cxl_pmu, dev)
24 struct cxl_pmu_regs;
25 int devm_cxl_pmu_add(struct device *parent, struct cxl_pmu_regs *regs,
26 		     int assoc_id, int idx, enum cxl_pmu_type type);
27 
28 #endif
29