| /linux-6.12.1/drivers/gpu/drm/i915/display/ |
| D | intel_dkl_phy_regs.h | 29 #define _DKL_REG_PHY_BASE(tc_port) _PORT(tc_port, \ argument
39 #define _DKL_REG(tc_port, phy_offset) \ argument
46 #define _DKL_REG_LN(tc_port, ln_idx, ln0_offs, ln1_offs) \ argument
51 #define DKL_PCS_DW5(tc_port, ln) _DKL_REG_LN(tc_port, ln, \ argument
57 #define DKL_PLL_DIV0(tc_port) _DKL_REG(tc_port, \ argument
76 #define DKL_PLL_DIV1(tc_port) _DKL_REG(tc_port, \ argument
84 #define DKL_PLL_SSC(tc_port) _DKL_REG(tc_port, \ argument
95 #define DKL_PLL_BIAS(tc_port) _DKL_REG(tc_port, \ argument
103 #define DKL_PLL_TDC_COLDST_BIAS(tc_port) _DKL_REG(tc_port, \ argument
111 #define DKL_REFCLKIN_CTL(tc_port) _DKL_REG(tc_port, \ argument
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| D | intel_mg_phy_regs.h | 11 #define MG_PHY_PORT_LN(ln, tc_port, ln0p1, ln0p2, ln1p1) \ argument
18 #define MG_TX1_LINK_PARAMS(ln, tc_port) \ argument
27 #define MG_TX2_LINK_PARAMS(ln, tc_port) \ argument
37 #define MG_TX1_PISO_READLOAD(ln, tc_port) \ argument
46 #define MG_TX2_PISO_READLOAD(ln, tc_port) \ argument
56 #define MG_TX1_SWINGCTRL(ln, tc_port) \ argument
65 #define MG_TX2_SWINGCTRL(ln, tc_port) \ argument
80 #define MG_TX1_DRVCTRL(ln, tc_port) \ argument
89 #define MG_TX2_DRVCTRL(ln, tc_port) \ argument
105 #define MG_CLKHUB(ln, tc_port) \ argument
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| D | intel_dkl_phy.c | 25 enum tc_port tc_port = DKL_REG_TC_PORT(reg); in dkl_phy_set_hip_idx() local
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| D | intel_ddi.c | 1236 enum tc_port tc_port = intel_encoder_to_tc(encoder); in icl_mg_phy_set_signal_levels() local
1337 enum tc_port tc_port = intel_encoder_to_tc(encoder); in tgl_dkl_phy_set_signal_levels() local
1776 enum tc_port tc_port = intel_encoder_to_tc(encoder); in icl_ddi_tc_enable_clock() local
1796 enum tc_port tc_port = intel_encoder_to_tc(encoder); in icl_ddi_tc_disable_clock() local
1812 enum tc_port tc_port = intel_encoder_to_tc(encoder); in icl_ddi_tc_is_clock_enabled() local
1829 enum tc_port tc_port = intel_encoder_to_tc(encoder); in icl_ddi_tc_get_pll() local
2095 enum tc_port tc_port = intel_encoder_to_tc(&dig_port->base); in icl_program_mg_dp_mode() local
3545 enum tc_port tc_port = intel_encoder_to_tc(encoder); in adlp_tbt_to_dp_alt_switch_wa() local
4807 #define tc_port_name(tc_port) ((tc_port) - TC_PORT_1 + '1') argument
4955 enum tc_port tc_port = intel_port_to_tc(dev_priv, port); in intel_ddi_init() local
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| D | intel_tc.c | 253 enum tc_port tc_port = intel_encoder_to_tc(&tc->dig_port->base); in tc_port_power_domain() local
300 enum tc_port tc_port = intel_encoder_to_tc(&dig_port->base); in lnl_tc_port_get_max_lane_count() local
458 enum tc_port tc_port = intel_encoder_to_tc(&tc->dig_port->base); in tc_phy_load_fia_params() local
810 enum tc_port tc_port = intel_encoder_to_tc(&tc->dig_port->base); in adlp_tc_phy_is_ready() local
1854 enum tc_port tc_port = intel_encoder_to_tc(&dig_port->base); in intel_tc_port_init() local
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| D | intel_dpll_mgr.c | 195 enum intel_dpll_id icl_tc_port_to_pll_id(enum tc_port tc_port) in icl_tc_port_to_pll_id()
218 enum tc_port tc_port = icl_pll_id_to_tc_port(id); in intel_tc_pll_enable_reg() local
3541 enum tc_port tc_port = icl_pll_id_to_tc_port(id); in mg_pll_get_hw_state() local
3608 enum tc_port tc_port = icl_pll_id_to_tc_port(id); in dkl_pll_get_hw_state() local
3797 enum tc_port tc_port = icl_pll_id_to_tc_port(pll->info->id); in icl_mg_pll_write() local
3840 enum tc_port tc_port = icl_pll_id_to_tc_port(pll->info->id); in dkl_pll_write() local
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| D | intel_display.h | 153 enum tc_port { enum
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| D | intel_display_power_well.c | 533 enum tc_port tc_port; in icl_tc_phy_aux_power_well_enable() local
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| /linux-6.12.1/drivers/gpu/drm/i915/ |
| D | i915_reg.h | 4161 #define ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) < TC_PORT_4 ? \ argument
4238 #define MG_PLL_ENABLE(tc_port) _MMIO_PORT((tc_port), _MG_PLL1_ENABLE, \ argument
4250 #define ADLP_PORTTC_PLL_ENABLE(tc_port) _MMIO_PORT((tc_port), \ argument
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