1  /*
2   * Copyright (c) 2013-2014, 2016-2019 The Linux Foundation. All rights reserved.
3   *
4   * Permission to use, copy, modify, and/or distribute this software for
5   * any purpose with or without fee is hereby granted, provided that the
6   * above copyright notice and this permission notice appear in all
7   * copies.
8   *
9   * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
10   * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
11   * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
12   * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
13   * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
14   * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
15   * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
16   * PERFORMANCE OF THIS SOFTWARE.
17   */
18  
19  #ifndef _HIF_SDIO_INTERNAL_H_
20  #define _HIF_SDIO_INTERNAL_H_
21  
22  #include "a_debug.h"
23  #include "hif_sdio_dev.h"
24  #include "htc_packet.h"
25  #include "htc_api.h"
26  #include "hif_internal.h"
27  
28  #if defined(CONFIG_SDIO_TRANSFER_MAILBOX)
29  #include <transfer/mailbox.h>
30  #elif defined(CONFIG_SDIO_TRANSFER_ADMA)
31  #include <transfer/adma.h>
32  #else
33  #error "Error - Invalid transfer method"
34  #endif
35  
36  #define INVALID_MAILBOX_NUMBER 0xFF
37  
38  #define HIF_SDIO_RX_BUFFER_SIZE            1792
39  #define HIF_SDIO_RX_DATA_OFFSET            64
40  
41  /* TODO: print output level and mask control */
42  #define ATH_DEBUG_IRQ  ATH_DEBUG_MAKE_MODULE_MASK(4)
43  #define ATH_DEBUG_XMIT ATH_DEBUG_MAKE_MODULE_MASK(5)
44  #define ATH_DEBUG_RECV ATH_DEBUG_MAKE_MODULE_MASK(6)
45  
46  #define ATH_DEBUG_MAX_MASK 32
47  
48  #define SDIO_NUM_DATA_RX_BUFFERS  64
49  #define SDIO_DATA_RX_SIZE         1664
50  
51  struct hif_sdio_device {
52  	struct hif_sdio_dev *HIFDevice;
53  	qdf_spinlock_t Lock;
54  	qdf_spinlock_t TxLock;
55  	qdf_spinlock_t RxLock;
56  	struct hif_msg_callbacks hif_callbacks;
57  	uint32_t BlockSize;
58  	uint32_t BlockMask;
59  	enum hif_device_irq_mode HifIRQProcessingMode;
60  	struct hif_device_irq_yield_params HifIRQYieldParams;
61  	bool DSRCanYield;
62  	HIF_MASK_UNMASK_RECV_EVENT HifMaskUmaskRecvEvent;
63  	int CurrentDSRRecvCount;
64  	int RecheckIRQStatusCnt;
65  	uint32_t RecvStateFlags;
66  	void *pTarget;
67  	struct devRegisters devRegisters;
68  #ifdef CONFIG_SDIO_TRANSFER_MAILBOX
69  	bool swap_mailbox;
70  	struct hif_device_mbox_info MailBoxInfo;
71  #endif
72  };
73  
74  #define LOCK_HIF_DEV(device)    qdf_spin_lock(&(device)->Lock)
75  #define UNLOCK_HIF_DEV(device)  qdf_spin_unlock(&(device)->Lock)
76  #define LOCK_HIF_DEV_RX(t)      qdf_spin_lock(&(t)->RxLock)
77  #define UNLOCK_HIF_DEV_RX(t)    qdf_spin_unlock(&(t)->RxLock)
78  #define LOCK_HIF_DEV_TX(t)      qdf_spin_lock(&(t)->TxLock)
79  #define UNLOCK_HIF_DEV_TX(t)    qdf_spin_unlock(&(t)->TxLock)
80  
81  #define DEV_CALC_RECV_PADDED_LEN(pDev, length) \
82  		(((length) + (pDev)->BlockMask) & (~((pDev)->BlockMask)))
83  #define DEV_CALC_SEND_PADDED_LEN(pDev, length) \
84  		DEV_CALC_RECV_PADDED_LEN(pDev, length)
85  #define DEV_IS_LEN_BLOCK_ALIGNED(pDev, length) \
86  		(((length) % (pDev)->BlockSize) == 0)
87  
88  #define HTC_RECV_WAIT_BUFFERS        (1 << 0)
89  #define HTC_OP_STATE_STOPPING        (1 << 0)
90  
91  #define HTC_RX_PKT_IGNORE_LOOKAHEAD      (1 << 0)
92  #define HTC_RX_PKT_REFRESH_HDR           (1 << 1)
93  #define HTC_RX_PKT_PART_OF_BUNDLE        (1 << 2)
94  #define HTC_RX_PKT_NO_RECYCLE            (1 << 3)
95  #define HTC_RX_PKT_LAST_BUNDLED_PKT_HAS_ADDTIONAL_BLOCK     (1 << 4)
96  
97  #define IS_DEV_IRQ_PROCESSING_ASYNC_ALLOWED(pDev) \
98  		((pDev)->HifIRQProcessingMode != HIF_DEVICE_IRQ_SYNC_ONLY)
99  
100  /* hif_sdio_dev.c */
101  HTC_PACKET *hif_dev_alloc_rx_buffer(struct hif_sdio_device *pDev);
102  
103  /* hif_sdio_recv.c */
104  QDF_STATUS hif_dev_rw_completion_handler(void *context, QDF_STATUS status);
105  QDF_STATUS hif_dev_dsr_handler(void *context);
106  
107  #endif /* _HIF_SDIO_INTERNAL_H_ */
108