1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * stf_isp_hw_ops.c
4 *
5 * Register interface file for StarFive ISP driver
6 *
7 * Copyright (C) 2021-2023 StarFive Technology Co., Ltd.
8 *
9 */
10
11 #include "stf-camss.h"
12
stf_isp_config_obc(struct stfcamss * stfcamss)13 static void stf_isp_config_obc(struct stfcamss *stfcamss)
14 {
15 u32 reg_val, reg_add;
16
17 stf_isp_reg_write(stfcamss, ISP_REG_OBC_CFG, OBC_W_H(11) | OBC_W_W(11));
18
19 reg_val = GAIN_D_POINT(0x40) | GAIN_C_POINT(0x40) |
20 GAIN_B_POINT(0x40) | GAIN_A_POINT(0x40);
21 for (reg_add = ISP_REG_OBCG_CFG_0; reg_add <= ISP_REG_OBCG_CFG_3;) {
22 stf_isp_reg_write(stfcamss, reg_add, reg_val);
23 reg_add += 4;
24 }
25
26 reg_val = OFFSET_D_POINT(0) | OFFSET_C_POINT(0) |
27 OFFSET_B_POINT(0) | OFFSET_A_POINT(0);
28 for (reg_add = ISP_REG_OBCO_CFG_0; reg_add <= ISP_REG_OBCO_CFG_3;) {
29 stf_isp_reg_write(stfcamss, reg_add, reg_val);
30 reg_add += 4;
31 }
32 }
33
stf_isp_config_oecf(struct stfcamss * stfcamss)34 static void stf_isp_config_oecf(struct stfcamss *stfcamss)
35 {
36 u32 reg_add, par_val;
37 u16 par_h, par_l;
38
39 par_h = 0x10; par_l = 0;
40 par_val = OCEF_PAR_H(par_h) | OCEF_PAR_L(par_l);
41 for (reg_add = ISP_REG_OECF_X0_CFG0; reg_add <= ISP_REG_OECF_Y3_CFG0;) {
42 stf_isp_reg_write(stfcamss, reg_add, par_val);
43 reg_add += 0x20;
44 }
45
46 par_h = 0x40; par_l = 0x20;
47 par_val = OCEF_PAR_H(par_h) | OCEF_PAR_L(par_l);
48 for (reg_add = ISP_REG_OECF_X0_CFG1; reg_add <= ISP_REG_OECF_Y3_CFG1;) {
49 stf_isp_reg_write(stfcamss, reg_add, par_val);
50 reg_add += 0x20;
51 }
52
53 par_h = 0x80; par_l = 0x60;
54 par_val = OCEF_PAR_H(par_h) | OCEF_PAR_L(par_l);
55 for (reg_add = ISP_REG_OECF_X0_CFG2; reg_add <= ISP_REG_OECF_Y3_CFG2;) {
56 stf_isp_reg_write(stfcamss, reg_add, par_val);
57 reg_add += 0x20;
58 }
59
60 par_h = 0xc0; par_l = 0xa0;
61 par_val = OCEF_PAR_H(par_h) | OCEF_PAR_L(par_l);
62 for (reg_add = ISP_REG_OECF_X0_CFG3; reg_add <= ISP_REG_OECF_Y3_CFG3;) {
63 stf_isp_reg_write(stfcamss, reg_add, par_val);
64 reg_add += 0x20;
65 }
66
67 par_h = 0x100; par_l = 0xe0;
68 par_val = OCEF_PAR_H(par_h) | OCEF_PAR_L(par_l);
69 for (reg_add = ISP_REG_OECF_X0_CFG4; reg_add <= ISP_REG_OECF_Y3_CFG4;) {
70 stf_isp_reg_write(stfcamss, reg_add, par_val);
71 reg_add += 0x20;
72 }
73
74 par_h = 0x200; par_l = 0x180;
75 par_val = OCEF_PAR_H(par_h) | OCEF_PAR_L(par_l);
76 for (reg_add = ISP_REG_OECF_X0_CFG5; reg_add <= ISP_REG_OECF_Y3_CFG5;) {
77 stf_isp_reg_write(stfcamss, reg_add, par_val);
78 reg_add += 0x20;
79 }
80
81 par_h = 0x300; par_l = 0x280;
82 par_val = OCEF_PAR_H(par_h) | OCEF_PAR_L(par_l);
83 for (reg_add = ISP_REG_OECF_X0_CFG6; reg_add <= ISP_REG_OECF_Y3_CFG6;) {
84 stf_isp_reg_write(stfcamss, reg_add, par_val);
85 reg_add += 0x20;
86 }
87
88 par_h = 0x3fe; par_l = 0x380;
89 par_val = OCEF_PAR_H(par_h) | OCEF_PAR_L(par_l);
90 for (reg_add = ISP_REG_OECF_X0_CFG7; reg_add <= ISP_REG_OECF_Y3_CFG7;) {
91 stf_isp_reg_write(stfcamss, reg_add, par_val);
92 reg_add += 0x20;
93 }
94
95 par_h = 0x80; par_l = 0x80;
96 par_val = OCEF_PAR_H(par_h) | OCEF_PAR_L(par_l);
97 for (reg_add = ISP_REG_OECF_S0_CFG0; reg_add <= ISP_REG_OECF_S3_CFG7;) {
98 stf_isp_reg_write(stfcamss, reg_add, par_val);
99 reg_add += 4;
100 }
101 }
102
stf_isp_config_lccf(struct stfcamss * stfcamss)103 static void stf_isp_config_lccf(struct stfcamss *stfcamss)
104 {
105 u32 reg_add;
106
107 stf_isp_reg_write(stfcamss, ISP_REG_LCCF_CFG_0,
108 Y_DISTANCE(0x21C) | X_DISTANCE(0x3C0));
109 stf_isp_reg_write(stfcamss, ISP_REG_LCCF_CFG_1, LCCF_MAX_DIS(0xb));
110
111 for (reg_add = ISP_REG_LCCF_CFG_2; reg_add <= ISP_REG_LCCF_CFG_5;) {
112 stf_isp_reg_write(stfcamss, reg_add,
113 LCCF_F2_PAR(0x0) | LCCF_F1_PAR(0x0));
114 reg_add += 4;
115 }
116 }
117
stf_isp_config_awb(struct stfcamss * stfcamss)118 static void stf_isp_config_awb(struct stfcamss *stfcamss)
119 {
120 u32 reg_val, reg_add;
121 u16 symbol_h, symbol_l;
122
123 symbol_h = 0x0; symbol_l = 0x0;
124 reg_val = AWB_X_SYMBOL_H(symbol_h) | AWB_X_SYMBOL_L(symbol_l);
125
126 for (reg_add = ISP_REG_AWB_X0_CFG_0; reg_add <= ISP_REG_AWB_X3_CFG_1;) {
127 stf_isp_reg_write(stfcamss, reg_add, reg_val);
128 reg_add += 4;
129 }
130
131 symbol_h = 0x0, symbol_l = 0x0;
132 reg_val = AWB_Y_SYMBOL_H(symbol_h) | AWB_Y_SYMBOL_L(symbol_l);
133
134 for (reg_add = ISP_REG_AWB_Y0_CFG_0; reg_add <= ISP_REG_AWB_Y3_CFG_1;) {
135 stf_isp_reg_write(stfcamss, reg_add, reg_val);
136 reg_add += 4;
137 }
138
139 symbol_h = 0x80, symbol_l = 0x80;
140 reg_val = AWB_S_SYMBOL_H(symbol_h) | AWB_S_SYMBOL_L(symbol_l);
141
142 for (reg_add = ISP_REG_AWB_S0_CFG_0; reg_add <= ISP_REG_AWB_S3_CFG_1;) {
143 stf_isp_reg_write(stfcamss, reg_add, reg_val);
144 reg_add += 4;
145 }
146 }
147
stf_isp_config_grgb(struct stfcamss * stfcamss)148 static void stf_isp_config_grgb(struct stfcamss *stfcamss)
149 {
150 stf_isp_reg_write(stfcamss, ISP_REG_ICTC,
151 GF_MODE(1) | MAXGT(0x140) | MINGT(0x40));
152 stf_isp_reg_write(stfcamss, ISP_REG_IDBC, BADGT(0x200) | BADXT(0x200));
153 }
154
stf_isp_config_cfa(struct stfcamss * stfcamss)155 static void stf_isp_config_cfa(struct stfcamss *stfcamss)
156 {
157 stf_isp_reg_write(stfcamss, ISP_REG_RAW_FORMAT_CFG,
158 SMY13(0) | SMY12(1) | SMY11(0) | SMY10(1) | SMY3(2) |
159 SMY2(3) | SMY1(2) | SMY0(3));
160 stf_isp_reg_write(stfcamss, ISP_REG_ICFAM, CROSS_COV(3) | HV_W(2));
161 }
162
stf_isp_config_ccm(struct stfcamss * stfcamss)163 static void stf_isp_config_ccm(struct stfcamss *stfcamss)
164 {
165 u32 reg_add;
166
167 stf_isp_reg_write(stfcamss, ISP_REG_ICAMD_0, DNRM_F(6) | CCM_M_DAT(0));
168
169 for (reg_add = ISP_REG_ICAMD_12; reg_add <= ISP_REG_ICAMD_20;) {
170 stf_isp_reg_write(stfcamss, reg_add, CCM_M_DAT(0x80));
171 reg_add += 0x10;
172 }
173
174 stf_isp_reg_write(stfcamss, ISP_REG_ICAMD_24, CCM_M_DAT(0x700));
175 stf_isp_reg_write(stfcamss, ISP_REG_ICAMD_25, CCM_M_DAT(0x200));
176 }
177
stf_isp_config_gamma(struct stfcamss * stfcamss)178 static void stf_isp_config_gamma(struct stfcamss *stfcamss)
179 {
180 u32 reg_val, reg_add;
181 u16 gamma_slope_v, gamma_v;
182
183 gamma_slope_v = 0x2400; gamma_v = 0x0;
184 reg_val = GAMMA_S_VAL(gamma_slope_v) | GAMMA_VAL(gamma_v);
185 stf_isp_reg_write(stfcamss, ISP_REG_GAMMA_VAL0, reg_val);
186
187 gamma_slope_v = 0x800; gamma_v = 0x20;
188 for (reg_add = ISP_REG_GAMMA_VAL1; reg_add <= ISP_REG_GAMMA_VAL7;) {
189 reg_val = GAMMA_S_VAL(gamma_slope_v) | GAMMA_VAL(gamma_v);
190 stf_isp_reg_write(stfcamss, reg_add, reg_val);
191 reg_add += 4;
192 gamma_v += 0x20;
193 }
194
195 gamma_v = 0x100;
196 for (reg_add = ISP_REG_GAMMA_VAL8; reg_add <= ISP_REG_GAMMA_VAL13;) {
197 reg_val = GAMMA_S_VAL(gamma_slope_v) | GAMMA_VAL(gamma_v);
198 stf_isp_reg_write(stfcamss, reg_add, reg_val);
199 reg_add += 4;
200 gamma_v += 0x80;
201 }
202
203 gamma_v = 0x3fe;
204 reg_val = GAMMA_S_VAL(gamma_slope_v) | GAMMA_VAL(gamma_v);
205 stf_isp_reg_write(stfcamss, ISP_REG_GAMMA_VAL14, reg_val);
206 }
207
stf_isp_config_r2y(struct stfcamss * stfcamss)208 static void stf_isp_config_r2y(struct stfcamss *stfcamss)
209 {
210 stf_isp_reg_write(stfcamss, ISP_REG_R2Y_0, 0x4C);
211 stf_isp_reg_write(stfcamss, ISP_REG_R2Y_1, 0x97);
212 stf_isp_reg_write(stfcamss, ISP_REG_R2Y_2, 0x1d);
213 stf_isp_reg_write(stfcamss, ISP_REG_R2Y_3, 0x1d5);
214 stf_isp_reg_write(stfcamss, ISP_REG_R2Y_4, 0x1ac);
215 stf_isp_reg_write(stfcamss, ISP_REG_R2Y_5, 0x80);
216 stf_isp_reg_write(stfcamss, ISP_REG_R2Y_6, 0x80);
217 stf_isp_reg_write(stfcamss, ISP_REG_R2Y_7, 0x194);
218 stf_isp_reg_write(stfcamss, ISP_REG_R2Y_8, 0x1ec);
219 }
220
stf_isp_config_y_curve(struct stfcamss * stfcamss)221 static void stf_isp_config_y_curve(struct stfcamss *stfcamss)
222 {
223 u32 reg_add;
224 u16 y_curve;
225
226 y_curve = 0x0;
227 for (reg_add = ISP_REG_YCURVE_0; reg_add <= ISP_REG_YCURVE_63;) {
228 stf_isp_reg_write(stfcamss, reg_add, y_curve);
229 reg_add += 4;
230 y_curve += 0x10;
231 }
232 }
233
stf_isp_config_sharpen(struct stfcamss * sc)234 static void stf_isp_config_sharpen(struct stfcamss *sc)
235 {
236 u32 reg_add;
237
238 stf_isp_reg_write(sc, ISP_REG_SHARPEN0, S_DELTA(0x7) | S_WEIGHT(0xf));
239 stf_isp_reg_write(sc, ISP_REG_SHARPEN1, S_DELTA(0x18) | S_WEIGHT(0xf));
240 stf_isp_reg_write(sc, ISP_REG_SHARPEN2, S_DELTA(0x80) | S_WEIGHT(0xf));
241 stf_isp_reg_write(sc, ISP_REG_SHARPEN3, S_DELTA(0x100) | S_WEIGHT(0xf));
242 stf_isp_reg_write(sc, ISP_REG_SHARPEN4, S_DELTA(0x10) | S_WEIGHT(0xf));
243 stf_isp_reg_write(sc, ISP_REG_SHARPEN5, S_DELTA(0x60) | S_WEIGHT(0xf));
244 stf_isp_reg_write(sc, ISP_REG_SHARPEN6, S_DELTA(0x100) | S_WEIGHT(0xf));
245 stf_isp_reg_write(sc, ISP_REG_SHARPEN7, S_DELTA(0x190) | S_WEIGHT(0xf));
246 stf_isp_reg_write(sc, ISP_REG_SHARPEN8, S_DELTA(0x0) | S_WEIGHT(0xf));
247
248 for (reg_add = ISP_REG_SHARPEN9; reg_add <= ISP_REG_SHARPEN14;) {
249 stf_isp_reg_write(sc, reg_add, S_WEIGHT(0xf));
250 reg_add += 4;
251 }
252
253 for (reg_add = ISP_REG_SHARPEN_FS0; reg_add <= ISP_REG_SHARPEN_FS5;) {
254 stf_isp_reg_write(sc, reg_add, S_FACTOR(0x10) | S_SLOPE(0x0));
255 reg_add += 4;
256 }
257
258 stf_isp_reg_write(sc, ISP_REG_SHARPEN_WN,
259 PDIRF(0x8) | NDIRF(0x8) | WSUM(0xd7c));
260 stf_isp_reg_write(sc, ISP_REG_IUVS1, UVDIFF2(0xC0) | UVDIFF1(0x40));
261 stf_isp_reg_write(sc, ISP_REG_IUVS2, UVF(0xff) | UVSLOPE(0x0));
262 stf_isp_reg_write(sc, ISP_REG_IUVCKS1,
263 UVCKDIFF2(0xa0) | UVCKDIFF1(0x40));
264 }
265
stf_isp_config_dnyuv(struct stfcamss * stfcamss)266 static void stf_isp_config_dnyuv(struct stfcamss *stfcamss)
267 {
268 u32 reg_val;
269
270 reg_val = YUVSW5(7) | YUVSW4(7) | YUVSW3(7) | YUVSW2(7) |
271 YUVSW1(7) | YUVSW0(7);
272 stf_isp_reg_write(stfcamss, ISP_REG_DNYUV_YSWR0, reg_val);
273 stf_isp_reg_write(stfcamss, ISP_REG_DNYUV_CSWR0, reg_val);
274
275 reg_val = YUVSW3(7) | YUVSW2(7) | YUVSW1(7) | YUVSW0(7);
276 stf_isp_reg_write(stfcamss, ISP_REG_DNYUV_YSWR1, reg_val);
277 stf_isp_reg_write(stfcamss, ISP_REG_DNYUV_CSWR1, reg_val);
278
279 reg_val = CURVE_D_H(0x60) | CURVE_D_L(0x40);
280 stf_isp_reg_write(stfcamss, ISP_REG_DNYUV_YDR0, reg_val);
281 stf_isp_reg_write(stfcamss, ISP_REG_DNYUV_CDR0, reg_val);
282
283 reg_val = CURVE_D_H(0xd8) | CURVE_D_L(0x90);
284 stf_isp_reg_write(stfcamss, ISP_REG_DNYUV_YDR1, reg_val);
285 stf_isp_reg_write(stfcamss, ISP_REG_DNYUV_CDR1, reg_val);
286
287 reg_val = CURVE_D_H(0x1e6) | CURVE_D_L(0x144);
288 stf_isp_reg_write(stfcamss, ISP_REG_DNYUV_YDR2, reg_val);
289 stf_isp_reg_write(stfcamss, ISP_REG_DNYUV_CDR2, reg_val);
290 }
291
stf_isp_config_sat(struct stfcamss * stfcamss)292 static void stf_isp_config_sat(struct stfcamss *stfcamss)
293 {
294 stf_isp_reg_write(stfcamss, ISP_REG_CS_GAIN, CMAD(0x0) | CMAB(0x100));
295 stf_isp_reg_write(stfcamss, ISP_REG_CS_THRESHOLD, CMD(0x1f) | CMB(0x1));
296 stf_isp_reg_write(stfcamss, ISP_REG_CS_OFFSET, VOFF(0x0) | UOFF(0x0));
297 stf_isp_reg_write(stfcamss, ISP_REG_CS_HUE_F, SIN(0x0) | COS(0x100));
298 stf_isp_reg_write(stfcamss, ISP_REG_CS_SCALE, 0x8);
299 stf_isp_reg_write(stfcamss, ISP_REG_YADJ0, YOIR(0x401) | YIMIN(0x1));
300 stf_isp_reg_write(stfcamss, ISP_REG_YADJ1, YOMAX(0x3ff) | YOMIN(0x1));
301 }
302
stf_isp_reset(struct stf_isp_dev * isp_dev)303 int stf_isp_reset(struct stf_isp_dev *isp_dev)
304 {
305 stf_isp_reg_set_bit(isp_dev->stfcamss, ISP_REG_ISP_CTRL_0,
306 ISPC_RST_MASK, ISPC_RST);
307 stf_isp_reg_set_bit(isp_dev->stfcamss, ISP_REG_ISP_CTRL_0,
308 ISPC_RST_MASK, 0);
309
310 return 0;
311 }
312
stf_isp_init_cfg(struct stf_isp_dev * isp_dev)313 void stf_isp_init_cfg(struct stf_isp_dev *isp_dev)
314 {
315 stf_isp_reg_write(isp_dev->stfcamss, ISP_REG_DC_CFG_1, DC_AXI_ID(0x0));
316 stf_isp_reg_write(isp_dev->stfcamss, ISP_REG_DEC_CFG,
317 DEC_V_KEEP(0x0) |
318 DEC_V_PERIOD(0x0) |
319 DEC_H_KEEP(0x0) |
320 DEC_H_PERIOD(0x0));
321
322 stf_isp_config_obc(isp_dev->stfcamss);
323 stf_isp_config_oecf(isp_dev->stfcamss);
324 stf_isp_config_lccf(isp_dev->stfcamss);
325 stf_isp_config_awb(isp_dev->stfcamss);
326 stf_isp_config_grgb(isp_dev->stfcamss);
327 stf_isp_config_cfa(isp_dev->stfcamss);
328 stf_isp_config_ccm(isp_dev->stfcamss);
329 stf_isp_config_gamma(isp_dev->stfcamss);
330 stf_isp_config_r2y(isp_dev->stfcamss);
331 stf_isp_config_y_curve(isp_dev->stfcamss);
332 stf_isp_config_sharpen(isp_dev->stfcamss);
333 stf_isp_config_dnyuv(isp_dev->stfcamss);
334 stf_isp_config_sat(isp_dev->stfcamss);
335
336 stf_isp_reg_write(isp_dev->stfcamss, ISP_REG_CSI_MODULE_CFG,
337 CSI_DUMP_EN | CSI_SC_EN | CSI_AWB_EN |
338 CSI_LCCF_EN | CSI_OECF_EN | CSI_OBC_EN | CSI_DEC_EN);
339 stf_isp_reg_write(isp_dev->stfcamss, ISP_REG_ISP_CTRL_1,
340 CTRL_SAT(1) | CTRL_DBC | CTRL_CTC | CTRL_YHIST |
341 CTRL_YCURVE | CTRL_BIYUV | CTRL_SCE | CTRL_EE |
342 CTRL_CCE | CTRL_RGE | CTRL_CME | CTRL_AE | CTRL_CE);
343 }
344
stf_isp_config_crop(struct stfcamss * stfcamss,struct v4l2_rect * crop)345 static void stf_isp_config_crop(struct stfcamss *stfcamss,
346 struct v4l2_rect *crop)
347 {
348 u32 bpp = stfcamss->isp_dev.current_fmt->bpp;
349 u32 val;
350
351 val = VSTART_CAP(crop->top) | HSTART_CAP(crop->left);
352 stf_isp_reg_write(stfcamss, ISP_REG_PIC_CAPTURE_START_CFG, val);
353
354 val = VEND_CAP(crop->height + crop->top - 1) |
355 HEND_CAP(crop->width + crop->left - 1);
356 stf_isp_reg_write(stfcamss, ISP_REG_PIC_CAPTURE_END_CFG, val);
357
358 val = H_ACT_CAP(crop->height) | W_ACT_CAP(crop->width);
359 stf_isp_reg_write(stfcamss, ISP_REG_PIPELINE_XY_SIZE, val);
360
361 val = ALIGN(crop->width * bpp / 8, STFCAMSS_FRAME_WIDTH_ALIGN_8);
362 stf_isp_reg_write(stfcamss, ISP_REG_STRIDE, val);
363 }
364
stf_isp_config_raw_fmt(struct stfcamss * stfcamss,u32 mcode)365 static void stf_isp_config_raw_fmt(struct stfcamss *stfcamss, u32 mcode)
366 {
367 u32 val, val1;
368
369 switch (mcode) {
370 case MEDIA_BUS_FMT_SRGGB10_1X10:
371 case MEDIA_BUS_FMT_SRGGB8_1X8:
372 /* 3 2 3 2 1 0 1 0 B Gb B Gb Gr R Gr R */
373 val = SMY13(3) | SMY12(2) | SMY11(3) | SMY10(2) |
374 SMY3(1) | SMY2(0) | SMY1(1) | SMY0(0);
375 val1 = CTRL_SAT(0x0);
376 break;
377 case MEDIA_BUS_FMT_SGRBG10_1X10:
378 case MEDIA_BUS_FMT_SGRBG8_1X8:
379 /* 2 3 2 3 0 1 0 1, Gb B Gb B R Gr R Gr */
380 val = SMY13(2) | SMY12(3) | SMY11(2) | SMY10(3) |
381 SMY3(0) | SMY2(1) | SMY1(0) | SMY0(1);
382 val1 = CTRL_SAT(0x2);
383 break;
384 case MEDIA_BUS_FMT_SGBRG10_1X10:
385 case MEDIA_BUS_FMT_SGBRG8_1X8:
386 /* 1 0 1 0 3 2 3 2, Gr R Gr R B Gb B Gb */
387 val = SMY13(1) | SMY12(0) | SMY11(1) | SMY10(0) |
388 SMY3(3) | SMY2(2) | SMY1(3) | SMY0(2);
389 val1 = CTRL_SAT(0x3);
390 break;
391 case MEDIA_BUS_FMT_SBGGR10_1X10:
392 case MEDIA_BUS_FMT_SBGGR8_1X8:
393 /* 0 1 0 1 2 3 2 3 R Gr R Gr Gb B Gb B */
394 val = SMY13(0) | SMY12(1) | SMY11(0) | SMY10(1) |
395 SMY3(2) | SMY2(3) | SMY1(2) | SMY0(3);
396 val1 = CTRL_SAT(0x1);
397 break;
398 default:
399 val = SMY13(0) | SMY12(1) | SMY11(0) | SMY10(1) |
400 SMY3(2) | SMY2(3) | SMY1(2) | SMY0(3);
401 val1 = CTRL_SAT(0x1);
402 break;
403 }
404 stf_isp_reg_write(stfcamss, ISP_REG_RAW_FORMAT_CFG, val);
405 stf_isp_reg_set_bit(stfcamss, ISP_REG_ISP_CTRL_1, CTRL_SAT_MASK, val1);
406 }
407
stf_isp_settings(struct stf_isp_dev * isp_dev,struct v4l2_rect * crop,u32 mcode)408 void stf_isp_settings(struct stf_isp_dev *isp_dev,
409 struct v4l2_rect *crop, u32 mcode)
410 {
411 struct stfcamss *stfcamss = isp_dev->stfcamss;
412
413 stf_isp_config_crop(stfcamss, crop);
414 stf_isp_config_raw_fmt(stfcamss, mcode);
415
416 stf_isp_reg_set_bit(stfcamss, ISP_REG_DUMP_CFG_1,
417 DUMP_BURST_LEN_MASK | DUMP_SD_MASK,
418 DUMP_BURST_LEN(3));
419
420 stf_isp_reg_write(stfcamss, ISP_REG_ITIIWSR,
421 ITI_HSIZE(IMAGE_MAX_HEIGH) |
422 ITI_WSIZE(IMAGE_MAX_WIDTH));
423 stf_isp_reg_write(stfcamss, ISP_REG_ITIDWLSR, 0x960);
424 stf_isp_reg_write(stfcamss, ISP_REG_ITIDRLSR, 0x960);
425 stf_isp_reg_write(stfcamss, ISP_REG_SENSOR, IMAGER_SEL(1));
426 }
427
stf_isp_stream_set(struct stf_isp_dev * isp_dev)428 void stf_isp_stream_set(struct stf_isp_dev *isp_dev)
429 {
430 struct stfcamss *stfcamss = isp_dev->stfcamss;
431
432 stf_isp_reg_write_delay(stfcamss, ISP_REG_ISP_CTRL_0,
433 ISPC_ENUO | ISPC_ENLS | ISPC_RST, 10);
434 stf_isp_reg_write_delay(stfcamss, ISP_REG_ISP_CTRL_0,
435 ISPC_ENUO | ISPC_ENLS, 10);
436 stf_isp_reg_write(stfcamss, ISP_REG_IESHD, SHAD_UP_M);
437 stf_isp_reg_write_delay(stfcamss, ISP_REG_ISP_CTRL_0,
438 ISPC_ENUO | ISPC_ENLS | ISPC_EN, 10);
439 stf_isp_reg_write_delay(stfcamss, ISP_REG_CSIINTS,
440 CSI_INTS(1) | CSI_SHA_M(4), 10);
441 stf_isp_reg_write_delay(stfcamss, ISP_REG_CSIINTS,
442 CSI_INTS(2) | CSI_SHA_M(4), 10);
443 stf_isp_reg_write_delay(stfcamss, ISP_REG_CSI_INPUT_EN_AND_STATUS,
444 CSI_EN_S, 10);
445 }
446