1 /*
2 * Copyright 2023 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #define SWSMU_CODE_LAYER_L2
25
26 #include <linux/firmware.h>
27 #include <linux/pci.h>
28 #include <linux/i2c.h>
29 #include "amdgpu.h"
30 #include "amdgpu_smu.h"
31 #include "atomfirmware.h"
32 #include "amdgpu_atomfirmware.h"
33 #include "amdgpu_atombios.h"
34 #include "smu_v14_0.h"
35 #include "smu14_driver_if_v14_0.h"
36 #include "soc15_common.h"
37 #include "atom.h"
38 #include "smu_v14_0_2_ppt.h"
39 #include "smu_v14_0_2_pptable.h"
40 #include "smu_v14_0_2_ppsmc.h"
41 #include "mp/mp_14_0_2_offset.h"
42 #include "mp/mp_14_0_2_sh_mask.h"
43
44 #include "smu_cmn.h"
45 #include "amdgpu_ras.h"
46
47 /*
48 * DO NOT use these for err/warn/info/debug messages.
49 * Use dev_err, dev_warn, dev_info and dev_dbg instead.
50 * They are more MGPU friendly.
51 */
52 #undef pr_err
53 #undef pr_warn
54 #undef pr_info
55 #undef pr_debug
56
57 #define to_amdgpu_device(x) (container_of(x, struct amdgpu_device, pm.smu_i2c))
58
59 #define FEATURE_MASK(feature) (1ULL << feature)
60 #define SMC_DPM_FEATURE ( \
61 FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT) | \
62 FEATURE_MASK(FEATURE_DPM_UCLK_BIT) | \
63 FEATURE_MASK(FEATURE_DPM_LINK_BIT) | \
64 FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT) | \
65 FEATURE_MASK(FEATURE_DPM_FCLK_BIT))
66
67 #define MP0_MP1_DATA_REGION_SIZE_COMBOPPTABLE 0x4000
68 #define DEBUGSMC_MSG_Mode1Reset 2
69 #define LINK_SPEED_MAX 3
70
71 #define PP_OD_FEATURE_GFXCLK_FMIN 0
72 #define PP_OD_FEATURE_GFXCLK_FMAX 1
73 #define PP_OD_FEATURE_UCLK_FMIN 2
74 #define PP_OD_FEATURE_UCLK_FMAX 3
75 #define PP_OD_FEATURE_GFX_VF_CURVE 4
76 #define PP_OD_FEATURE_FAN_CURVE_TEMP 5
77 #define PP_OD_FEATURE_FAN_CURVE_PWM 6
78 #define PP_OD_FEATURE_FAN_ACOUSTIC_LIMIT 7
79 #define PP_OD_FEATURE_FAN_ACOUSTIC_TARGET 8
80 #define PP_OD_FEATURE_FAN_TARGET_TEMPERATURE 9
81 #define PP_OD_FEATURE_FAN_MINIMUM_PWM 10
82
83 static struct cmn2asic_msg_mapping smu_v14_0_2_message_map[SMU_MSG_MAX_COUNT] = {
84 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 1),
85 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1),
86 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1),
87 MSG_MAP(SetAllowedFeaturesMaskLow, PPSMC_MSG_SetAllowedFeaturesMaskLow, 0),
88 MSG_MAP(SetAllowedFeaturesMaskHigh, PPSMC_MSG_SetAllowedFeaturesMaskHigh, 0),
89 MSG_MAP(EnableAllSmuFeatures, PPSMC_MSG_EnableAllSmuFeatures, 0),
90 MSG_MAP(DisableAllSmuFeatures, PPSMC_MSG_DisableAllSmuFeatures, 0),
91 MSG_MAP(EnableSmuFeaturesLow, PPSMC_MSG_EnableSmuFeaturesLow, 1),
92 MSG_MAP(EnableSmuFeaturesHigh, PPSMC_MSG_EnableSmuFeaturesHigh, 1),
93 MSG_MAP(DisableSmuFeaturesLow, PPSMC_MSG_DisableSmuFeaturesLow, 1),
94 MSG_MAP(DisableSmuFeaturesHigh, PPSMC_MSG_DisableSmuFeaturesHigh, 1),
95 MSG_MAP(GetEnabledSmuFeaturesLow, PPSMC_MSG_GetRunningSmuFeaturesLow, 1),
96 MSG_MAP(GetEnabledSmuFeaturesHigh, PPSMC_MSG_GetRunningSmuFeaturesHigh, 1),
97 MSG_MAP(SetWorkloadMask, PPSMC_MSG_SetWorkloadMask, 1),
98 MSG_MAP(SetPptLimit, PPSMC_MSG_SetPptLimit, 0),
99 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 1),
100 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 1),
101 MSG_MAP(SetToolsDramAddrHigh, PPSMC_MSG_SetToolsDramAddrHigh, 0),
102 MSG_MAP(SetToolsDramAddrLow, PPSMC_MSG_SetToolsDramAddrLow, 0),
103 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 1),
104 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 0),
105 MSG_MAP(UseDefaultPPTable, PPSMC_MSG_UseDefaultPPTable, 0),
106 MSG_MAP(RunDcBtc, PPSMC_MSG_RunDcBtc, 0),
107 MSG_MAP(EnterBaco, PPSMC_MSG_EnterBaco, 0),
108 MSG_MAP(ExitBaco, PPSMC_MSG_ExitBaco, 0),
109 MSG_MAP(SetSoftMinByFreq, PPSMC_MSG_SetSoftMinByFreq, 1),
110 MSG_MAP(SetSoftMaxByFreq, PPSMC_MSG_SetSoftMaxByFreq, 1),
111 MSG_MAP(SetHardMinByFreq, PPSMC_MSG_SetHardMinByFreq, 1),
112 MSG_MAP(SetHardMaxByFreq, PPSMC_MSG_SetHardMaxByFreq, 0),
113 MSG_MAP(GetMinDpmFreq, PPSMC_MSG_GetMinDpmFreq, 1),
114 MSG_MAP(GetMaxDpmFreq, PPSMC_MSG_GetMaxDpmFreq, 1),
115 MSG_MAP(GetDpmFreqByIndex, PPSMC_MSG_GetDpmFreqByIndex, 1),
116 MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn, 0),
117 MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn, 0),
118 MSG_MAP(PowerUpJpeg, PPSMC_MSG_PowerUpJpeg, 0),
119 MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg, 0),
120 MSG_MAP(GetDcModeMaxDpmFreq, PPSMC_MSG_GetDcModeMaxDpmFreq, 1),
121 MSG_MAP(OverridePcieParameters, PPSMC_MSG_OverridePcieParameters, 0),
122 MSG_MAP(DramLogSetDramAddrHigh, PPSMC_MSG_DramLogSetDramAddrHigh, 0),
123 MSG_MAP(DramLogSetDramAddrLow, PPSMC_MSG_DramLogSetDramAddrLow, 0),
124 MSG_MAP(DramLogSetDramSize, PPSMC_MSG_DramLogSetDramSize, 0),
125 MSG_MAP(AllowGfxOff, PPSMC_MSG_AllowGfxOff, 0),
126 MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisallowGfxOff, 0),
127 MSG_MAP(SetMGpuFanBoostLimitRpm, PPSMC_MSG_SetMGpuFanBoostLimitRpm, 0),
128 MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit, 0),
129 MSG_MAP(NotifyPowerSource, PPSMC_MSG_NotifyPowerSource, 0),
130 MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload, 0),
131 MSG_MAP(DFCstateControl, PPSMC_MSG_SetExternalClientDfCstateAllow, 0),
132 MSG_MAP(ArmD3, PPSMC_MSG_ArmD3, 0),
133 MSG_MAP(SetNumBadMemoryPagesRetired, PPSMC_MSG_SetNumBadMemoryPagesRetired, 0),
134 MSG_MAP(SetBadMemoryPagesRetiredFlagsPerChannel,
135 PPSMC_MSG_SetBadMemoryPagesRetiredFlagsPerChannel, 0),
136 MSG_MAP(AllowIHHostInterrupt, PPSMC_MSG_AllowIHHostInterrupt, 0),
137 MSG_MAP(ReenableAcDcInterrupt, PPSMC_MSG_ReenableAcDcInterrupt, 0),
138 };
139
140 static struct cmn2asic_mapping smu_v14_0_2_clk_map[SMU_CLK_COUNT] = {
141 CLK_MAP(GFXCLK, PPCLK_GFXCLK),
142 CLK_MAP(SCLK, PPCLK_GFXCLK),
143 CLK_MAP(SOCCLK, PPCLK_SOCCLK),
144 CLK_MAP(FCLK, PPCLK_FCLK),
145 CLK_MAP(UCLK, PPCLK_UCLK),
146 CLK_MAP(MCLK, PPCLK_UCLK),
147 CLK_MAP(VCLK, PPCLK_VCLK_0),
148 CLK_MAP(DCLK, PPCLK_DCLK_0),
149 CLK_MAP(DCEFCLK, PPCLK_DCFCLK),
150 };
151
152 static struct cmn2asic_mapping smu_v14_0_2_feature_mask_map[SMU_FEATURE_COUNT] = {
153 FEA_MAP(FW_DATA_READ),
154 FEA_MAP(DPM_GFXCLK),
155 FEA_MAP(DPM_GFX_POWER_OPTIMIZER),
156 FEA_MAP(DPM_UCLK),
157 FEA_MAP(DPM_FCLK),
158 FEA_MAP(DPM_SOCCLK),
159 FEA_MAP(DPM_LINK),
160 FEA_MAP(DPM_DCN),
161 FEA_MAP(VMEMP_SCALING),
162 FEA_MAP(VDDIO_MEM_SCALING),
163 FEA_MAP(DS_GFXCLK),
164 FEA_MAP(DS_SOCCLK),
165 FEA_MAP(DS_FCLK),
166 FEA_MAP(DS_LCLK),
167 FEA_MAP(DS_DCFCLK),
168 FEA_MAP(DS_UCLK),
169 FEA_MAP(GFX_ULV),
170 FEA_MAP(FW_DSTATE),
171 FEA_MAP(GFXOFF),
172 FEA_MAP(BACO),
173 FEA_MAP(MM_DPM),
174 FEA_MAP(SOC_MPCLK_DS),
175 FEA_MAP(BACO_MPCLK_DS),
176 FEA_MAP(THROTTLERS),
177 FEA_MAP(SMARTSHIFT),
178 FEA_MAP(GTHR),
179 FEA_MAP(ACDC),
180 FEA_MAP(VR0HOT),
181 FEA_MAP(FW_CTF),
182 FEA_MAP(FAN_CONTROL),
183 FEA_MAP(GFX_DCS),
184 FEA_MAP(GFX_READ_MARGIN),
185 FEA_MAP(LED_DISPLAY),
186 FEA_MAP(GFXCLK_SPREAD_SPECTRUM),
187 FEA_MAP(OUT_OF_BAND_MONITOR),
188 FEA_MAP(OPTIMIZED_VMIN),
189 FEA_MAP(GFX_IMU),
190 FEA_MAP(BOOT_TIME_CAL),
191 FEA_MAP(GFX_PCC_DFLL),
192 FEA_MAP(SOC_CG),
193 FEA_MAP(DF_CSTATE),
194 FEA_MAP(GFX_EDC),
195 FEA_MAP(BOOT_POWER_OPT),
196 FEA_MAP(CLOCK_POWER_DOWN_BYPASS),
197 FEA_MAP(DS_VCN),
198 FEA_MAP(BACO_CG),
199 FEA_MAP(MEM_TEMP_READ),
200 FEA_MAP(ATHUB_MMHUB_PG),
201 FEA_MAP(SOC_PCC),
202 FEA_MAP(EDC_PWRBRK),
203 FEA_MAP(SOC_EDC_XVMIN),
204 FEA_MAP(GFX_PSM_DIDT),
205 FEA_MAP(APT_ALL_ENABLE),
206 FEA_MAP(APT_SQ_THROTTLE),
207 FEA_MAP(APT_PF_DCS),
208 FEA_MAP(GFX_EDC_XVMIN),
209 FEA_MAP(GFX_DIDT_XVMIN),
210 FEA_MAP(FAN_ABNORMAL),
211 [SMU_FEATURE_DPM_VCLK_BIT] = {1, FEATURE_MM_DPM_BIT},
212 [SMU_FEATURE_DPM_DCLK_BIT] = {1, FEATURE_MM_DPM_BIT},
213 [SMU_FEATURE_PPT_BIT] = {1, FEATURE_THROTTLERS_BIT},
214 };
215
216 static struct cmn2asic_mapping smu_v14_0_2_table_map[SMU_TABLE_COUNT] = {
217 TAB_MAP(PPTABLE),
218 TAB_MAP(WATERMARKS),
219 TAB_MAP(AVFS_PSM_DEBUG),
220 TAB_MAP(PMSTATUSLOG),
221 TAB_MAP(SMU_METRICS),
222 TAB_MAP(DRIVER_SMU_CONFIG),
223 TAB_MAP(ACTIVITY_MONITOR_COEFF),
224 [SMU_TABLE_COMBO_PPTABLE] = {1, TABLE_COMBO_PPTABLE},
225 TAB_MAP(I2C_COMMANDS),
226 TAB_MAP(ECCINFO),
227 TAB_MAP(OVERDRIVE),
228 };
229
230 static struct cmn2asic_mapping smu_v14_0_2_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
231 PWR_MAP(AC),
232 PWR_MAP(DC),
233 };
234
235 static struct cmn2asic_mapping smu_v14_0_2_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
236 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT, WORKLOAD_PPLIB_DEFAULT_BIT),
237 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D, WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
238 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING, WORKLOAD_PPLIB_POWER_SAVING_BIT),
239 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT),
240 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR, WORKLOAD_PPLIB_VR_BIT),
241 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_COMPUTE_BIT),
242 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT),
243 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_WINDOW3D, WORKLOAD_PPLIB_WINDOW_3D_BIT),
244 };
245
246 static const uint8_t smu_v14_0_2_throttler_map[] = {
247 [THROTTLER_PPT0_BIT] = (SMU_THROTTLER_PPT0_BIT),
248 [THROTTLER_PPT1_BIT] = (SMU_THROTTLER_PPT1_BIT),
249 [THROTTLER_PPT2_BIT] = (SMU_THROTTLER_PPT2_BIT),
250 [THROTTLER_PPT3_BIT] = (SMU_THROTTLER_PPT3_BIT),
251 [THROTTLER_TDC_GFX_BIT] = (SMU_THROTTLER_TDC_GFX_BIT),
252 [THROTTLER_TDC_SOC_BIT] = (SMU_THROTTLER_TDC_SOC_BIT),
253 [THROTTLER_TEMP_EDGE_BIT] = (SMU_THROTTLER_TEMP_EDGE_BIT),
254 [THROTTLER_TEMP_HOTSPOT_BIT] = (SMU_THROTTLER_TEMP_HOTSPOT_BIT),
255 [THROTTLER_TEMP_MEM_BIT] = (SMU_THROTTLER_TEMP_MEM_BIT),
256 [THROTTLER_TEMP_VR_GFX_BIT] = (SMU_THROTTLER_TEMP_VR_GFX_BIT),
257 [THROTTLER_TEMP_VR_SOC_BIT] = (SMU_THROTTLER_TEMP_VR_SOC_BIT),
258 [THROTTLER_TEMP_VR_MEM0_BIT] = (SMU_THROTTLER_TEMP_VR_MEM0_BIT),
259 [THROTTLER_TEMP_VR_MEM1_BIT] = (SMU_THROTTLER_TEMP_VR_MEM1_BIT),
260 [THROTTLER_TEMP_LIQUID0_BIT] = (SMU_THROTTLER_TEMP_LIQUID0_BIT),
261 [THROTTLER_TEMP_LIQUID1_BIT] = (SMU_THROTTLER_TEMP_LIQUID1_BIT),
262 [THROTTLER_GFX_APCC_PLUS_BIT] = (SMU_THROTTLER_APCC_BIT),
263 [THROTTLER_FIT_BIT] = (SMU_THROTTLER_FIT_BIT),
264 };
265
266 static int
smu_v14_0_2_get_allowed_feature_mask(struct smu_context * smu,uint32_t * feature_mask,uint32_t num)267 smu_v14_0_2_get_allowed_feature_mask(struct smu_context *smu,
268 uint32_t *feature_mask, uint32_t num)
269 {
270 struct amdgpu_device *adev = smu->adev;
271 /*u32 smu_version;*/
272
273 if (num > 2)
274 return -EINVAL;
275
276 memset(feature_mask, 0xff, sizeof(uint32_t) * num);
277
278 if (adev->pm.pp_feature & PP_SCLK_DPM_MASK) {
279 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT);
280 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_IMU_BIT);
281 }
282 #if 0
283 if (!(adev->pg_flags & AMD_PG_SUPPORT_ATHUB) ||
284 !(adev->pg_flags & AMD_PG_SUPPORT_MMHUB))
285 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_ATHUB_MMHUB_PG_BIT);
286
287 if (!(adev->pm.pp_feature & PP_SOCCLK_DPM_MASK))
288 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);
289
290 /* PMFW 78.58 contains a critical fix for gfxoff feature */
291 smu_cmn_get_smc_version(smu, NULL, &smu_version);
292 if ((smu_version < 0x004e3a00) ||
293 !(adev->pm.pp_feature & PP_GFXOFF_MASK))
294 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_GFXOFF_BIT);
295
296 if (!(adev->pm.pp_feature & PP_MCLK_DPM_MASK)) {
297 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DPM_UCLK_BIT);
298 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_VMEMP_SCALING_BIT);
299 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_VDDIO_MEM_SCALING_BIT);
300 }
301
302 if (!(adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK))
303 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DS_GFXCLK_BIT);
304
305 if (!(adev->pm.pp_feature & PP_PCIE_DPM_MASK)) {
306 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DPM_LINK_BIT);
307 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DS_LCLK_BIT);
308 }
309
310 if (!(adev->pm.pp_feature & PP_ULV_MASK))
311 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_GFX_ULV_BIT);
312 #endif
313
314 return 0;
315 }
316
smu_v14_0_2_check_powerplay_table(struct smu_context * smu)317 static int smu_v14_0_2_check_powerplay_table(struct smu_context *smu)
318 {
319 struct smu_table_context *table_context = &smu->smu_table;
320 struct smu_14_0_2_powerplay_table *powerplay_table =
321 table_context->power_play_table;
322 struct smu_baco_context *smu_baco = &smu->smu_baco;
323 PPTable_t *pptable = smu->smu_table.driver_pptable;
324 const OverDriveLimits_t * const overdrive_upperlimits =
325 &pptable->SkuTable.OverDriveLimitsBasicMax;
326 const OverDriveLimits_t * const overdrive_lowerlimits =
327 &pptable->SkuTable.OverDriveLimitsBasicMin;
328
329 if (powerplay_table->platform_caps & SMU_14_0_2_PP_PLATFORM_CAP_HARDWAREDC)
330 smu->dc_controlled_by_gpio = true;
331
332 if (powerplay_table->platform_caps & SMU_14_0_2_PP_PLATFORM_CAP_BACO) {
333 smu_baco->platform_support = true;
334
335 if (powerplay_table->platform_caps & SMU_14_0_2_PP_PLATFORM_CAP_MACO)
336 smu_baco->maco_support = true;
337 }
338
339 if (!overdrive_lowerlimits->FeatureCtrlMask ||
340 !overdrive_upperlimits->FeatureCtrlMask)
341 smu->od_enabled = false;
342
343 table_context->thermal_controller_type =
344 powerplay_table->thermal_controller_type;
345
346 /*
347 * Instead of having its own buffer space and get overdrive_table copied,
348 * smu->od_settings just points to the actual overdrive_table
349 */
350 smu->od_settings = &powerplay_table->overdrive_table;
351
352 smu->adev->pm.no_fan =
353 !(pptable->PFE_Settings.FeaturesToRun[0] & (1 << FEATURE_FAN_CONTROL_BIT));
354
355 return 0;
356 }
357
smu_v14_0_2_store_powerplay_table(struct smu_context * smu)358 static int smu_v14_0_2_store_powerplay_table(struct smu_context *smu)
359 {
360 struct smu_table_context *table_context = &smu->smu_table;
361 struct smu_14_0_2_powerplay_table *powerplay_table =
362 table_context->power_play_table;
363
364 memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,
365 sizeof(PPTable_t));
366
367 return 0;
368 }
369
smu_v14_0_2_get_pptable_from_pmfw(struct smu_context * smu,void ** table,uint32_t * size)370 static int smu_v14_0_2_get_pptable_from_pmfw(struct smu_context *smu,
371 void **table,
372 uint32_t *size)
373 {
374 struct smu_table_context *smu_table = &smu->smu_table;
375 void *combo_pptable = smu_table->combo_pptable;
376 int ret = 0;
377
378 ret = smu_cmn_get_combo_pptable(smu);
379 if (ret)
380 return ret;
381
382 *table = combo_pptable;
383 *size = sizeof(struct smu_14_0_2_powerplay_table);
384
385 return 0;
386 }
387
smu_v14_0_2_setup_pptable(struct smu_context * smu)388 static int smu_v14_0_2_setup_pptable(struct smu_context *smu)
389 {
390 struct smu_table_context *smu_table = &smu->smu_table;
391 int ret = 0;
392
393 if (amdgpu_sriov_vf(smu->adev))
394 return 0;
395
396 ret = smu_v14_0_2_get_pptable_from_pmfw(smu,
397 &smu_table->power_play_table,
398 &smu_table->power_play_table_size);
399 if (ret)
400 return ret;
401
402 ret = smu_v14_0_2_store_powerplay_table(smu);
403 if (ret)
404 return ret;
405
406 ret = smu_v14_0_2_check_powerplay_table(smu);
407 if (ret)
408 return ret;
409
410 return ret;
411 }
412
smu_v14_0_2_tables_init(struct smu_context * smu)413 static int smu_v14_0_2_tables_init(struct smu_context *smu)
414 {
415 struct smu_table_context *smu_table = &smu->smu_table;
416 struct smu_table *tables = smu_table->tables;
417
418 SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t),
419 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
420 SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
421 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
422 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetricsExternal_t),
423 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
424 SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t),
425 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
426 SMU_TABLE_INIT(tables, SMU_TABLE_OVERDRIVE, sizeof(OverDriveTable_t),
427 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
428 SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU14_TOOL_SIZE,
429 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
430 SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF,
431 sizeof(DpmActivityMonitorCoeffIntExternal_t), PAGE_SIZE,
432 AMDGPU_GEM_DOMAIN_VRAM);
433 SMU_TABLE_INIT(tables, SMU_TABLE_COMBO_PPTABLE, MP0_MP1_DATA_REGION_SIZE_COMBOPPTABLE,
434 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
435 SMU_TABLE_INIT(tables, SMU_TABLE_ECCINFO, sizeof(EccInfoTable_t),
436 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
437
438 smu_table->metrics_table = kzalloc(sizeof(SmuMetricsExternal_t), GFP_KERNEL);
439 if (!smu_table->metrics_table)
440 goto err0_out;
441 smu_table->metrics_time = 0;
442
443 smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_3);
444 smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
445 if (!smu_table->gpu_metrics_table)
446 goto err1_out;
447
448 smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL);
449 if (!smu_table->watermarks_table)
450 goto err2_out;
451
452 smu_table->ecc_table = kzalloc(tables[SMU_TABLE_ECCINFO].size, GFP_KERNEL);
453 if (!smu_table->ecc_table)
454 goto err3_out;
455
456 return 0;
457
458 err3_out:
459 kfree(smu_table->watermarks_table);
460 err2_out:
461 kfree(smu_table->gpu_metrics_table);
462 err1_out:
463 kfree(smu_table->metrics_table);
464 err0_out:
465 return -ENOMEM;
466 }
467
smu_v14_0_2_allocate_dpm_context(struct smu_context * smu)468 static int smu_v14_0_2_allocate_dpm_context(struct smu_context *smu)
469 {
470 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
471
472 smu_dpm->dpm_context = kzalloc(sizeof(struct smu_14_0_dpm_context),
473 GFP_KERNEL);
474 if (!smu_dpm->dpm_context)
475 return -ENOMEM;
476
477 smu_dpm->dpm_context_size = sizeof(struct smu_14_0_dpm_context);
478
479 return 0;
480 }
481
smu_v14_0_2_init_smc_tables(struct smu_context * smu)482 static int smu_v14_0_2_init_smc_tables(struct smu_context *smu)
483 {
484 int ret = 0;
485
486 ret = smu_v14_0_2_tables_init(smu);
487 if (ret)
488 return ret;
489
490 ret = smu_v14_0_2_allocate_dpm_context(smu);
491 if (ret)
492 return ret;
493
494 return smu_v14_0_init_smc_tables(smu);
495 }
496
smu_v14_0_2_set_default_dpm_table(struct smu_context * smu)497 static int smu_v14_0_2_set_default_dpm_table(struct smu_context *smu)
498 {
499 struct smu_14_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
500 struct smu_table_context *table_context = &smu->smu_table;
501 PPTable_t *pptable = table_context->driver_pptable;
502 SkuTable_t *skutable = &pptable->SkuTable;
503 struct smu_14_0_dpm_table *dpm_table;
504 struct smu_14_0_pcie_table *pcie_table;
505 uint32_t link_level;
506 int ret = 0;
507
508 /* socclk dpm table setup */
509 dpm_table = &dpm_context->dpm_tables.soc_table;
510 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
511 ret = smu_v14_0_set_single_dpm_table(smu,
512 SMU_SOCCLK,
513 dpm_table);
514 if (ret)
515 return ret;
516 } else {
517 dpm_table->count = 1;
518 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
519 dpm_table->dpm_levels[0].enabled = true;
520 dpm_table->min = dpm_table->dpm_levels[0].value;
521 dpm_table->max = dpm_table->dpm_levels[0].value;
522 }
523
524 /* gfxclk dpm table setup */
525 dpm_table = &dpm_context->dpm_tables.gfx_table;
526 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
527 ret = smu_v14_0_set_single_dpm_table(smu,
528 SMU_GFXCLK,
529 dpm_table);
530 if (ret)
531 return ret;
532
533 /*
534 * Update the reported maximum shader clock to the value
535 * which can be guarded to be achieved on all cards. This
536 * is aligned with Window setting. And considering that value
537 * might be not the peak frequency the card can achieve, it
538 * is normal some real-time clock frequency can overtake this
539 * labelled maximum clock frequency(for example in pp_dpm_sclk
540 * sysfs output).
541 */
542 if (skutable->DriverReportedClocks.GameClockAc &&
543 (dpm_table->dpm_levels[dpm_table->count - 1].value >
544 skutable->DriverReportedClocks.GameClockAc)) {
545 dpm_table->dpm_levels[dpm_table->count - 1].value =
546 skutable->DriverReportedClocks.GameClockAc;
547 dpm_table->max = skutable->DriverReportedClocks.GameClockAc;
548 }
549 } else {
550 dpm_table->count = 1;
551 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
552 dpm_table->dpm_levels[0].enabled = true;
553 dpm_table->min = dpm_table->dpm_levels[0].value;
554 dpm_table->max = dpm_table->dpm_levels[0].value;
555 }
556
557 /* uclk dpm table setup */
558 dpm_table = &dpm_context->dpm_tables.uclk_table;
559 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
560 ret = smu_v14_0_set_single_dpm_table(smu,
561 SMU_UCLK,
562 dpm_table);
563 if (ret)
564 return ret;
565 } else {
566 dpm_table->count = 1;
567 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
568 dpm_table->dpm_levels[0].enabled = true;
569 dpm_table->min = dpm_table->dpm_levels[0].value;
570 dpm_table->max = dpm_table->dpm_levels[0].value;
571 }
572
573 /* fclk dpm table setup */
574 dpm_table = &dpm_context->dpm_tables.fclk_table;
575 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) {
576 ret = smu_v14_0_set_single_dpm_table(smu,
577 SMU_FCLK,
578 dpm_table);
579 if (ret)
580 return ret;
581 } else {
582 dpm_table->count = 1;
583 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100;
584 dpm_table->dpm_levels[0].enabled = true;
585 dpm_table->min = dpm_table->dpm_levels[0].value;
586 dpm_table->max = dpm_table->dpm_levels[0].value;
587 }
588
589 /* vclk dpm table setup */
590 dpm_table = &dpm_context->dpm_tables.vclk_table;
591 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_VCLK_BIT)) {
592 ret = smu_v14_0_set_single_dpm_table(smu,
593 SMU_VCLK,
594 dpm_table);
595 if (ret)
596 return ret;
597 } else {
598 dpm_table->count = 1;
599 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.vclk / 100;
600 dpm_table->dpm_levels[0].enabled = true;
601 dpm_table->min = dpm_table->dpm_levels[0].value;
602 dpm_table->max = dpm_table->dpm_levels[0].value;
603 }
604
605 /* dclk dpm table setup */
606 dpm_table = &dpm_context->dpm_tables.dclk_table;
607 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCLK_BIT)) {
608 ret = smu_v14_0_set_single_dpm_table(smu,
609 SMU_DCLK,
610 dpm_table);
611 if (ret)
612 return ret;
613 } else {
614 dpm_table->count = 1;
615 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dclk / 100;
616 dpm_table->dpm_levels[0].enabled = true;
617 dpm_table->min = dpm_table->dpm_levels[0].value;
618 dpm_table->max = dpm_table->dpm_levels[0].value;
619 }
620
621 /* lclk dpm table setup */
622 pcie_table = &dpm_context->dpm_tables.pcie_table;
623 pcie_table->num_of_link_levels = 0;
624 for (link_level = 0; link_level < NUM_LINK_LEVELS; link_level++) {
625 if (!skutable->PcieGenSpeed[link_level] &&
626 !skutable->PcieLaneCount[link_level] &&
627 !skutable->LclkFreq[link_level])
628 continue;
629
630 pcie_table->pcie_gen[pcie_table->num_of_link_levels] =
631 skutable->PcieGenSpeed[link_level];
632 pcie_table->pcie_lane[pcie_table->num_of_link_levels] =
633 skutable->PcieLaneCount[link_level];
634 pcie_table->clk_freq[pcie_table->num_of_link_levels] =
635 skutable->LclkFreq[link_level];
636 pcie_table->num_of_link_levels++;
637
638 if (link_level == 0)
639 link_level++;
640 }
641
642 /* dcefclk dpm table setup */
643 dpm_table = &dpm_context->dpm_tables.dcef_table;
644 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCN_BIT)) {
645 ret = smu_v14_0_set_single_dpm_table(smu,
646 SMU_DCEFCLK,
647 dpm_table);
648 if (ret)
649 return ret;
650 } else {
651 dpm_table->count = 1;
652 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
653 dpm_table->dpm_levels[0].enabled = true;
654 dpm_table->min = dpm_table->dpm_levels[0].value;
655 dpm_table->max = dpm_table->dpm_levels[0].value;
656 }
657
658 return 0;
659 }
660
smu_v14_0_2_is_dpm_running(struct smu_context * smu)661 static bool smu_v14_0_2_is_dpm_running(struct smu_context *smu)
662 {
663 int ret = 0;
664 uint64_t feature_enabled;
665
666 ret = smu_cmn_get_enabled_mask(smu, &feature_enabled);
667 if (ret)
668 return false;
669
670 return !!(feature_enabled & SMC_DPM_FEATURE);
671 }
672
smu_v14_0_2_dump_pptable(struct smu_context * smu)673 static void smu_v14_0_2_dump_pptable(struct smu_context *smu)
674 {
675 struct smu_table_context *table_context = &smu->smu_table;
676 PPTable_t *pptable = table_context->driver_pptable;
677 PFE_Settings_t *PFEsettings = &pptable->PFE_Settings;
678
679 dev_info(smu->adev->dev, "Dumped PPTable:\n");
680
681 dev_info(smu->adev->dev, "Version = 0x%08x\n", PFEsettings->Version);
682 dev_info(smu->adev->dev, "FeaturesToRun[0] = 0x%08x\n", PFEsettings->FeaturesToRun[0]);
683 dev_info(smu->adev->dev, "FeaturesToRun[1] = 0x%08x\n", PFEsettings->FeaturesToRun[1]);
684 }
685
smu_v14_0_2_get_throttler_status(SmuMetrics_t * metrics)686 static uint32_t smu_v14_0_2_get_throttler_status(SmuMetrics_t *metrics)
687 {
688 uint32_t throttler_status = 0;
689 int i;
690
691 for (i = 0; i < THROTTLER_COUNT; i++)
692 throttler_status |=
693 (metrics->ThrottlingPercentage[i] ? 1U << i : 0);
694
695 return throttler_status;
696 }
697
698 #define SMU_14_0_2_BUSY_THRESHOLD 5
smu_v14_0_2_get_smu_metrics_data(struct smu_context * smu,MetricsMember_t member,uint32_t * value)699 static int smu_v14_0_2_get_smu_metrics_data(struct smu_context *smu,
700 MetricsMember_t member,
701 uint32_t *value)
702 {
703 struct smu_table_context *smu_table = &smu->smu_table;
704 SmuMetrics_t *metrics =
705 &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics);
706 int ret = 0;
707
708 ret = smu_cmn_get_metrics_table(smu,
709 NULL,
710 false);
711 if (ret)
712 return ret;
713
714 switch (member) {
715 case METRICS_CURR_GFXCLK:
716 *value = metrics->CurrClock[PPCLK_GFXCLK];
717 break;
718 case METRICS_CURR_SOCCLK:
719 *value = metrics->CurrClock[PPCLK_SOCCLK];
720 break;
721 case METRICS_CURR_UCLK:
722 *value = metrics->CurrClock[PPCLK_UCLK];
723 break;
724 case METRICS_CURR_VCLK:
725 *value = metrics->CurrClock[PPCLK_VCLK_0];
726 break;
727 case METRICS_CURR_DCLK:
728 *value = metrics->CurrClock[PPCLK_DCLK_0];
729 break;
730 case METRICS_CURR_FCLK:
731 *value = metrics->CurrClock[PPCLK_FCLK];
732 break;
733 case METRICS_CURR_DCEFCLK:
734 *value = metrics->CurrClock[PPCLK_DCFCLK];
735 break;
736 case METRICS_AVERAGE_GFXCLK:
737 if (metrics->AverageGfxActivity <= SMU_14_0_2_BUSY_THRESHOLD)
738 *value = metrics->AverageGfxclkFrequencyPostDs;
739 else
740 *value = metrics->AverageGfxclkFrequencyPreDs;
741 break;
742 case METRICS_AVERAGE_FCLK:
743 if (metrics->AverageUclkActivity <= SMU_14_0_2_BUSY_THRESHOLD)
744 *value = metrics->AverageFclkFrequencyPostDs;
745 else
746 *value = metrics->AverageFclkFrequencyPreDs;
747 break;
748 case METRICS_AVERAGE_UCLK:
749 if (metrics->AverageUclkActivity <= SMU_14_0_2_BUSY_THRESHOLD)
750 *value = metrics->AverageMemclkFrequencyPostDs;
751 else
752 *value = metrics->AverageMemclkFrequencyPreDs;
753 break;
754 case METRICS_AVERAGE_VCLK:
755 *value = metrics->AverageVclk0Frequency;
756 break;
757 case METRICS_AVERAGE_DCLK:
758 *value = metrics->AverageDclk0Frequency;
759 break;
760 case METRICS_AVERAGE_VCLK1:
761 *value = metrics->AverageVclk1Frequency;
762 break;
763 case METRICS_AVERAGE_DCLK1:
764 *value = metrics->AverageDclk1Frequency;
765 break;
766 case METRICS_AVERAGE_GFXACTIVITY:
767 *value = metrics->AverageGfxActivity;
768 break;
769 case METRICS_AVERAGE_MEMACTIVITY:
770 *value = metrics->AverageUclkActivity;
771 break;
772 case METRICS_AVERAGE_SOCKETPOWER:
773 *value = metrics->AverageSocketPower << 8;
774 break;
775 case METRICS_TEMPERATURE_EDGE:
776 *value = metrics->AvgTemperature[TEMP_EDGE] *
777 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
778 break;
779 case METRICS_TEMPERATURE_HOTSPOT:
780 *value = metrics->AvgTemperature[TEMP_HOTSPOT] *
781 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
782 break;
783 case METRICS_TEMPERATURE_MEM:
784 *value = metrics->AvgTemperature[TEMP_MEM] *
785 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
786 break;
787 case METRICS_TEMPERATURE_VRGFX:
788 *value = metrics->AvgTemperature[TEMP_VR_GFX] *
789 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
790 break;
791 case METRICS_TEMPERATURE_VRSOC:
792 *value = metrics->AvgTemperature[TEMP_VR_SOC] *
793 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
794 break;
795 case METRICS_THROTTLER_STATUS:
796 *value = smu_v14_0_2_get_throttler_status(metrics);
797 break;
798 case METRICS_CURR_FANSPEED:
799 *value = metrics->AvgFanRpm;
800 break;
801 case METRICS_CURR_FANPWM:
802 *value = metrics->AvgFanPwm;
803 break;
804 case METRICS_VOLTAGE_VDDGFX:
805 *value = metrics->AvgVoltage[SVI_PLANE_VDD_GFX];
806 break;
807 case METRICS_PCIE_RATE:
808 *value = metrics->PcieRate;
809 break;
810 case METRICS_PCIE_WIDTH:
811 *value = metrics->PcieWidth;
812 break;
813 default:
814 *value = UINT_MAX;
815 break;
816 }
817
818 return ret;
819 }
820
smu_v14_0_2_get_dpm_ultimate_freq(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * min,uint32_t * max)821 static int smu_v14_0_2_get_dpm_ultimate_freq(struct smu_context *smu,
822 enum smu_clk_type clk_type,
823 uint32_t *min,
824 uint32_t *max)
825 {
826 struct smu_14_0_dpm_context *dpm_context =
827 smu->smu_dpm.dpm_context;
828 struct smu_14_0_dpm_table *dpm_table;
829
830 switch (clk_type) {
831 case SMU_MCLK:
832 case SMU_UCLK:
833 /* uclk dpm table */
834 dpm_table = &dpm_context->dpm_tables.uclk_table;
835 break;
836 case SMU_GFXCLK:
837 case SMU_SCLK:
838 /* gfxclk dpm table */
839 dpm_table = &dpm_context->dpm_tables.gfx_table;
840 break;
841 case SMU_SOCCLK:
842 /* socclk dpm table */
843 dpm_table = &dpm_context->dpm_tables.soc_table;
844 break;
845 case SMU_FCLK:
846 /* fclk dpm table */
847 dpm_table = &dpm_context->dpm_tables.fclk_table;
848 break;
849 case SMU_VCLK:
850 case SMU_VCLK1:
851 /* vclk dpm table */
852 dpm_table = &dpm_context->dpm_tables.vclk_table;
853 break;
854 case SMU_DCLK:
855 case SMU_DCLK1:
856 /* dclk dpm table */
857 dpm_table = &dpm_context->dpm_tables.dclk_table;
858 break;
859 default:
860 dev_err(smu->adev->dev, "Unsupported clock type!\n");
861 return -EINVAL;
862 }
863
864 if (min)
865 *min = dpm_table->min;
866 if (max)
867 *max = dpm_table->max;
868
869 return 0;
870 }
871
smu_v14_0_2_read_sensor(struct smu_context * smu,enum amd_pp_sensors sensor,void * data,uint32_t * size)872 static int smu_v14_0_2_read_sensor(struct smu_context *smu,
873 enum amd_pp_sensors sensor,
874 void *data,
875 uint32_t *size)
876 {
877 struct smu_table_context *table_context = &smu->smu_table;
878 PPTable_t *smc_pptable = table_context->driver_pptable;
879 int ret = 0;
880
881 switch (sensor) {
882 case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
883 *(uint16_t *)data = smc_pptable->CustomSkuTable.FanMaximumRpm;
884 *size = 4;
885 break;
886 case AMDGPU_PP_SENSOR_MEM_LOAD:
887 ret = smu_v14_0_2_get_smu_metrics_data(smu,
888 METRICS_AVERAGE_MEMACTIVITY,
889 (uint32_t *)data);
890 *size = 4;
891 break;
892 case AMDGPU_PP_SENSOR_GPU_LOAD:
893 ret = smu_v14_0_2_get_smu_metrics_data(smu,
894 METRICS_AVERAGE_GFXACTIVITY,
895 (uint32_t *)data);
896 *size = 4;
897 break;
898 case AMDGPU_PP_SENSOR_GPU_AVG_POWER:
899 ret = smu_v14_0_2_get_smu_metrics_data(smu,
900 METRICS_AVERAGE_SOCKETPOWER,
901 (uint32_t *)data);
902 *size = 4;
903 break;
904 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
905 ret = smu_v14_0_2_get_smu_metrics_data(smu,
906 METRICS_TEMPERATURE_HOTSPOT,
907 (uint32_t *)data);
908 *size = 4;
909 break;
910 case AMDGPU_PP_SENSOR_EDGE_TEMP:
911 ret = smu_v14_0_2_get_smu_metrics_data(smu,
912 METRICS_TEMPERATURE_EDGE,
913 (uint32_t *)data);
914 *size = 4;
915 break;
916 case AMDGPU_PP_SENSOR_MEM_TEMP:
917 ret = smu_v14_0_2_get_smu_metrics_data(smu,
918 METRICS_TEMPERATURE_MEM,
919 (uint32_t *)data);
920 *size = 4;
921 break;
922 case AMDGPU_PP_SENSOR_GFX_MCLK:
923 ret = smu_v14_0_2_get_smu_metrics_data(smu,
924 METRICS_CURR_UCLK,
925 (uint32_t *)data);
926 *(uint32_t *)data *= 100;
927 *size = 4;
928 break;
929 case AMDGPU_PP_SENSOR_GFX_SCLK:
930 ret = smu_v14_0_2_get_smu_metrics_data(smu,
931 METRICS_AVERAGE_GFXCLK,
932 (uint32_t *)data);
933 *(uint32_t *)data *= 100;
934 *size = 4;
935 break;
936 case AMDGPU_PP_SENSOR_VDDGFX:
937 ret = smu_v14_0_2_get_smu_metrics_data(smu,
938 METRICS_VOLTAGE_VDDGFX,
939 (uint32_t *)data);
940 *size = 4;
941 break;
942 default:
943 ret = -EOPNOTSUPP;
944 break;
945 }
946
947 return ret;
948 }
949
smu_v14_0_2_get_current_clk_freq_by_table(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * value)950 static int smu_v14_0_2_get_current_clk_freq_by_table(struct smu_context *smu,
951 enum smu_clk_type clk_type,
952 uint32_t *value)
953 {
954 MetricsMember_t member_type;
955 int clk_id = 0;
956
957 clk_id = smu_cmn_to_asic_specific_index(smu,
958 CMN2ASIC_MAPPING_CLK,
959 clk_type);
960 if (clk_id < 0)
961 return -EINVAL;
962
963 switch (clk_id) {
964 case PPCLK_GFXCLK:
965 member_type = METRICS_AVERAGE_GFXCLK;
966 break;
967 case PPCLK_UCLK:
968 member_type = METRICS_CURR_UCLK;
969 break;
970 case PPCLK_FCLK:
971 member_type = METRICS_CURR_FCLK;
972 break;
973 case PPCLK_SOCCLK:
974 member_type = METRICS_CURR_SOCCLK;
975 break;
976 case PPCLK_VCLK_0:
977 member_type = METRICS_AVERAGE_VCLK;
978 break;
979 case PPCLK_DCLK_0:
980 member_type = METRICS_AVERAGE_DCLK;
981 break;
982 case PPCLK_DCFCLK:
983 member_type = METRICS_CURR_DCEFCLK;
984 break;
985 default:
986 return -EINVAL;
987 }
988
989 return smu_v14_0_2_get_smu_metrics_data(smu,
990 member_type,
991 value);
992 }
993
smu_v14_0_2_is_od_feature_supported(struct smu_context * smu,int od_feature_bit)994 static bool smu_v14_0_2_is_od_feature_supported(struct smu_context *smu,
995 int od_feature_bit)
996 {
997 PPTable_t *pptable = smu->smu_table.driver_pptable;
998 const OverDriveLimits_t * const overdrive_upperlimits =
999 &pptable->SkuTable.OverDriveLimitsBasicMax;
1000
1001 return overdrive_upperlimits->FeatureCtrlMask & (1U << od_feature_bit);
1002 }
1003
smu_v14_0_2_get_od_setting_limits(struct smu_context * smu,int od_feature_bit,int32_t * min,int32_t * max)1004 static void smu_v14_0_2_get_od_setting_limits(struct smu_context *smu,
1005 int od_feature_bit,
1006 int32_t *min,
1007 int32_t *max)
1008 {
1009 PPTable_t *pptable = smu->smu_table.driver_pptable;
1010 const OverDriveLimits_t * const overdrive_upperlimits =
1011 &pptable->SkuTable.OverDriveLimitsBasicMax;
1012 const OverDriveLimits_t * const overdrive_lowerlimits =
1013 &pptable->SkuTable.OverDriveLimitsBasicMin;
1014 int32_t od_min_setting, od_max_setting;
1015
1016 switch (od_feature_bit) {
1017 case PP_OD_FEATURE_GFXCLK_FMIN:
1018 case PP_OD_FEATURE_GFXCLK_FMAX:
1019 od_min_setting = overdrive_lowerlimits->GfxclkFoffset;
1020 od_max_setting = overdrive_upperlimits->GfxclkFoffset;
1021 break;
1022 case PP_OD_FEATURE_UCLK_FMIN:
1023 od_min_setting = overdrive_lowerlimits->UclkFmin;
1024 od_max_setting = overdrive_upperlimits->UclkFmin;
1025 break;
1026 case PP_OD_FEATURE_UCLK_FMAX:
1027 od_min_setting = overdrive_lowerlimits->UclkFmax;
1028 od_max_setting = overdrive_upperlimits->UclkFmax;
1029 break;
1030 case PP_OD_FEATURE_GFX_VF_CURVE:
1031 od_min_setting = overdrive_lowerlimits->VoltageOffsetPerZoneBoundary[0];
1032 od_max_setting = overdrive_upperlimits->VoltageOffsetPerZoneBoundary[0];
1033 break;
1034 case PP_OD_FEATURE_FAN_CURVE_TEMP:
1035 od_min_setting = overdrive_lowerlimits->FanLinearTempPoints[0];
1036 od_max_setting = overdrive_upperlimits->FanLinearTempPoints[0];
1037 break;
1038 case PP_OD_FEATURE_FAN_CURVE_PWM:
1039 od_min_setting = overdrive_lowerlimits->FanLinearPwmPoints[0];
1040 od_max_setting = overdrive_upperlimits->FanLinearPwmPoints[0];
1041 break;
1042 case PP_OD_FEATURE_FAN_ACOUSTIC_LIMIT:
1043 od_min_setting = overdrive_lowerlimits->AcousticLimitRpmThreshold;
1044 od_max_setting = overdrive_upperlimits->AcousticLimitRpmThreshold;
1045 break;
1046 case PP_OD_FEATURE_FAN_ACOUSTIC_TARGET:
1047 od_min_setting = overdrive_lowerlimits->AcousticTargetRpmThreshold;
1048 od_max_setting = overdrive_upperlimits->AcousticTargetRpmThreshold;
1049 break;
1050 case PP_OD_FEATURE_FAN_TARGET_TEMPERATURE:
1051 od_min_setting = overdrive_lowerlimits->FanTargetTemperature;
1052 od_max_setting = overdrive_upperlimits->FanTargetTemperature;
1053 break;
1054 case PP_OD_FEATURE_FAN_MINIMUM_PWM:
1055 od_min_setting = overdrive_lowerlimits->FanMinimumPwm;
1056 od_max_setting = overdrive_upperlimits->FanMinimumPwm;
1057 break;
1058 default:
1059 od_min_setting = od_max_setting = INT_MAX;
1060 break;
1061 }
1062
1063 if (min)
1064 *min = od_min_setting;
1065 if (max)
1066 *max = od_max_setting;
1067 }
1068
smu_v14_0_2_print_clk_levels(struct smu_context * smu,enum smu_clk_type clk_type,char * buf)1069 static int smu_v14_0_2_print_clk_levels(struct smu_context *smu,
1070 enum smu_clk_type clk_type,
1071 char *buf)
1072 {
1073 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
1074 struct smu_14_0_dpm_context *dpm_context = smu_dpm->dpm_context;
1075 OverDriveTableExternal_t *od_table =
1076 (OverDriveTableExternal_t *)smu->smu_table.overdrive_table;
1077 struct smu_14_0_dpm_table *single_dpm_table;
1078 struct smu_14_0_pcie_table *pcie_table;
1079 uint32_t gen_speed, lane_width;
1080 int i, curr_freq, size = 0;
1081 int32_t min_value, max_value;
1082 int ret = 0;
1083
1084 smu_cmn_get_sysfs_buf(&buf, &size);
1085
1086 if (amdgpu_ras_intr_triggered()) {
1087 size += sysfs_emit_at(buf, size, "unavailable\n");
1088 return size;
1089 }
1090
1091 switch (clk_type) {
1092 case SMU_SCLK:
1093 single_dpm_table = &(dpm_context->dpm_tables.gfx_table);
1094 break;
1095 case SMU_MCLK:
1096 single_dpm_table = &(dpm_context->dpm_tables.uclk_table);
1097 break;
1098 case SMU_SOCCLK:
1099 single_dpm_table = &(dpm_context->dpm_tables.soc_table);
1100 break;
1101 case SMU_FCLK:
1102 single_dpm_table = &(dpm_context->dpm_tables.fclk_table);
1103 break;
1104 case SMU_VCLK:
1105 case SMU_VCLK1:
1106 single_dpm_table = &(dpm_context->dpm_tables.vclk_table);
1107 break;
1108 case SMU_DCLK:
1109 case SMU_DCLK1:
1110 single_dpm_table = &(dpm_context->dpm_tables.dclk_table);
1111 break;
1112 case SMU_DCEFCLK:
1113 single_dpm_table = &(dpm_context->dpm_tables.dcef_table);
1114 break;
1115 default:
1116 break;
1117 }
1118
1119 switch (clk_type) {
1120 case SMU_SCLK:
1121 case SMU_MCLK:
1122 case SMU_SOCCLK:
1123 case SMU_FCLK:
1124 case SMU_VCLK:
1125 case SMU_VCLK1:
1126 case SMU_DCLK:
1127 case SMU_DCLK1:
1128 case SMU_DCEFCLK:
1129 ret = smu_v14_0_2_get_current_clk_freq_by_table(smu, clk_type, &curr_freq);
1130 if (ret) {
1131 dev_err(smu->adev->dev, "Failed to get current clock freq!");
1132 return ret;
1133 }
1134
1135 if (single_dpm_table->is_fine_grained) {
1136 /*
1137 * For fine grained dpms, there are only two dpm levels:
1138 * - level 0 -> min clock freq
1139 * - level 1 -> max clock freq
1140 * And the current clock frequency can be any value between them.
1141 * So, if the current clock frequency is not at level 0 or level 1,
1142 * we will fake it as three dpm levels:
1143 * - level 0 -> min clock freq
1144 * - level 1 -> current actual clock freq
1145 * - level 2 -> max clock freq
1146 */
1147 if ((single_dpm_table->dpm_levels[0].value != curr_freq) &&
1148 (single_dpm_table->dpm_levels[1].value != curr_freq)) {
1149 size += sysfs_emit_at(buf, size, "0: %uMhz\n",
1150 single_dpm_table->dpm_levels[0].value);
1151 size += sysfs_emit_at(buf, size, "1: %uMhz *\n",
1152 curr_freq);
1153 size += sysfs_emit_at(buf, size, "2: %uMhz\n",
1154 single_dpm_table->dpm_levels[1].value);
1155 } else {
1156 size += sysfs_emit_at(buf, size, "0: %uMhz %s\n",
1157 single_dpm_table->dpm_levels[0].value,
1158 single_dpm_table->dpm_levels[0].value == curr_freq ? "*" : "");
1159 size += sysfs_emit_at(buf, size, "1: %uMhz %s\n",
1160 single_dpm_table->dpm_levels[1].value,
1161 single_dpm_table->dpm_levels[1].value == curr_freq ? "*" : "");
1162 }
1163 } else {
1164 for (i = 0; i < single_dpm_table->count; i++)
1165 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n",
1166 i, single_dpm_table->dpm_levels[i].value,
1167 single_dpm_table->dpm_levels[i].value == curr_freq ? "*" : "");
1168 }
1169 break;
1170 case SMU_PCIE:
1171 ret = smu_v14_0_2_get_smu_metrics_data(smu,
1172 METRICS_PCIE_RATE,
1173 &gen_speed);
1174 if (ret)
1175 return ret;
1176
1177 ret = smu_v14_0_2_get_smu_metrics_data(smu,
1178 METRICS_PCIE_WIDTH,
1179 &lane_width);
1180 if (ret)
1181 return ret;
1182
1183 pcie_table = &(dpm_context->dpm_tables.pcie_table);
1184 for (i = 0; i < pcie_table->num_of_link_levels; i++)
1185 size += sysfs_emit_at(buf, size, "%d: %s %s %dMhz %s\n", i,
1186 (pcie_table->pcie_gen[i] == 0) ? "2.5GT/s," :
1187 (pcie_table->pcie_gen[i] == 1) ? "5.0GT/s," :
1188 (pcie_table->pcie_gen[i] == 2) ? "8.0GT/s," :
1189 (pcie_table->pcie_gen[i] == 3) ? "16.0GT/s," : "",
1190 (pcie_table->pcie_lane[i] == 1) ? "x1" :
1191 (pcie_table->pcie_lane[i] == 2) ? "x2" :
1192 (pcie_table->pcie_lane[i] == 3) ? "x4" :
1193 (pcie_table->pcie_lane[i] == 4) ? "x8" :
1194 (pcie_table->pcie_lane[i] == 5) ? "x12" :
1195 (pcie_table->pcie_lane[i] == 6) ? "x16" : "",
1196 pcie_table->clk_freq[i],
1197 (gen_speed == DECODE_GEN_SPEED(pcie_table->pcie_gen[i])) &&
1198 (lane_width == DECODE_LANE_WIDTH(pcie_table->pcie_lane[i])) ?
1199 "*" : "");
1200 break;
1201
1202 case SMU_OD_SCLK:
1203 if (!smu_v14_0_2_is_od_feature_supported(smu,
1204 PP_OD_FEATURE_GFXCLK_BIT))
1205 break;
1206
1207 PPTable_t *pptable = smu->smu_table.driver_pptable;
1208 const OverDriveLimits_t * const overdrive_upperlimits =
1209 &pptable->SkuTable.OverDriveLimitsBasicMax;
1210 const OverDriveLimits_t * const overdrive_lowerlimits =
1211 &pptable->SkuTable.OverDriveLimitsBasicMin;
1212
1213 size += sysfs_emit_at(buf, size, "OD_SCLK_OFFSET:\n");
1214 size += sysfs_emit_at(buf, size, "0: %dMhz\n1: %uMhz\n",
1215 overdrive_lowerlimits->GfxclkFoffset,
1216 overdrive_upperlimits->GfxclkFoffset);
1217 break;
1218
1219 case SMU_OD_MCLK:
1220 if (!smu_v14_0_2_is_od_feature_supported(smu,
1221 PP_OD_FEATURE_UCLK_BIT))
1222 break;
1223
1224 size += sysfs_emit_at(buf, size, "OD_MCLK:\n");
1225 size += sysfs_emit_at(buf, size, "0: %uMhz\n1: %uMHz\n",
1226 od_table->OverDriveTable.UclkFmin,
1227 od_table->OverDriveTable.UclkFmax);
1228 break;
1229
1230 case SMU_OD_VDDGFX_OFFSET:
1231 if (!smu_v14_0_2_is_od_feature_supported(smu,
1232 PP_OD_FEATURE_GFX_VF_CURVE_BIT))
1233 break;
1234
1235 size += sysfs_emit_at(buf, size, "OD_VDDGFX_OFFSET:\n");
1236 size += sysfs_emit_at(buf, size, "%dmV\n",
1237 od_table->OverDriveTable.VoltageOffsetPerZoneBoundary[0]);
1238 break;
1239
1240 case SMU_OD_FAN_CURVE:
1241 if (!smu_v14_0_2_is_od_feature_supported(smu,
1242 PP_OD_FEATURE_FAN_CURVE_BIT))
1243 break;
1244
1245 size += sysfs_emit_at(buf, size, "OD_FAN_CURVE:\n");
1246 for (i = 0; i < NUM_OD_FAN_MAX_POINTS - 1; i++)
1247 size += sysfs_emit_at(buf, size, "%d: %dC %d%%\n",
1248 i,
1249 (int)od_table->OverDriveTable.FanLinearTempPoints[i],
1250 (int)od_table->OverDriveTable.FanLinearPwmPoints[i]);
1251
1252 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
1253 smu_v14_0_2_get_od_setting_limits(smu,
1254 PP_OD_FEATURE_FAN_CURVE_TEMP,
1255 &min_value,
1256 &max_value);
1257 size += sysfs_emit_at(buf, size, "FAN_CURVE(hotspot temp): %uC %uC\n",
1258 min_value, max_value);
1259
1260 smu_v14_0_2_get_od_setting_limits(smu,
1261 PP_OD_FEATURE_FAN_CURVE_PWM,
1262 &min_value,
1263 &max_value);
1264 size += sysfs_emit_at(buf, size, "FAN_CURVE(fan speed): %u%% %u%%\n",
1265 min_value, max_value);
1266
1267 break;
1268
1269 case SMU_OD_ACOUSTIC_LIMIT:
1270 if (!smu_v14_0_2_is_od_feature_supported(smu,
1271 PP_OD_FEATURE_FAN_CURVE_BIT))
1272 break;
1273
1274 size += sysfs_emit_at(buf, size, "OD_ACOUSTIC_LIMIT:\n");
1275 size += sysfs_emit_at(buf, size, "%d\n",
1276 (int)od_table->OverDriveTable.AcousticLimitRpmThreshold);
1277
1278 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
1279 smu_v14_0_2_get_od_setting_limits(smu,
1280 PP_OD_FEATURE_FAN_ACOUSTIC_LIMIT,
1281 &min_value,
1282 &max_value);
1283 size += sysfs_emit_at(buf, size, "ACOUSTIC_LIMIT: %u %u\n",
1284 min_value, max_value);
1285 break;
1286
1287 case SMU_OD_ACOUSTIC_TARGET:
1288 if (!smu_v14_0_2_is_od_feature_supported(smu,
1289 PP_OD_FEATURE_FAN_CURVE_BIT))
1290 break;
1291
1292 size += sysfs_emit_at(buf, size, "OD_ACOUSTIC_TARGET:\n");
1293 size += sysfs_emit_at(buf, size, "%d\n",
1294 (int)od_table->OverDriveTable.AcousticTargetRpmThreshold);
1295
1296 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
1297 smu_v14_0_2_get_od_setting_limits(smu,
1298 PP_OD_FEATURE_FAN_ACOUSTIC_TARGET,
1299 &min_value,
1300 &max_value);
1301 size += sysfs_emit_at(buf, size, "ACOUSTIC_TARGET: %u %u\n",
1302 min_value, max_value);
1303 break;
1304
1305 case SMU_OD_FAN_TARGET_TEMPERATURE:
1306 if (!smu_v14_0_2_is_od_feature_supported(smu,
1307 PP_OD_FEATURE_FAN_CURVE_BIT))
1308 break;
1309
1310 size += sysfs_emit_at(buf, size, "FAN_TARGET_TEMPERATURE:\n");
1311 size += sysfs_emit_at(buf, size, "%d\n",
1312 (int)od_table->OverDriveTable.FanTargetTemperature);
1313
1314 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
1315 smu_v14_0_2_get_od_setting_limits(smu,
1316 PP_OD_FEATURE_FAN_TARGET_TEMPERATURE,
1317 &min_value,
1318 &max_value);
1319 size += sysfs_emit_at(buf, size, "TARGET_TEMPERATURE: %u %u\n",
1320 min_value, max_value);
1321 break;
1322
1323 case SMU_OD_FAN_MINIMUM_PWM:
1324 if (!smu_v14_0_2_is_od_feature_supported(smu,
1325 PP_OD_FEATURE_FAN_CURVE_BIT))
1326 break;
1327
1328 size += sysfs_emit_at(buf, size, "FAN_MINIMUM_PWM:\n");
1329 size += sysfs_emit_at(buf, size, "%d\n",
1330 (int)od_table->OverDriveTable.FanMinimumPwm);
1331
1332 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
1333 smu_v14_0_2_get_od_setting_limits(smu,
1334 PP_OD_FEATURE_FAN_MINIMUM_PWM,
1335 &min_value,
1336 &max_value);
1337 size += sysfs_emit_at(buf, size, "MINIMUM_PWM: %u %u\n",
1338 min_value, max_value);
1339 break;
1340
1341 case SMU_OD_RANGE:
1342 if (!smu_v14_0_2_is_od_feature_supported(smu, PP_OD_FEATURE_GFXCLK_BIT) &&
1343 !smu_v14_0_2_is_od_feature_supported(smu, PP_OD_FEATURE_UCLK_BIT) &&
1344 !smu_v14_0_2_is_od_feature_supported(smu, PP_OD_FEATURE_GFX_VF_CURVE_BIT))
1345 break;
1346
1347 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
1348
1349 if (smu_v14_0_2_is_od_feature_supported(smu, PP_OD_FEATURE_GFXCLK_BIT)) {
1350 smu_v14_0_2_get_od_setting_limits(smu,
1351 PP_OD_FEATURE_GFXCLK_FMIN,
1352 &min_value,
1353 NULL);
1354 smu_v14_0_2_get_od_setting_limits(smu,
1355 PP_OD_FEATURE_GFXCLK_FMAX,
1356 NULL,
1357 &max_value);
1358 size += sysfs_emit_at(buf, size, "SCLK_OFFSET: %7dMhz %10uMhz\n",
1359 min_value, max_value);
1360 }
1361
1362 if (smu_v14_0_2_is_od_feature_supported(smu, PP_OD_FEATURE_UCLK_BIT)) {
1363 smu_v14_0_2_get_od_setting_limits(smu,
1364 PP_OD_FEATURE_UCLK_FMIN,
1365 &min_value,
1366 NULL);
1367 smu_v14_0_2_get_od_setting_limits(smu,
1368 PP_OD_FEATURE_UCLK_FMAX,
1369 NULL,
1370 &max_value);
1371 size += sysfs_emit_at(buf, size, "MCLK: %7uMhz %10uMhz\n",
1372 min_value, max_value);
1373 }
1374
1375 if (smu_v14_0_2_is_od_feature_supported(smu, PP_OD_FEATURE_GFX_VF_CURVE_BIT)) {
1376 smu_v14_0_2_get_od_setting_limits(smu,
1377 PP_OD_FEATURE_GFX_VF_CURVE,
1378 &min_value,
1379 &max_value);
1380 size += sysfs_emit_at(buf, size, "VDDGFX_OFFSET: %7dmv %10dmv\n",
1381 min_value, max_value);
1382 }
1383 break;
1384
1385 default:
1386 break;
1387 }
1388
1389 return size;
1390 }
1391
smu_v14_0_2_force_clk_levels(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t mask)1392 static int smu_v14_0_2_force_clk_levels(struct smu_context *smu,
1393 enum smu_clk_type clk_type,
1394 uint32_t mask)
1395 {
1396 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
1397 struct smu_14_0_dpm_context *dpm_context = smu_dpm->dpm_context;
1398 struct smu_14_0_dpm_table *single_dpm_table;
1399 uint32_t soft_min_level, soft_max_level;
1400 uint32_t min_freq, max_freq;
1401 int ret = 0;
1402
1403 soft_min_level = mask ? (ffs(mask) - 1) : 0;
1404 soft_max_level = mask ? (fls(mask) - 1) : 0;
1405
1406 switch (clk_type) {
1407 case SMU_GFXCLK:
1408 case SMU_SCLK:
1409 single_dpm_table = &(dpm_context->dpm_tables.gfx_table);
1410 break;
1411 case SMU_MCLK:
1412 case SMU_UCLK:
1413 single_dpm_table = &(dpm_context->dpm_tables.uclk_table);
1414 break;
1415 case SMU_SOCCLK:
1416 single_dpm_table = &(dpm_context->dpm_tables.soc_table);
1417 break;
1418 case SMU_FCLK:
1419 single_dpm_table = &(dpm_context->dpm_tables.fclk_table);
1420 break;
1421 case SMU_VCLK:
1422 case SMU_VCLK1:
1423 single_dpm_table = &(dpm_context->dpm_tables.vclk_table);
1424 break;
1425 case SMU_DCLK:
1426 case SMU_DCLK1:
1427 single_dpm_table = &(dpm_context->dpm_tables.dclk_table);
1428 break;
1429 default:
1430 break;
1431 }
1432
1433 switch (clk_type) {
1434 case SMU_GFXCLK:
1435 case SMU_SCLK:
1436 case SMU_MCLK:
1437 case SMU_UCLK:
1438 case SMU_SOCCLK:
1439 case SMU_FCLK:
1440 case SMU_VCLK:
1441 case SMU_VCLK1:
1442 case SMU_DCLK:
1443 case SMU_DCLK1:
1444 if (single_dpm_table->is_fine_grained) {
1445 /* There is only 2 levels for fine grained DPM */
1446 soft_max_level = (soft_max_level >= 1 ? 1 : 0);
1447 soft_min_level = (soft_min_level >= 1 ? 1 : 0);
1448 } else {
1449 if ((soft_max_level >= single_dpm_table->count) ||
1450 (soft_min_level >= single_dpm_table->count))
1451 return -EINVAL;
1452 }
1453
1454 min_freq = single_dpm_table->dpm_levels[soft_min_level].value;
1455 max_freq = single_dpm_table->dpm_levels[soft_max_level].value;
1456
1457 ret = smu_v14_0_set_soft_freq_limited_range(smu,
1458 clk_type,
1459 min_freq,
1460 max_freq);
1461 break;
1462 case SMU_DCEFCLK:
1463 case SMU_PCIE:
1464 default:
1465 break;
1466 }
1467
1468 return ret;
1469 }
1470
smu_v14_0_2_update_pcie_parameters(struct smu_context * smu,uint8_t pcie_gen_cap,uint8_t pcie_width_cap)1471 static int smu_v14_0_2_update_pcie_parameters(struct smu_context *smu,
1472 uint8_t pcie_gen_cap,
1473 uint8_t pcie_width_cap)
1474 {
1475 struct smu_14_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
1476 struct smu_14_0_pcie_table *pcie_table =
1477 &dpm_context->dpm_tables.pcie_table;
1478 uint32_t smu_pcie_arg;
1479 int ret, i;
1480
1481 for (i = 0; i < pcie_table->num_of_link_levels; i++) {
1482 if (pcie_table->pcie_gen[i] > pcie_gen_cap)
1483 pcie_table->pcie_gen[i] = pcie_gen_cap;
1484 if (pcie_table->pcie_lane[i] > pcie_width_cap)
1485 pcie_table->pcie_lane[i] = pcie_width_cap;
1486
1487 smu_pcie_arg = i << 16;
1488 smu_pcie_arg |= pcie_table->pcie_gen[i] << 8;
1489 smu_pcie_arg |= pcie_table->pcie_lane[i];
1490
1491 ret = smu_cmn_send_smc_msg_with_param(smu,
1492 SMU_MSG_OverridePcieParameters,
1493 smu_pcie_arg,
1494 NULL);
1495 if (ret)
1496 return ret;
1497 }
1498
1499 return 0;
1500 }
1501
1502 static const struct smu_temperature_range smu14_thermal_policy[] = {
1503 {-273150, 99000, 99000, -273150, 99000, 99000, -273150, 99000, 99000},
1504 { 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000},
1505 };
1506
smu_v14_0_2_get_thermal_temperature_range(struct smu_context * smu,struct smu_temperature_range * range)1507 static int smu_v14_0_2_get_thermal_temperature_range(struct smu_context *smu,
1508 struct smu_temperature_range *range)
1509 {
1510 struct smu_table_context *table_context = &smu->smu_table;
1511 struct smu_14_0_2_powerplay_table *powerplay_table =
1512 table_context->power_play_table;
1513 PPTable_t *pptable = smu->smu_table.driver_pptable;
1514
1515 if (amdgpu_sriov_vf(smu->adev))
1516 return 0;
1517
1518 if (!range)
1519 return -EINVAL;
1520
1521 memcpy(range, &smu14_thermal_policy[0], sizeof(struct smu_temperature_range));
1522
1523 range->max = pptable->CustomSkuTable.TemperatureLimit[TEMP_EDGE] *
1524 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1525 range->edge_emergency_max = (pptable->CustomSkuTable.TemperatureLimit[TEMP_EDGE] + CTF_OFFSET_EDGE) *
1526 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1527 range->hotspot_crit_max = pptable->CustomSkuTable.TemperatureLimit[TEMP_HOTSPOT] *
1528 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1529 range->hotspot_emergency_max = (pptable->CustomSkuTable.TemperatureLimit[TEMP_HOTSPOT] + CTF_OFFSET_HOTSPOT) *
1530 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1531 range->mem_crit_max = pptable->CustomSkuTable.TemperatureLimit[TEMP_MEM] *
1532 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1533 range->mem_emergency_max = (pptable->CustomSkuTable.TemperatureLimit[TEMP_MEM] + CTF_OFFSET_MEM)*
1534 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1535 range->software_shutdown_temp = powerplay_table->software_shutdown_temp;
1536 range->software_shutdown_temp_offset = pptable->CustomSkuTable.FanAbnormalTempLimitOffset;
1537
1538 return 0;
1539 }
1540
smu_v14_0_2_populate_umd_state_clk(struct smu_context * smu)1541 static int smu_v14_0_2_populate_umd_state_clk(struct smu_context *smu)
1542 {
1543 struct smu_14_0_dpm_context *dpm_context =
1544 smu->smu_dpm.dpm_context;
1545 struct smu_14_0_dpm_table *gfx_table =
1546 &dpm_context->dpm_tables.gfx_table;
1547 struct smu_14_0_dpm_table *mem_table =
1548 &dpm_context->dpm_tables.uclk_table;
1549 struct smu_14_0_dpm_table *soc_table =
1550 &dpm_context->dpm_tables.soc_table;
1551 struct smu_14_0_dpm_table *vclk_table =
1552 &dpm_context->dpm_tables.vclk_table;
1553 struct smu_14_0_dpm_table *dclk_table =
1554 &dpm_context->dpm_tables.dclk_table;
1555 struct smu_14_0_dpm_table *fclk_table =
1556 &dpm_context->dpm_tables.fclk_table;
1557 struct smu_umd_pstate_table *pstate_table =
1558 &smu->pstate_table;
1559 struct smu_table_context *table_context = &smu->smu_table;
1560 PPTable_t *pptable = table_context->driver_pptable;
1561 DriverReportedClocks_t driver_clocks =
1562 pptable->SkuTable.DriverReportedClocks;
1563
1564 pstate_table->gfxclk_pstate.min = gfx_table->min;
1565 if (driver_clocks.GameClockAc &&
1566 (driver_clocks.GameClockAc < gfx_table->max))
1567 pstate_table->gfxclk_pstate.peak = driver_clocks.GameClockAc;
1568 else
1569 pstate_table->gfxclk_pstate.peak = gfx_table->max;
1570
1571 pstate_table->uclk_pstate.min = mem_table->min;
1572 pstate_table->uclk_pstate.peak = mem_table->max;
1573
1574 pstate_table->socclk_pstate.min = soc_table->min;
1575 pstate_table->socclk_pstate.peak = soc_table->max;
1576
1577 pstate_table->vclk_pstate.min = vclk_table->min;
1578 pstate_table->vclk_pstate.peak = vclk_table->max;
1579
1580 pstate_table->dclk_pstate.min = dclk_table->min;
1581 pstate_table->dclk_pstate.peak = dclk_table->max;
1582
1583 pstate_table->fclk_pstate.min = fclk_table->min;
1584 pstate_table->fclk_pstate.peak = fclk_table->max;
1585
1586 if (driver_clocks.BaseClockAc &&
1587 driver_clocks.BaseClockAc < gfx_table->max)
1588 pstate_table->gfxclk_pstate.standard = driver_clocks.BaseClockAc;
1589 else
1590 pstate_table->gfxclk_pstate.standard = gfx_table->max;
1591 pstate_table->uclk_pstate.standard = mem_table->max;
1592 pstate_table->socclk_pstate.standard = soc_table->min;
1593 pstate_table->vclk_pstate.standard = vclk_table->min;
1594 pstate_table->dclk_pstate.standard = dclk_table->min;
1595 pstate_table->fclk_pstate.standard = fclk_table->min;
1596
1597 return 0;
1598 }
1599
smu_v14_0_2_get_unique_id(struct smu_context * smu)1600 static void smu_v14_0_2_get_unique_id(struct smu_context *smu)
1601 {
1602 struct smu_table_context *smu_table = &smu->smu_table;
1603 SmuMetrics_t *metrics =
1604 &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics);
1605 struct amdgpu_device *adev = smu->adev;
1606 uint32_t upper32 = 0, lower32 = 0;
1607 int ret;
1608
1609 ret = smu_cmn_get_metrics_table(smu, NULL, false);
1610 if (ret)
1611 goto out;
1612
1613 upper32 = metrics->PublicSerialNumberUpper;
1614 lower32 = metrics->PublicSerialNumberLower;
1615
1616 out:
1617 adev->unique_id = ((uint64_t)upper32 << 32) | lower32;
1618 }
1619
smu_v14_0_2_get_power_limit(struct smu_context * smu,uint32_t * current_power_limit,uint32_t * default_power_limit,uint32_t * max_power_limit,uint32_t * min_power_limit)1620 static int smu_v14_0_2_get_power_limit(struct smu_context *smu,
1621 uint32_t *current_power_limit,
1622 uint32_t *default_power_limit,
1623 uint32_t *max_power_limit,
1624 uint32_t *min_power_limit)
1625 {
1626 struct smu_table_context *table_context = &smu->smu_table;
1627 PPTable_t *pptable = table_context->driver_pptable;
1628 CustomSkuTable_t *skutable = &pptable->CustomSkuTable;
1629 uint32_t power_limit;
1630 uint32_t msg_limit = pptable->SkuTable.MsgLimits.Power[PPT_THROTTLER_PPT0][POWER_SOURCE_AC];
1631
1632 if (smu_v14_0_get_current_power_limit(smu, &power_limit))
1633 power_limit = smu->adev->pm.ac_power ?
1634 skutable->SocketPowerLimitAc[PPT_THROTTLER_PPT0] :
1635 skutable->SocketPowerLimitDc[PPT_THROTTLER_PPT0];
1636
1637 if (current_power_limit)
1638 *current_power_limit = power_limit;
1639 if (default_power_limit)
1640 *default_power_limit = power_limit;
1641
1642 if (max_power_limit)
1643 *max_power_limit = msg_limit;
1644
1645 if (min_power_limit)
1646 *min_power_limit = 0;
1647
1648 return 0;
1649 }
1650
smu_v14_0_2_get_power_profile_mode(struct smu_context * smu,char * buf)1651 static int smu_v14_0_2_get_power_profile_mode(struct smu_context *smu,
1652 char *buf)
1653 {
1654 DpmActivityMonitorCoeffIntExternal_t activity_monitor_external;
1655 DpmActivityMonitorCoeffInt_t *activity_monitor =
1656 &(activity_monitor_external.DpmActivityMonitorCoeffInt);
1657 static const char *title[] = {
1658 "PROFILE_INDEX(NAME)",
1659 "CLOCK_TYPE(NAME)",
1660 "FPS",
1661 "MinActiveFreqType",
1662 "MinActiveFreq",
1663 "BoosterFreqType",
1664 "BoosterFreq",
1665 "PD_Data_limit_c",
1666 "PD_Data_error_coeff",
1667 "PD_Data_error_rate_coeff"};
1668 int16_t workload_type = 0;
1669 uint32_t i, size = 0;
1670 int result = 0;
1671
1672 if (!buf)
1673 return -EINVAL;
1674
1675 size += sysfs_emit_at(buf, size, "%16s %s %s %s %s %s %s %s %s %s\n",
1676 title[0], title[1], title[2], title[3], title[4], title[5],
1677 title[6], title[7], title[8], title[9]);
1678
1679 for (i = 0; i < PP_SMC_POWER_PROFILE_COUNT; i++) {
1680 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1681 workload_type = smu_cmn_to_asic_specific_index(smu,
1682 CMN2ASIC_MAPPING_WORKLOAD,
1683 i);
1684 if (workload_type == -ENOTSUPP)
1685 continue;
1686 else if (workload_type < 0)
1687 return -EINVAL;
1688
1689 result = smu_cmn_update_table(smu,
1690 SMU_TABLE_ACTIVITY_MONITOR_COEFF,
1691 workload_type,
1692 (void *)(&activity_monitor_external),
1693 false);
1694 if (result) {
1695 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
1696 return result;
1697 }
1698
1699 size += sysfs_emit_at(buf, size, "%2d %14s%s:\n",
1700 i, amdgpu_pp_profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
1701
1702 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d\n",
1703 " ",
1704 0,
1705 "GFXCLK",
1706 activity_monitor->Gfx_FPS,
1707 activity_monitor->Gfx_MinActiveFreqType,
1708 activity_monitor->Gfx_MinActiveFreq,
1709 activity_monitor->Gfx_BoosterFreqType,
1710 activity_monitor->Gfx_BoosterFreq,
1711 activity_monitor->Gfx_PD_Data_limit_c,
1712 activity_monitor->Gfx_PD_Data_error_coeff,
1713 activity_monitor->Gfx_PD_Data_error_rate_coeff);
1714
1715 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d\n",
1716 " ",
1717 1,
1718 "FCLK",
1719 activity_monitor->Fclk_FPS,
1720 activity_monitor->Fclk_MinActiveFreqType,
1721 activity_monitor->Fclk_MinActiveFreq,
1722 activity_monitor->Fclk_BoosterFreqType,
1723 activity_monitor->Fclk_BoosterFreq,
1724 activity_monitor->Fclk_PD_Data_limit_c,
1725 activity_monitor->Fclk_PD_Data_error_coeff,
1726 activity_monitor->Fclk_PD_Data_error_rate_coeff);
1727 }
1728
1729 return size;
1730 }
1731
smu_v14_0_2_set_power_profile_mode(struct smu_context * smu,long * input,uint32_t size)1732 static int smu_v14_0_2_set_power_profile_mode(struct smu_context *smu,
1733 long *input,
1734 uint32_t size)
1735 {
1736 DpmActivityMonitorCoeffIntExternal_t activity_monitor_external;
1737 DpmActivityMonitorCoeffInt_t *activity_monitor =
1738 &(activity_monitor_external.DpmActivityMonitorCoeffInt);
1739 int workload_type, ret = 0;
1740 uint32_t current_profile_mode = smu->power_profile_mode;
1741 smu->power_profile_mode = input[size];
1742
1743 if (smu->power_profile_mode >= PP_SMC_POWER_PROFILE_COUNT) {
1744 dev_err(smu->adev->dev, "Invalid power profile mode %d\n", smu->power_profile_mode);
1745 return -EINVAL;
1746 }
1747
1748 if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
1749 if (size != 9)
1750 return -EINVAL;
1751
1752 ret = smu_cmn_update_table(smu,
1753 SMU_TABLE_ACTIVITY_MONITOR_COEFF,
1754 WORKLOAD_PPLIB_CUSTOM_BIT,
1755 (void *)(&activity_monitor_external),
1756 false);
1757 if (ret) {
1758 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
1759 return ret;
1760 }
1761
1762 switch (input[0]) {
1763 case 0: /* Gfxclk */
1764 activity_monitor->Gfx_FPS = input[1];
1765 activity_monitor->Gfx_MinActiveFreqType = input[2];
1766 activity_monitor->Gfx_MinActiveFreq = input[3];
1767 activity_monitor->Gfx_BoosterFreqType = input[4];
1768 activity_monitor->Gfx_BoosterFreq = input[5];
1769 activity_monitor->Gfx_PD_Data_limit_c = input[6];
1770 activity_monitor->Gfx_PD_Data_error_coeff = input[7];
1771 activity_monitor->Gfx_PD_Data_error_rate_coeff = input[8];
1772 break;
1773 case 1: /* Fclk */
1774 activity_monitor->Fclk_FPS = input[1];
1775 activity_monitor->Fclk_MinActiveFreqType = input[2];
1776 activity_monitor->Fclk_MinActiveFreq = input[3];
1777 activity_monitor->Fclk_BoosterFreqType = input[4];
1778 activity_monitor->Fclk_BoosterFreq = input[5];
1779 activity_monitor->Fclk_PD_Data_limit_c = input[6];
1780 activity_monitor->Fclk_PD_Data_error_coeff = input[7];
1781 activity_monitor->Fclk_PD_Data_error_rate_coeff = input[8];
1782 break;
1783 default:
1784 return -EINVAL;
1785 }
1786
1787 ret = smu_cmn_update_table(smu,
1788 SMU_TABLE_ACTIVITY_MONITOR_COEFF,
1789 WORKLOAD_PPLIB_CUSTOM_BIT,
1790 (void *)(&activity_monitor_external),
1791 true);
1792 if (ret) {
1793 dev_err(smu->adev->dev, "[%s] Failed to set activity monitor!", __func__);
1794 return ret;
1795 }
1796 }
1797
1798 if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_COMPUTE)
1799 smu_v14_0_deep_sleep_control(smu, false);
1800 else if (current_profile_mode == PP_SMC_POWER_PROFILE_COMPUTE)
1801 smu_v14_0_deep_sleep_control(smu, true);
1802
1803 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1804 workload_type = smu_cmn_to_asic_specific_index(smu,
1805 CMN2ASIC_MAPPING_WORKLOAD,
1806 smu->power_profile_mode);
1807 if (workload_type < 0)
1808 return -EINVAL;
1809
1810 ret = smu_cmn_send_smc_msg_with_param(smu,
1811 SMU_MSG_SetWorkloadMask,
1812 1 << workload_type,
1813 NULL);
1814 if (!ret)
1815 smu->workload_mask = 1 << workload_type;
1816
1817 return ret;
1818 }
1819
smu_v14_0_2_baco_enter(struct smu_context * smu)1820 static int smu_v14_0_2_baco_enter(struct smu_context *smu)
1821 {
1822 struct smu_baco_context *smu_baco = &smu->smu_baco;
1823 struct amdgpu_device *adev = smu->adev;
1824
1825 if (adev->in_runpm && smu_cmn_is_audio_func_enabled(adev))
1826 return smu_v14_0_baco_set_armd3_sequence(smu,
1827 smu_baco->maco_support ? BACO_SEQ_BAMACO : BACO_SEQ_BACO);
1828 else
1829 return smu_v14_0_baco_enter(smu);
1830 }
1831
smu_v14_0_2_baco_exit(struct smu_context * smu)1832 static int smu_v14_0_2_baco_exit(struct smu_context *smu)
1833 {
1834 struct amdgpu_device *adev = smu->adev;
1835
1836 if (adev->in_runpm && smu_cmn_is_audio_func_enabled(adev)) {
1837 /* Wait for PMFW handling for the Dstate change */
1838 usleep_range(10000, 11000);
1839 return smu_v14_0_baco_set_armd3_sequence(smu, BACO_SEQ_ULPS);
1840 } else {
1841 return smu_v14_0_baco_exit(smu);
1842 }
1843 }
1844
smu_v14_0_2_is_mode1_reset_supported(struct smu_context * smu)1845 static bool smu_v14_0_2_is_mode1_reset_supported(struct smu_context *smu)
1846 {
1847 // TODO
1848
1849 return true;
1850 }
1851
smu_v14_0_2_i2c_xfer(struct i2c_adapter * i2c_adap,struct i2c_msg * msg,int num_msgs)1852 static int smu_v14_0_2_i2c_xfer(struct i2c_adapter *i2c_adap,
1853 struct i2c_msg *msg, int num_msgs)
1854 {
1855 struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(i2c_adap);
1856 struct amdgpu_device *adev = smu_i2c->adev;
1857 struct smu_context *smu = adev->powerplay.pp_handle;
1858 struct smu_table_context *smu_table = &smu->smu_table;
1859 struct smu_table *table = &smu_table->driver_table;
1860 SwI2cRequest_t *req, *res = (SwI2cRequest_t *)table->cpu_addr;
1861 int i, j, r, c;
1862 u16 dir;
1863
1864 if (!adev->pm.dpm_enabled)
1865 return -EBUSY;
1866
1867 req = kzalloc(sizeof(*req), GFP_KERNEL);
1868 if (!req)
1869 return -ENOMEM;
1870
1871 req->I2CcontrollerPort = smu_i2c->port;
1872 req->I2CSpeed = I2C_SPEED_FAST_400K;
1873 req->SlaveAddress = msg[0].addr << 1; /* wants an 8-bit address */
1874 dir = msg[0].flags & I2C_M_RD;
1875
1876 for (c = i = 0; i < num_msgs; i++) {
1877 for (j = 0; j < msg[i].len; j++, c++) {
1878 SwI2cCmd_t *cmd = &req->SwI2cCmds[c];
1879
1880 if (!(msg[i].flags & I2C_M_RD)) {
1881 /* write */
1882 cmd->CmdConfig |= CMDCONFIG_READWRITE_MASK;
1883 cmd->ReadWriteData = msg[i].buf[j];
1884 }
1885
1886 if ((dir ^ msg[i].flags) & I2C_M_RD) {
1887 /* The direction changes.
1888 */
1889 dir = msg[i].flags & I2C_M_RD;
1890 cmd->CmdConfig |= CMDCONFIG_RESTART_MASK;
1891 }
1892
1893 req->NumCmds++;
1894
1895 /*
1896 * Insert STOP if we are at the last byte of either last
1897 * message for the transaction or the client explicitly
1898 * requires a STOP at this particular message.
1899 */
1900 if ((j == msg[i].len - 1) &&
1901 ((i == num_msgs - 1) || (msg[i].flags & I2C_M_STOP))) {
1902 cmd->CmdConfig &= ~CMDCONFIG_RESTART_MASK;
1903 cmd->CmdConfig |= CMDCONFIG_STOP_MASK;
1904 }
1905 }
1906 }
1907 mutex_lock(&adev->pm.mutex);
1908 r = smu_cmn_update_table(smu, SMU_TABLE_I2C_COMMANDS, 0, req, true);
1909 mutex_unlock(&adev->pm.mutex);
1910 if (r)
1911 goto fail;
1912
1913 for (c = i = 0; i < num_msgs; i++) {
1914 if (!(msg[i].flags & I2C_M_RD)) {
1915 c += msg[i].len;
1916 continue;
1917 }
1918 for (j = 0; j < msg[i].len; j++, c++) {
1919 SwI2cCmd_t *cmd = &res->SwI2cCmds[c];
1920
1921 msg[i].buf[j] = cmd->ReadWriteData;
1922 }
1923 }
1924 r = num_msgs;
1925 fail:
1926 kfree(req);
1927 return r;
1928 }
1929
smu_v14_0_2_i2c_func(struct i2c_adapter * adap)1930 static u32 smu_v14_0_2_i2c_func(struct i2c_adapter *adap)
1931 {
1932 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
1933 }
1934
1935 static const struct i2c_algorithm smu_v14_0_2_i2c_algo = {
1936 .master_xfer = smu_v14_0_2_i2c_xfer,
1937 .functionality = smu_v14_0_2_i2c_func,
1938 };
1939
1940 static const struct i2c_adapter_quirks smu_v14_0_2_i2c_control_quirks = {
1941 .flags = I2C_AQ_COMB | I2C_AQ_COMB_SAME_ADDR | I2C_AQ_NO_ZERO_LEN,
1942 .max_read_len = MAX_SW_I2C_COMMANDS,
1943 .max_write_len = MAX_SW_I2C_COMMANDS,
1944 .max_comb_1st_msg_len = 2,
1945 .max_comb_2nd_msg_len = MAX_SW_I2C_COMMANDS - 2,
1946 };
1947
smu_v14_0_2_i2c_control_init(struct smu_context * smu)1948 static int smu_v14_0_2_i2c_control_init(struct smu_context *smu)
1949 {
1950 struct amdgpu_device *adev = smu->adev;
1951 int res, i;
1952
1953 for (i = 0; i < MAX_SMU_I2C_BUSES; i++) {
1954 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i];
1955 struct i2c_adapter *control = &smu_i2c->adapter;
1956
1957 smu_i2c->adev = adev;
1958 smu_i2c->port = i;
1959 mutex_init(&smu_i2c->mutex);
1960 control->owner = THIS_MODULE;
1961 control->dev.parent = &adev->pdev->dev;
1962 control->algo = &smu_v14_0_2_i2c_algo;
1963 snprintf(control->name, sizeof(control->name), "AMDGPU SMU %d", i);
1964 control->quirks = &smu_v14_0_2_i2c_control_quirks;
1965 i2c_set_adapdata(control, smu_i2c);
1966
1967 res = i2c_add_adapter(control);
1968 if (res) {
1969 DRM_ERROR("Failed to register hw i2c, err: %d\n", res);
1970 goto Out_err;
1971 }
1972 }
1973
1974 /* assign the buses used for the FRU EEPROM and RAS EEPROM */
1975 /* XXX ideally this would be something in a vbios data table */
1976 adev->pm.ras_eeprom_i2c_bus = &adev->pm.smu_i2c[1].adapter;
1977 adev->pm.fru_eeprom_i2c_bus = &adev->pm.smu_i2c[0].adapter;
1978
1979 return 0;
1980 Out_err:
1981 for ( ; i >= 0; i--) {
1982 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i];
1983 struct i2c_adapter *control = &smu_i2c->adapter;
1984
1985 i2c_del_adapter(control);
1986 }
1987 return res;
1988 }
1989
smu_v14_0_2_i2c_control_fini(struct smu_context * smu)1990 static void smu_v14_0_2_i2c_control_fini(struct smu_context *smu)
1991 {
1992 struct amdgpu_device *adev = smu->adev;
1993 int i;
1994
1995 for (i = 0; i < MAX_SMU_I2C_BUSES; i++) {
1996 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i];
1997 struct i2c_adapter *control = &smu_i2c->adapter;
1998
1999 i2c_del_adapter(control);
2000 }
2001 adev->pm.ras_eeprom_i2c_bus = NULL;
2002 adev->pm.fru_eeprom_i2c_bus = NULL;
2003 }
2004
smu_v14_0_2_set_mp1_state(struct smu_context * smu,enum pp_mp1_state mp1_state)2005 static int smu_v14_0_2_set_mp1_state(struct smu_context *smu,
2006 enum pp_mp1_state mp1_state)
2007 {
2008 int ret;
2009
2010 switch (mp1_state) {
2011 case PP_MP1_STATE_UNLOAD:
2012 ret = smu_cmn_set_mp1_state(smu, mp1_state);
2013 break;
2014 default:
2015 /* Ignore others */
2016 ret = 0;
2017 }
2018
2019 return ret;
2020 }
2021
smu_v14_0_2_set_df_cstate(struct smu_context * smu,enum pp_df_cstate state)2022 static int smu_v14_0_2_set_df_cstate(struct smu_context *smu,
2023 enum pp_df_cstate state)
2024 {
2025 return smu_cmn_send_smc_msg_with_param(smu,
2026 SMU_MSG_DFCstateControl,
2027 state,
2028 NULL);
2029 }
2030
smu_v14_0_2_mode1_reset(struct smu_context * smu)2031 static int smu_v14_0_2_mode1_reset(struct smu_context *smu)
2032 {
2033 int ret = 0;
2034
2035 ret = smu_cmn_send_debug_smc_msg(smu, DEBUGSMC_MSG_Mode1Reset);
2036 if (!ret) {
2037 if (amdgpu_emu_mode == 1)
2038 msleep(50000);
2039 else
2040 msleep(1000);
2041 }
2042
2043 return ret;
2044 }
2045
smu_v14_0_2_mode2_reset(struct smu_context * smu)2046 static int smu_v14_0_2_mode2_reset(struct smu_context *smu)
2047 {
2048 int ret = 0;
2049
2050 // TODO
2051
2052 return ret;
2053 }
2054
smu_v14_0_2_enable_gfx_features(struct smu_context * smu)2055 static int smu_v14_0_2_enable_gfx_features(struct smu_context *smu)
2056 {
2057 struct amdgpu_device *adev = smu->adev;
2058
2059 if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(14, 0, 2))
2060 return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_EnableAllSmuFeatures,
2061 FEATURE_PWR_GFX, NULL);
2062 else
2063 return -EOPNOTSUPP;
2064 }
2065
smu_v14_0_2_set_smu_mailbox_registers(struct smu_context * smu)2066 static void smu_v14_0_2_set_smu_mailbox_registers(struct smu_context *smu)
2067 {
2068 struct amdgpu_device *adev = smu->adev;
2069
2070 smu->param_reg = SOC15_REG_OFFSET(MP1, 0, regMP1_SMN_C2PMSG_82);
2071 smu->msg_reg = SOC15_REG_OFFSET(MP1, 0, regMP1_SMN_C2PMSG_66);
2072 smu->resp_reg = SOC15_REG_OFFSET(MP1, 0, regMP1_SMN_C2PMSG_90);
2073
2074 smu->debug_param_reg = SOC15_REG_OFFSET(MP1, 0, regMP1_SMN_C2PMSG_53);
2075 smu->debug_msg_reg = SOC15_REG_OFFSET(MP1, 0, regMP1_SMN_C2PMSG_75);
2076 smu->debug_resp_reg = SOC15_REG_OFFSET(MP1, 0, regMP1_SMN_C2PMSG_54);
2077 }
2078
smu_v14_0_2_get_gpu_metrics(struct smu_context * smu,void ** table)2079 static ssize_t smu_v14_0_2_get_gpu_metrics(struct smu_context *smu,
2080 void **table)
2081 {
2082 struct smu_table_context *smu_table = &smu->smu_table;
2083 struct gpu_metrics_v1_3 *gpu_metrics =
2084 (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table;
2085 SmuMetricsExternal_t metrics_ext;
2086 SmuMetrics_t *metrics = &metrics_ext.SmuMetrics;
2087 int ret = 0;
2088
2089 ret = smu_cmn_get_metrics_table(smu,
2090 &metrics_ext,
2091 true);
2092 if (ret)
2093 return ret;
2094
2095 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3);
2096
2097 gpu_metrics->temperature_edge = metrics->AvgTemperature[TEMP_EDGE];
2098 gpu_metrics->temperature_hotspot = metrics->AvgTemperature[TEMP_HOTSPOT];
2099 gpu_metrics->temperature_mem = metrics->AvgTemperature[TEMP_MEM];
2100 gpu_metrics->temperature_vrgfx = metrics->AvgTemperature[TEMP_VR_GFX];
2101 gpu_metrics->temperature_vrsoc = metrics->AvgTemperature[TEMP_VR_SOC];
2102 gpu_metrics->temperature_vrmem = max(metrics->AvgTemperature[TEMP_VR_MEM0],
2103 metrics->AvgTemperature[TEMP_VR_MEM1]);
2104
2105 gpu_metrics->average_gfx_activity = metrics->AverageGfxActivity;
2106 gpu_metrics->average_umc_activity = metrics->AverageUclkActivity;
2107 gpu_metrics->average_mm_activity = max(metrics->AverageVcn0ActivityPercentage,
2108 metrics->Vcn1ActivityPercentage);
2109
2110 gpu_metrics->average_socket_power = metrics->AverageSocketPower;
2111 gpu_metrics->energy_accumulator = metrics->EnergyAccumulator;
2112
2113 if (metrics->AverageGfxActivity <= SMU_14_0_2_BUSY_THRESHOLD)
2114 gpu_metrics->average_gfxclk_frequency = metrics->AverageGfxclkFrequencyPostDs;
2115 else
2116 gpu_metrics->average_gfxclk_frequency = metrics->AverageGfxclkFrequencyPreDs;
2117
2118 if (metrics->AverageUclkActivity <= SMU_14_0_2_BUSY_THRESHOLD)
2119 gpu_metrics->average_uclk_frequency = metrics->AverageMemclkFrequencyPostDs;
2120 else
2121 gpu_metrics->average_uclk_frequency = metrics->AverageMemclkFrequencyPreDs;
2122
2123 gpu_metrics->average_vclk0_frequency = metrics->AverageVclk0Frequency;
2124 gpu_metrics->average_dclk0_frequency = metrics->AverageDclk0Frequency;
2125 gpu_metrics->average_vclk1_frequency = metrics->AverageVclk1Frequency;
2126 gpu_metrics->average_dclk1_frequency = metrics->AverageDclk1Frequency;
2127
2128 gpu_metrics->current_gfxclk = gpu_metrics->average_gfxclk_frequency;
2129 gpu_metrics->current_socclk = metrics->CurrClock[PPCLK_SOCCLK];
2130 gpu_metrics->current_uclk = metrics->CurrClock[PPCLK_UCLK];
2131 gpu_metrics->current_vclk0 = metrics->CurrClock[PPCLK_VCLK_0];
2132 gpu_metrics->current_dclk0 = metrics->CurrClock[PPCLK_DCLK_0];
2133 gpu_metrics->current_vclk1 = metrics->CurrClock[PPCLK_VCLK_0];
2134 gpu_metrics->current_dclk1 = metrics->CurrClock[PPCLK_DCLK_0];
2135
2136 gpu_metrics->throttle_status =
2137 smu_v14_0_2_get_throttler_status(metrics);
2138 gpu_metrics->indep_throttle_status =
2139 smu_cmn_get_indep_throttler_status(gpu_metrics->throttle_status,
2140 smu_v14_0_2_throttler_map);
2141
2142 gpu_metrics->current_fan_speed = metrics->AvgFanRpm;
2143
2144 gpu_metrics->pcie_link_width = metrics->PcieWidth;
2145 if ((metrics->PcieRate - 1) > LINK_SPEED_MAX)
2146 gpu_metrics->pcie_link_speed = pcie_gen_to_speed(1);
2147 else
2148 gpu_metrics->pcie_link_speed = pcie_gen_to_speed(metrics->PcieRate);
2149
2150 gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
2151
2152 gpu_metrics->voltage_gfx = metrics->AvgVoltage[SVI_PLANE_VDD_GFX];
2153 gpu_metrics->voltage_soc = metrics->AvgVoltage[SVI_PLANE_VDD_SOC];
2154 gpu_metrics->voltage_mem = metrics->AvgVoltage[SVI_PLANE_VDDIO_MEM];
2155
2156 *table = (void *)gpu_metrics;
2157
2158 return sizeof(struct gpu_metrics_v1_3);
2159 }
2160
smu_v14_0_2_dump_od_table(struct smu_context * smu,OverDriveTableExternal_t * od_table)2161 static void smu_v14_0_2_dump_od_table(struct smu_context *smu,
2162 OverDriveTableExternal_t *od_table)
2163 {
2164 struct amdgpu_device *adev = smu->adev;
2165
2166 dev_dbg(adev->dev, "OD: Gfxclk offset: (%d)\n", od_table->OverDriveTable.GfxclkFoffset);
2167 dev_dbg(adev->dev, "OD: Uclk: (%d, %d)\n", od_table->OverDriveTable.UclkFmin,
2168 od_table->OverDriveTable.UclkFmax);
2169 }
2170
smu_v14_0_2_upload_overdrive_table(struct smu_context * smu,OverDriveTableExternal_t * od_table)2171 static int smu_v14_0_2_upload_overdrive_table(struct smu_context *smu,
2172 OverDriveTableExternal_t *od_table)
2173 {
2174 int ret;
2175 ret = smu_cmn_update_table(smu,
2176 SMU_TABLE_OVERDRIVE,
2177 0,
2178 (void *)od_table,
2179 true);
2180 if (ret)
2181 dev_err(smu->adev->dev, "Failed to upload overdrive table!\n");
2182
2183 return ret;
2184 }
2185
smu_v14_0_2_set_supported_od_feature_mask(struct smu_context * smu)2186 static void smu_v14_0_2_set_supported_od_feature_mask(struct smu_context *smu)
2187 {
2188 struct amdgpu_device *adev = smu->adev;
2189
2190 if (smu_v14_0_2_is_od_feature_supported(smu,
2191 PP_OD_FEATURE_FAN_CURVE_BIT))
2192 adev->pm.od_feature_mask |= OD_OPS_SUPPORT_FAN_CURVE_RETRIEVE |
2193 OD_OPS_SUPPORT_FAN_CURVE_SET |
2194 OD_OPS_SUPPORT_ACOUSTIC_LIMIT_THRESHOLD_RETRIEVE |
2195 OD_OPS_SUPPORT_ACOUSTIC_LIMIT_THRESHOLD_SET |
2196 OD_OPS_SUPPORT_ACOUSTIC_TARGET_THRESHOLD_RETRIEVE |
2197 OD_OPS_SUPPORT_ACOUSTIC_TARGET_THRESHOLD_SET |
2198 OD_OPS_SUPPORT_FAN_TARGET_TEMPERATURE_RETRIEVE |
2199 OD_OPS_SUPPORT_FAN_TARGET_TEMPERATURE_SET |
2200 OD_OPS_SUPPORT_FAN_MINIMUM_PWM_RETRIEVE |
2201 OD_OPS_SUPPORT_FAN_MINIMUM_PWM_SET;
2202 }
2203
smu_v14_0_2_get_overdrive_table(struct smu_context * smu,OverDriveTableExternal_t * od_table)2204 static int smu_v14_0_2_get_overdrive_table(struct smu_context *smu,
2205 OverDriveTableExternal_t *od_table)
2206 {
2207 int ret;
2208 ret = smu_cmn_update_table(smu,
2209 SMU_TABLE_OVERDRIVE,
2210 0,
2211 (void *)od_table,
2212 false);
2213 if (ret)
2214 dev_err(smu->adev->dev, "Failed to get overdrive table!\n");
2215
2216 return ret;
2217 }
2218
smu_v14_0_2_set_default_od_settings(struct smu_context * smu)2219 static int smu_v14_0_2_set_default_od_settings(struct smu_context *smu)
2220 {
2221 OverDriveTableExternal_t *od_table =
2222 (OverDriveTableExternal_t *)smu->smu_table.overdrive_table;
2223 OverDriveTableExternal_t *boot_od_table =
2224 (OverDriveTableExternal_t *)smu->smu_table.boot_overdrive_table;
2225 OverDriveTableExternal_t *user_od_table =
2226 (OverDriveTableExternal_t *)smu->smu_table.user_overdrive_table;
2227 OverDriveTableExternal_t user_od_table_bak;
2228 int ret;
2229 int i;
2230
2231 ret = smu_v14_0_2_get_overdrive_table(smu, boot_od_table);
2232 if (ret)
2233 return ret;
2234
2235 smu_v14_0_2_dump_od_table(smu, boot_od_table);
2236
2237 memcpy(od_table,
2238 boot_od_table,
2239 sizeof(OverDriveTableExternal_t));
2240
2241 /*
2242 * For S3/S4/Runpm resume, we need to setup those overdrive tables again,
2243 * but we have to preserve user defined values in "user_od_table".
2244 */
2245 if (!smu->adev->in_suspend) {
2246 memcpy(user_od_table,
2247 boot_od_table,
2248 sizeof(OverDriveTableExternal_t));
2249 smu->user_dpm_profile.user_od = false;
2250 } else if (smu->user_dpm_profile.user_od) {
2251 memcpy(&user_od_table_bak,
2252 user_od_table,
2253 sizeof(OverDriveTableExternal_t));
2254 memcpy(user_od_table,
2255 boot_od_table,
2256 sizeof(OverDriveTableExternal_t));
2257 user_od_table->OverDriveTable.GfxclkFoffset =
2258 user_od_table_bak.OverDriveTable.GfxclkFoffset;
2259 user_od_table->OverDriveTable.UclkFmin =
2260 user_od_table_bak.OverDriveTable.UclkFmin;
2261 user_od_table->OverDriveTable.UclkFmax =
2262 user_od_table_bak.OverDriveTable.UclkFmax;
2263 for (i = 0; i < PP_NUM_OD_VF_CURVE_POINTS; i++)
2264 user_od_table->OverDriveTable.VoltageOffsetPerZoneBoundary[i] =
2265 user_od_table_bak.OverDriveTable.VoltageOffsetPerZoneBoundary[i];
2266 for (i = 0; i < NUM_OD_FAN_MAX_POINTS - 1; i++) {
2267 user_od_table->OverDriveTable.FanLinearTempPoints[i] =
2268 user_od_table_bak.OverDriveTable.FanLinearTempPoints[i];
2269 user_od_table->OverDriveTable.FanLinearPwmPoints[i] =
2270 user_od_table_bak.OverDriveTable.FanLinearPwmPoints[i];
2271 }
2272 user_od_table->OverDriveTable.AcousticLimitRpmThreshold =
2273 user_od_table_bak.OverDriveTable.AcousticLimitRpmThreshold;
2274 user_od_table->OverDriveTable.AcousticTargetRpmThreshold =
2275 user_od_table_bak.OverDriveTable.AcousticTargetRpmThreshold;
2276 user_od_table->OverDriveTable.FanTargetTemperature =
2277 user_od_table_bak.OverDriveTable.FanTargetTemperature;
2278 user_od_table->OverDriveTable.FanMinimumPwm =
2279 user_od_table_bak.OverDriveTable.FanMinimumPwm;
2280 }
2281
2282 smu_v14_0_2_set_supported_od_feature_mask(smu);
2283
2284 return 0;
2285 }
2286
smu_v14_0_2_restore_user_od_settings(struct smu_context * smu)2287 static int smu_v14_0_2_restore_user_od_settings(struct smu_context *smu)
2288 {
2289 struct smu_table_context *table_context = &smu->smu_table;
2290 OverDriveTableExternal_t *od_table = table_context->overdrive_table;
2291 OverDriveTableExternal_t *user_od_table = table_context->user_overdrive_table;
2292 int res;
2293
2294 user_od_table->OverDriveTable.FeatureCtrlMask = BIT(PP_OD_FEATURE_GFXCLK_BIT) |
2295 BIT(PP_OD_FEATURE_UCLK_BIT) |
2296 BIT(PP_OD_FEATURE_GFX_VF_CURVE_BIT) |
2297 BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
2298 res = smu_v14_0_2_upload_overdrive_table(smu, user_od_table);
2299 user_od_table->OverDriveTable.FeatureCtrlMask = 0;
2300 if (res == 0)
2301 memcpy(od_table, user_od_table, sizeof(OverDriveTableExternal_t));
2302
2303 return res;
2304 }
2305
smu_v14_0_2_od_restore_table_single(struct smu_context * smu,long input)2306 static int smu_v14_0_2_od_restore_table_single(struct smu_context *smu, long input)
2307 {
2308 struct smu_table_context *table_context = &smu->smu_table;
2309 OverDriveTableExternal_t *boot_overdrive_table =
2310 (OverDriveTableExternal_t *)table_context->boot_overdrive_table;
2311 OverDriveTableExternal_t *od_table =
2312 (OverDriveTableExternal_t *)table_context->overdrive_table;
2313 struct amdgpu_device *adev = smu->adev;
2314 int i;
2315
2316 switch (input) {
2317 case PP_OD_EDIT_FAN_CURVE:
2318 for (i = 0; i < NUM_OD_FAN_MAX_POINTS; i++) {
2319 od_table->OverDriveTable.FanLinearTempPoints[i] =
2320 boot_overdrive_table->OverDriveTable.FanLinearTempPoints[i];
2321 od_table->OverDriveTable.FanLinearPwmPoints[i] =
2322 boot_overdrive_table->OverDriveTable.FanLinearPwmPoints[i];
2323 }
2324 od_table->OverDriveTable.FanMode = FAN_MODE_AUTO;
2325 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
2326 break;
2327 case PP_OD_EDIT_ACOUSTIC_LIMIT:
2328 od_table->OverDriveTable.AcousticLimitRpmThreshold =
2329 boot_overdrive_table->OverDriveTable.AcousticLimitRpmThreshold;
2330 od_table->OverDriveTable.FanMode = FAN_MODE_AUTO;
2331 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
2332 break;
2333 case PP_OD_EDIT_ACOUSTIC_TARGET:
2334 od_table->OverDriveTable.AcousticTargetRpmThreshold =
2335 boot_overdrive_table->OverDriveTable.AcousticTargetRpmThreshold;
2336 od_table->OverDriveTable.FanMode = FAN_MODE_AUTO;
2337 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
2338 break;
2339 case PP_OD_EDIT_FAN_TARGET_TEMPERATURE:
2340 od_table->OverDriveTable.FanTargetTemperature =
2341 boot_overdrive_table->OverDriveTable.FanTargetTemperature;
2342 od_table->OverDriveTable.FanMode = FAN_MODE_AUTO;
2343 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
2344 break;
2345 case PP_OD_EDIT_FAN_MINIMUM_PWM:
2346 od_table->OverDriveTable.FanMinimumPwm =
2347 boot_overdrive_table->OverDriveTable.FanMinimumPwm;
2348 od_table->OverDriveTable.FanMode = FAN_MODE_AUTO;
2349 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
2350 break;
2351 default:
2352 dev_info(adev->dev, "Invalid table index: %ld\n", input);
2353 return -EINVAL;
2354 }
2355
2356 return 0;
2357 }
2358
smu_v14_0_2_od_edit_dpm_table(struct smu_context * smu,enum PP_OD_DPM_TABLE_COMMAND type,long input[],uint32_t size)2359 static int smu_v14_0_2_od_edit_dpm_table(struct smu_context *smu,
2360 enum PP_OD_DPM_TABLE_COMMAND type,
2361 long input[],
2362 uint32_t size)
2363 {
2364 struct smu_table_context *table_context = &smu->smu_table;
2365 OverDriveTableExternal_t *od_table =
2366 (OverDriveTableExternal_t *)table_context->overdrive_table;
2367 struct amdgpu_device *adev = smu->adev;
2368 uint32_t offset_of_voltageoffset;
2369 int32_t minimum, maximum;
2370 uint32_t feature_ctrlmask;
2371 int i, ret = 0;
2372
2373 switch (type) {
2374 case PP_OD_EDIT_SCLK_VDDC_TABLE:
2375 if (!smu_v14_0_2_is_od_feature_supported(smu, PP_OD_FEATURE_GFXCLK_BIT)) {
2376 dev_warn(adev->dev, "GFXCLK_LIMITS setting not supported!\n");
2377 return -ENOTSUPP;
2378 }
2379
2380 for (i = 0; i < size; i += 2) {
2381 if (i + 2 > size) {
2382 dev_info(adev->dev, "invalid number of input parameters %d\n", size);
2383 return -EINVAL;
2384 }
2385
2386 switch (input[i]) {
2387 case 1:
2388 smu_v14_0_2_get_od_setting_limits(smu,
2389 PP_OD_FEATURE_GFXCLK_FMAX,
2390 &minimum,
2391 &maximum);
2392 if (input[i + 1] < minimum ||
2393 input[i + 1] > maximum) {
2394 dev_info(adev->dev, "GfxclkFmax (%ld) must be within [%u, %u]!\n",
2395 input[i + 1], minimum, maximum);
2396 return -EINVAL;
2397 }
2398
2399 od_table->OverDriveTable.GfxclkFoffset = input[i + 1];
2400 od_table->OverDriveTable.FeatureCtrlMask |= 1U << PP_OD_FEATURE_GFXCLK_BIT;
2401 break;
2402
2403 default:
2404 dev_info(adev->dev, "Invalid SCLK_VDDC_TABLE index: %ld\n", input[i]);
2405 dev_info(adev->dev, "Supported indices: [0:min,1:max]\n");
2406 return -EINVAL;
2407 }
2408 }
2409
2410 break;
2411
2412 case PP_OD_EDIT_MCLK_VDDC_TABLE:
2413 if (!smu_v14_0_2_is_od_feature_supported(smu, PP_OD_FEATURE_UCLK_BIT)) {
2414 dev_warn(adev->dev, "UCLK_LIMITS setting not supported!\n");
2415 return -ENOTSUPP;
2416 }
2417
2418 for (i = 0; i < size; i += 2) {
2419 if (i + 2 > size) {
2420 dev_info(adev->dev, "invalid number of input parameters %d\n", size);
2421 return -EINVAL;
2422 }
2423
2424 switch (input[i]) {
2425 case 0:
2426 smu_v14_0_2_get_od_setting_limits(smu,
2427 PP_OD_FEATURE_UCLK_FMIN,
2428 &minimum,
2429 &maximum);
2430 if (input[i + 1] < minimum ||
2431 input[i + 1] > maximum) {
2432 dev_info(adev->dev, "UclkFmin (%ld) must be within [%u, %u]!\n",
2433 input[i + 1], minimum, maximum);
2434 return -EINVAL;
2435 }
2436
2437 od_table->OverDriveTable.UclkFmin = input[i + 1];
2438 od_table->OverDriveTable.FeatureCtrlMask |= 1U << PP_OD_FEATURE_UCLK_BIT;
2439 break;
2440
2441 case 1:
2442 smu_v14_0_2_get_od_setting_limits(smu,
2443 PP_OD_FEATURE_UCLK_FMAX,
2444 &minimum,
2445 &maximum);
2446 if (input[i + 1] < minimum ||
2447 input[i + 1] > maximum) {
2448 dev_info(adev->dev, "UclkFmax (%ld) must be within [%u, %u]!\n",
2449 input[i + 1], minimum, maximum);
2450 return -EINVAL;
2451 }
2452
2453 od_table->OverDriveTable.UclkFmax = input[i + 1];
2454 od_table->OverDriveTable.FeatureCtrlMask |= 1U << PP_OD_FEATURE_UCLK_BIT;
2455 break;
2456
2457 default:
2458 dev_info(adev->dev, "Invalid MCLK_VDDC_TABLE index: %ld\n", input[i]);
2459 dev_info(adev->dev, "Supported indices: [0:min,1:max]\n");
2460 return -EINVAL;
2461 }
2462 }
2463
2464 if (od_table->OverDriveTable.UclkFmin > od_table->OverDriveTable.UclkFmax) {
2465 dev_err(adev->dev,
2466 "Invalid setting: UclkFmin(%u) is bigger than UclkFmax(%u)\n",
2467 (uint32_t)od_table->OverDriveTable.UclkFmin,
2468 (uint32_t)od_table->OverDriveTable.UclkFmax);
2469 return -EINVAL;
2470 }
2471 break;
2472
2473 case PP_OD_EDIT_VDDGFX_OFFSET:
2474 if (!smu_v14_0_2_is_od_feature_supported(smu, PP_OD_FEATURE_GFX_VF_CURVE_BIT)) {
2475 dev_warn(adev->dev, "Gfx offset setting not supported!\n");
2476 return -ENOTSUPP;
2477 }
2478
2479 smu_v14_0_2_get_od_setting_limits(smu,
2480 PP_OD_FEATURE_GFX_VF_CURVE,
2481 &minimum,
2482 &maximum);
2483 if (input[0] < minimum ||
2484 input[0] > maximum) {
2485 dev_info(adev->dev, "Voltage offset (%ld) must be within [%d, %d]!\n",
2486 input[0], minimum, maximum);
2487 return -EINVAL;
2488 }
2489
2490 for (i = 0; i < PP_NUM_OD_VF_CURVE_POINTS; i++)
2491 od_table->OverDriveTable.VoltageOffsetPerZoneBoundary[i] = input[0];
2492 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_GFX_VF_CURVE_BIT);
2493 break;
2494
2495 case PP_OD_EDIT_FAN_CURVE:
2496 if (!smu_v14_0_2_is_od_feature_supported(smu, PP_OD_FEATURE_FAN_CURVE_BIT)) {
2497 dev_warn(adev->dev, "Fan curve setting not supported!\n");
2498 return -ENOTSUPP;
2499 }
2500
2501 if (input[0] >= NUM_OD_FAN_MAX_POINTS - 1 ||
2502 input[0] < 0)
2503 return -EINVAL;
2504
2505 smu_v14_0_2_get_od_setting_limits(smu,
2506 PP_OD_FEATURE_FAN_CURVE_TEMP,
2507 &minimum,
2508 &maximum);
2509 if (input[1] < minimum ||
2510 input[1] > maximum) {
2511 dev_info(adev->dev, "Fan curve temp setting(%ld) must be within [%d, %d]!\n",
2512 input[1], minimum, maximum);
2513 return -EINVAL;
2514 }
2515
2516 smu_v14_0_2_get_od_setting_limits(smu,
2517 PP_OD_FEATURE_FAN_CURVE_PWM,
2518 &minimum,
2519 &maximum);
2520 if (input[2] < minimum ||
2521 input[2] > maximum) {
2522 dev_info(adev->dev, "Fan curve pwm setting(%ld) must be within [%d, %d]!\n",
2523 input[2], minimum, maximum);
2524 return -EINVAL;
2525 }
2526
2527 od_table->OverDriveTable.FanLinearTempPoints[input[0]] = input[1];
2528 od_table->OverDriveTable.FanLinearPwmPoints[input[0]] = input[2];
2529 od_table->OverDriveTable.FanMode = FAN_MODE_MANUAL_LINEAR;
2530 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
2531 break;
2532
2533 case PP_OD_EDIT_ACOUSTIC_LIMIT:
2534 if (!smu_v14_0_2_is_od_feature_supported(smu, PP_OD_FEATURE_FAN_CURVE_BIT)) {
2535 dev_warn(adev->dev, "Fan curve setting not supported!\n");
2536 return -ENOTSUPP;
2537 }
2538
2539 smu_v14_0_2_get_od_setting_limits(smu,
2540 PP_OD_FEATURE_FAN_ACOUSTIC_LIMIT,
2541 &minimum,
2542 &maximum);
2543 if (input[0] < minimum ||
2544 input[0] > maximum) {
2545 dev_info(adev->dev, "acoustic limit threshold setting(%ld) must be within [%d, %d]!\n",
2546 input[0], minimum, maximum);
2547 return -EINVAL;
2548 }
2549
2550 od_table->OverDriveTable.AcousticLimitRpmThreshold = input[0];
2551 od_table->OverDriveTable.FanMode = FAN_MODE_AUTO;
2552 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
2553 break;
2554
2555 case PP_OD_EDIT_ACOUSTIC_TARGET:
2556 if (!smu_v14_0_2_is_od_feature_supported(smu, PP_OD_FEATURE_FAN_CURVE_BIT)) {
2557 dev_warn(adev->dev, "Fan curve setting not supported!\n");
2558 return -ENOTSUPP;
2559 }
2560
2561 smu_v14_0_2_get_od_setting_limits(smu,
2562 PP_OD_FEATURE_FAN_ACOUSTIC_TARGET,
2563 &minimum,
2564 &maximum);
2565 if (input[0] < minimum ||
2566 input[0] > maximum) {
2567 dev_info(adev->dev, "acoustic target threshold setting(%ld) must be within [%d, %d]!\n",
2568 input[0], minimum, maximum);
2569 return -EINVAL;
2570 }
2571
2572 od_table->OverDriveTable.AcousticTargetRpmThreshold = input[0];
2573 od_table->OverDriveTable.FanMode = FAN_MODE_AUTO;
2574 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
2575 break;
2576
2577 case PP_OD_EDIT_FAN_TARGET_TEMPERATURE:
2578 if (!smu_v14_0_2_is_od_feature_supported(smu, PP_OD_FEATURE_FAN_CURVE_BIT)) {
2579 dev_warn(adev->dev, "Fan curve setting not supported!\n");
2580 return -ENOTSUPP;
2581 }
2582
2583 smu_v14_0_2_get_od_setting_limits(smu,
2584 PP_OD_FEATURE_FAN_TARGET_TEMPERATURE,
2585 &minimum,
2586 &maximum);
2587 if (input[0] < minimum ||
2588 input[0] > maximum) {
2589 dev_info(adev->dev, "fan target temperature setting(%ld) must be within [%d, %d]!\n",
2590 input[0], minimum, maximum);
2591 return -EINVAL;
2592 }
2593
2594 od_table->OverDriveTable.FanTargetTemperature = input[0];
2595 od_table->OverDriveTable.FanMode = FAN_MODE_AUTO;
2596 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
2597 break;
2598
2599 case PP_OD_EDIT_FAN_MINIMUM_PWM:
2600 if (!smu_v14_0_2_is_od_feature_supported(smu, PP_OD_FEATURE_FAN_CURVE_BIT)) {
2601 dev_warn(adev->dev, "Fan curve setting not supported!\n");
2602 return -ENOTSUPP;
2603 }
2604
2605 smu_v14_0_2_get_od_setting_limits(smu,
2606 PP_OD_FEATURE_FAN_MINIMUM_PWM,
2607 &minimum,
2608 &maximum);
2609 if (input[0] < minimum ||
2610 input[0] > maximum) {
2611 dev_info(adev->dev, "fan minimum pwm setting(%ld) must be within [%d, %d]!\n",
2612 input[0], minimum, maximum);
2613 return -EINVAL;
2614 }
2615
2616 od_table->OverDriveTable.FanMinimumPwm = input[0];
2617 od_table->OverDriveTable.FanMode = FAN_MODE_AUTO;
2618 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
2619 break;
2620
2621 case PP_OD_RESTORE_DEFAULT_TABLE:
2622 if (size == 1) {
2623 ret = smu_v14_0_2_od_restore_table_single(smu, input[0]);
2624 if (ret)
2625 return ret;
2626 } else {
2627 feature_ctrlmask = od_table->OverDriveTable.FeatureCtrlMask;
2628 memcpy(od_table,
2629 table_context->boot_overdrive_table,
2630 sizeof(OverDriveTableExternal_t));
2631 od_table->OverDriveTable.FeatureCtrlMask = feature_ctrlmask;
2632 }
2633 fallthrough;
2634 case PP_OD_COMMIT_DPM_TABLE:
2635 /*
2636 * The member below instructs PMFW the settings focused in
2637 * this single operation.
2638 * `uint32_t FeatureCtrlMask;`
2639 * It does not contain actual informations about user's custom
2640 * settings. Thus we do not cache it.
2641 */
2642 offset_of_voltageoffset = offsetof(OverDriveTable_t, VoltageOffsetPerZoneBoundary);
2643 if (memcmp((u8 *)od_table + offset_of_voltageoffset,
2644 table_context->user_overdrive_table + offset_of_voltageoffset,
2645 sizeof(OverDriveTableExternal_t) - offset_of_voltageoffset)) {
2646 smu_v14_0_2_dump_od_table(smu, od_table);
2647
2648 ret = smu_v14_0_2_upload_overdrive_table(smu, od_table);
2649 if (ret) {
2650 dev_err(adev->dev, "Failed to upload overdrive table!\n");
2651 return ret;
2652 }
2653
2654 od_table->OverDriveTable.FeatureCtrlMask = 0;
2655 memcpy(table_context->user_overdrive_table + offset_of_voltageoffset,
2656 (u8 *)od_table + offset_of_voltageoffset,
2657 sizeof(OverDriveTableExternal_t) - offset_of_voltageoffset);
2658
2659 if (!memcmp(table_context->user_overdrive_table,
2660 table_context->boot_overdrive_table,
2661 sizeof(OverDriveTableExternal_t)))
2662 smu->user_dpm_profile.user_od = false;
2663 else
2664 smu->user_dpm_profile.user_od = true;
2665 }
2666 break;
2667
2668 default:
2669 return -ENOSYS;
2670 }
2671
2672 return ret;
2673 }
2674
smu_v14_0_2_set_power_limit(struct smu_context * smu,enum smu_ppt_limit_type limit_type,uint32_t limit)2675 static int smu_v14_0_2_set_power_limit(struct smu_context *smu,
2676 enum smu_ppt_limit_type limit_type,
2677 uint32_t limit)
2678 {
2679 PPTable_t *pptable = smu->smu_table.driver_pptable;
2680 uint32_t msg_limit = pptable->SkuTable.MsgLimits.Power[PPT_THROTTLER_PPT0][POWER_SOURCE_AC];
2681 struct smu_table_context *table_context = &smu->smu_table;
2682 OverDriveTableExternal_t *od_table =
2683 (OverDriveTableExternal_t *)table_context->overdrive_table;
2684 int ret = 0;
2685
2686 if (limit_type != SMU_DEFAULT_PPT_LIMIT)
2687 return -EINVAL;
2688
2689 if (limit <= msg_limit) {
2690 if (smu->current_power_limit > msg_limit) {
2691 od_table->OverDriveTable.Ppt = 0;
2692 od_table->OverDriveTable.FeatureCtrlMask |= 1U << PP_OD_FEATURE_PPT_BIT;
2693
2694 ret = smu_v14_0_2_upload_overdrive_table(smu, od_table);
2695 if (ret) {
2696 dev_err(smu->adev->dev, "Failed to upload overdrive table!\n");
2697 return ret;
2698 }
2699 }
2700 return smu_v14_0_set_power_limit(smu, limit_type, limit);
2701 } else if (smu->od_enabled) {
2702 ret = smu_v14_0_set_power_limit(smu, limit_type, msg_limit);
2703 if (ret)
2704 return ret;
2705
2706 od_table->OverDriveTable.Ppt = (limit * 100) / msg_limit - 100;
2707 od_table->OverDriveTable.FeatureCtrlMask |= 1U << PP_OD_FEATURE_PPT_BIT;
2708
2709 ret = smu_v14_0_2_upload_overdrive_table(smu, od_table);
2710 if (ret) {
2711 dev_err(smu->adev->dev, "Failed to upload overdrive table!\n");
2712 return ret;
2713 }
2714
2715 smu->current_power_limit = limit;
2716 } else {
2717 return -EINVAL;
2718 }
2719
2720 return 0;
2721 }
2722
2723 static const struct pptable_funcs smu_v14_0_2_ppt_funcs = {
2724 .get_allowed_feature_mask = smu_v14_0_2_get_allowed_feature_mask,
2725 .set_default_dpm_table = smu_v14_0_2_set_default_dpm_table,
2726 .i2c_init = smu_v14_0_2_i2c_control_init,
2727 .i2c_fini = smu_v14_0_2_i2c_control_fini,
2728 .is_dpm_running = smu_v14_0_2_is_dpm_running,
2729 .dump_pptable = smu_v14_0_2_dump_pptable,
2730 .init_microcode = smu_v14_0_init_microcode,
2731 .load_microcode = smu_v14_0_load_microcode,
2732 .fini_microcode = smu_v14_0_fini_microcode,
2733 .init_smc_tables = smu_v14_0_2_init_smc_tables,
2734 .fini_smc_tables = smu_v14_0_fini_smc_tables,
2735 .init_power = smu_v14_0_init_power,
2736 .fini_power = smu_v14_0_fini_power,
2737 .check_fw_status = smu_v14_0_check_fw_status,
2738 .setup_pptable = smu_v14_0_2_setup_pptable,
2739 .check_fw_version = smu_v14_0_check_fw_version,
2740 .set_driver_table_location = smu_v14_0_set_driver_table_location,
2741 .system_features_control = smu_v14_0_system_features_control,
2742 .set_allowed_mask = smu_v14_0_set_allowed_mask,
2743 .get_enabled_mask = smu_cmn_get_enabled_mask,
2744 .dpm_set_vcn_enable = smu_v14_0_set_vcn_enable,
2745 .dpm_set_jpeg_enable = smu_v14_0_set_jpeg_enable,
2746 .get_dpm_ultimate_freq = smu_v14_0_2_get_dpm_ultimate_freq,
2747 .get_vbios_bootup_values = smu_v14_0_get_vbios_bootup_values,
2748 .read_sensor = smu_v14_0_2_read_sensor,
2749 .feature_is_enabled = smu_cmn_feature_is_enabled,
2750 .print_clk_levels = smu_v14_0_2_print_clk_levels,
2751 .force_clk_levels = smu_v14_0_2_force_clk_levels,
2752 .update_pcie_parameters = smu_v14_0_2_update_pcie_parameters,
2753 .get_thermal_temperature_range = smu_v14_0_2_get_thermal_temperature_range,
2754 .register_irq_handler = smu_v14_0_register_irq_handler,
2755 .enable_thermal_alert = smu_v14_0_enable_thermal_alert,
2756 .disable_thermal_alert = smu_v14_0_disable_thermal_alert,
2757 .notify_memory_pool_location = smu_v14_0_notify_memory_pool_location,
2758 .get_gpu_metrics = smu_v14_0_2_get_gpu_metrics,
2759 .set_soft_freq_limited_range = smu_v14_0_set_soft_freq_limited_range,
2760 .set_default_od_settings = smu_v14_0_2_set_default_od_settings,
2761 .restore_user_od_settings = smu_v14_0_2_restore_user_od_settings,
2762 .od_edit_dpm_table = smu_v14_0_2_od_edit_dpm_table,
2763 .init_pptable_microcode = smu_v14_0_init_pptable_microcode,
2764 .populate_umd_state_clk = smu_v14_0_2_populate_umd_state_clk,
2765 .set_performance_level = smu_v14_0_set_performance_level,
2766 .gfx_off_control = smu_v14_0_gfx_off_control,
2767 .get_unique_id = smu_v14_0_2_get_unique_id,
2768 .get_power_limit = smu_v14_0_2_get_power_limit,
2769 .set_power_limit = smu_v14_0_2_set_power_limit,
2770 .set_power_source = smu_v14_0_set_power_source,
2771 .get_power_profile_mode = smu_v14_0_2_get_power_profile_mode,
2772 .set_power_profile_mode = smu_v14_0_2_set_power_profile_mode,
2773 .run_btc = smu_v14_0_run_btc,
2774 .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
2775 .set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
2776 .set_tool_table_location = smu_v14_0_set_tool_table_location,
2777 .deep_sleep_control = smu_v14_0_deep_sleep_control,
2778 .gfx_ulv_control = smu_v14_0_gfx_ulv_control,
2779 .get_bamaco_support = smu_v14_0_get_bamaco_support,
2780 .baco_get_state = smu_v14_0_baco_get_state,
2781 .baco_set_state = smu_v14_0_baco_set_state,
2782 .baco_enter = smu_v14_0_2_baco_enter,
2783 .baco_exit = smu_v14_0_2_baco_exit,
2784 .mode1_reset_is_support = smu_v14_0_2_is_mode1_reset_supported,
2785 .mode1_reset = smu_v14_0_2_mode1_reset,
2786 .mode2_reset = smu_v14_0_2_mode2_reset,
2787 .enable_gfx_features = smu_v14_0_2_enable_gfx_features,
2788 .set_mp1_state = smu_v14_0_2_set_mp1_state,
2789 .set_df_cstate = smu_v14_0_2_set_df_cstate,
2790 #if 0
2791 .gpo_control = smu_v14_0_gpo_control,
2792 #endif
2793 };
2794
smu_v14_0_2_set_ppt_funcs(struct smu_context * smu)2795 void smu_v14_0_2_set_ppt_funcs(struct smu_context *smu)
2796 {
2797 smu->ppt_funcs = &smu_v14_0_2_ppt_funcs;
2798 smu->message_map = smu_v14_0_2_message_map;
2799 smu->clock_map = smu_v14_0_2_clk_map;
2800 smu->feature_map = smu_v14_0_2_feature_mask_map;
2801 smu->table_map = smu_v14_0_2_table_map;
2802 smu->pwr_src_map = smu_v14_0_2_pwr_src_map;
2803 smu->workload_map = smu_v14_0_2_workload_map;
2804 smu_v14_0_2_set_smu_mailbox_registers(smu);
2805 }
2806