1 /*
2 * Copyright 2020 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include <linux/firmware.h>
24 #include <linux/module.h>
25 #include <linux/pci.h>
26 #include <linux/reboot.h>
27
28 #define SMU_13_0_PARTIAL_PPTABLE
29 #define SWSMU_CODE_LAYER_L3
30
31 #include "amdgpu.h"
32 #include "amdgpu_smu.h"
33 #include "atomfirmware.h"
34 #include "amdgpu_atomfirmware.h"
35 #include "amdgpu_atombios.h"
36 #include "smu_v13_0.h"
37 #include "soc15_common.h"
38 #include "atom.h"
39 #include "amdgpu_ras.h"
40 #include "smu_cmn.h"
41
42 #include "asic_reg/thm/thm_13_0_2_offset.h"
43 #include "asic_reg/thm/thm_13_0_2_sh_mask.h"
44 #include "asic_reg/mp/mp_13_0_2_offset.h"
45 #include "asic_reg/mp/mp_13_0_2_sh_mask.h"
46 #include "asic_reg/smuio/smuio_13_0_2_offset.h"
47 #include "asic_reg/smuio/smuio_13_0_2_sh_mask.h"
48
49 /*
50 * DO NOT use these for err/warn/info/debug messages.
51 * Use dev_err, dev_warn, dev_info and dev_dbg instead.
52 * They are more MGPU friendly.
53 */
54 #undef pr_err
55 #undef pr_warn
56 #undef pr_info
57 #undef pr_debug
58
59 MODULE_FIRMWARE("amdgpu/aldebaran_smc.bin");
60 MODULE_FIRMWARE("amdgpu/smu_13_0_0.bin");
61 MODULE_FIRMWARE("amdgpu/smu_13_0_7.bin");
62 MODULE_FIRMWARE("amdgpu/smu_13_0_10.bin");
63
64 #define mmMP1_SMN_C2PMSG_66 0x0282
65 #define mmMP1_SMN_C2PMSG_66_BASE_IDX 0
66
67 #define mmMP1_SMN_C2PMSG_82 0x0292
68 #define mmMP1_SMN_C2PMSG_82_BASE_IDX 0
69
70 #define mmMP1_SMN_C2PMSG_90 0x029a
71 #define mmMP1_SMN_C2PMSG_90_BASE_IDX 0
72
73 #define SMU13_VOLTAGE_SCALE 4
74
75 #define LINK_WIDTH_MAX 6
76 #define LINK_SPEED_MAX 3
77
78 #define smnPCIE_LC_LINK_WIDTH_CNTL 0x11140288
79 #define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x00000070L
80 #define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4
81 #define smnPCIE_LC_SPEED_CNTL 0x11140290
82 #define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0xE0
83 #define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0x5
84
85 #define ENABLE_IMU_ARG_GFXOFF_ENABLE 1
86
87 static const int link_width[] = {0, 1, 2, 4, 8, 12, 16};
88
89 const int pmfw_decoded_link_speed[5] = {1, 2, 3, 4, 5};
90 const int pmfw_decoded_link_width[7] = {0, 1, 2, 4, 8, 12, 16};
91
smu_v13_0_init_microcode(struct smu_context * smu)92 int smu_v13_0_init_microcode(struct smu_context *smu)
93 {
94 struct amdgpu_device *adev = smu->adev;
95 char ucode_prefix[15];
96 int err = 0;
97 const struct smc_firmware_header_v1_0 *hdr;
98 const struct common_firmware_header *header;
99 struct amdgpu_firmware_info *ucode = NULL;
100
101 /* doesn't need to load smu firmware in IOV mode */
102 if (amdgpu_sriov_vf(adev))
103 return 0;
104
105 amdgpu_ucode_ip_version_decode(adev, MP1_HWIP, ucode_prefix, sizeof(ucode_prefix));
106 err = amdgpu_ucode_request(adev, &adev->pm.fw, "amdgpu/%s.bin", ucode_prefix);
107 if (err)
108 goto out;
109
110 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
111 amdgpu_ucode_print_smc_hdr(&hdr->header);
112 adev->pm.fw_version = le32_to_cpu(hdr->header.ucode_version);
113
114 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
115 ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC];
116 ucode->ucode_id = AMDGPU_UCODE_ID_SMC;
117 ucode->fw = adev->pm.fw;
118 header = (const struct common_firmware_header *)ucode->fw->data;
119 adev->firmware.fw_size +=
120 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
121 }
122
123 out:
124 if (err)
125 amdgpu_ucode_release(&adev->pm.fw);
126 return err;
127 }
128
smu_v13_0_fini_microcode(struct smu_context * smu)129 void smu_v13_0_fini_microcode(struct smu_context *smu)
130 {
131 struct amdgpu_device *adev = smu->adev;
132
133 amdgpu_ucode_release(&adev->pm.fw);
134 adev->pm.fw_version = 0;
135 }
136
smu_v13_0_load_microcode(struct smu_context * smu)137 int smu_v13_0_load_microcode(struct smu_context *smu)
138 {
139 #if 0
140 struct amdgpu_device *adev = smu->adev;
141 const uint32_t *src;
142 const struct smc_firmware_header_v1_0 *hdr;
143 uint32_t addr_start = MP1_SRAM;
144 uint32_t i;
145 uint32_t smc_fw_size;
146 uint32_t mp1_fw_flags;
147
148 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
149 src = (const uint32_t *)(adev->pm.fw->data +
150 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
151 smc_fw_size = hdr->header.ucode_size_bytes;
152
153 for (i = 1; i < smc_fw_size/4 - 1; i++) {
154 WREG32_PCIE(addr_start, src[i]);
155 addr_start += 4;
156 }
157
158 WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
159 1 & MP1_SMN_PUB_CTRL__RESET_MASK);
160 WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
161 1 & ~MP1_SMN_PUB_CTRL__RESET_MASK);
162
163 for (i = 0; i < adev->usec_timeout; i++) {
164 mp1_fw_flags = RREG32_PCIE(MP1_Public |
165 (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
166 if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
167 MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
168 break;
169 udelay(1);
170 }
171
172 if (i == adev->usec_timeout)
173 return -ETIME;
174 #endif
175
176 return 0;
177 }
178
smu_v13_0_init_pptable_microcode(struct smu_context * smu)179 int smu_v13_0_init_pptable_microcode(struct smu_context *smu)
180 {
181 struct amdgpu_device *adev = smu->adev;
182 struct amdgpu_firmware_info *ucode = NULL;
183 uint32_t size = 0, pptable_id = 0;
184 int ret = 0;
185 void *table;
186
187 /* doesn't need to load smu firmware in IOV mode */
188 if (amdgpu_sriov_vf(adev))
189 return 0;
190
191 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
192 return 0;
193
194 if (!adev->scpm_enabled)
195 return 0;
196
197 if ((amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 7)) ||
198 (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 0)) ||
199 (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 10)))
200 return 0;
201
202 /* override pptable_id from driver parameter */
203 if (amdgpu_smu_pptable_id >= 0) {
204 pptable_id = amdgpu_smu_pptable_id;
205 dev_info(adev->dev, "override pptable id %d\n", pptable_id);
206 } else {
207 pptable_id = smu->smu_table.boot_values.pp_table_id;
208 }
209
210 /* "pptable_id == 0" means vbios carries the pptable. */
211 if (!pptable_id)
212 return 0;
213
214 ret = smu_v13_0_get_pptable_from_firmware(smu, &table, &size, pptable_id);
215 if (ret)
216 return ret;
217
218 smu->pptable_firmware.data = table;
219 smu->pptable_firmware.size = size;
220
221 ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_PPTABLE];
222 ucode->ucode_id = AMDGPU_UCODE_ID_PPTABLE;
223 ucode->fw = &smu->pptable_firmware;
224 adev->firmware.fw_size +=
225 ALIGN(smu->pptable_firmware.size, PAGE_SIZE);
226
227 return 0;
228 }
229
smu_v13_0_check_fw_status(struct smu_context * smu)230 int smu_v13_0_check_fw_status(struct smu_context *smu)
231 {
232 struct amdgpu_device *adev = smu->adev;
233 uint32_t mp1_fw_flags;
234
235 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
236 case IP_VERSION(13, 0, 4):
237 case IP_VERSION(13, 0, 11):
238 mp1_fw_flags = RREG32_PCIE(MP1_Public |
239 (smnMP1_V13_0_4_FIRMWARE_FLAGS & 0xffffffff));
240 break;
241 default:
242 mp1_fw_flags = RREG32_PCIE(MP1_Public |
243 (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
244 break;
245 }
246
247 if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
248 MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
249 return 0;
250
251 return -EIO;
252 }
253
smu_v13_0_check_fw_version(struct smu_context * smu)254 int smu_v13_0_check_fw_version(struct smu_context *smu)
255 {
256 struct amdgpu_device *adev = smu->adev;
257 uint32_t if_version = 0xff, smu_version = 0xff;
258 uint8_t smu_program, smu_major, smu_minor, smu_debug;
259 int ret = 0;
260
261 ret = smu_cmn_get_smc_version(smu, &if_version, &smu_version);
262 if (ret)
263 return ret;
264
265 smu_program = (smu_version >> 24) & 0xff;
266 smu_major = (smu_version >> 16) & 0xff;
267 smu_minor = (smu_version >> 8) & 0xff;
268 smu_debug = (smu_version >> 0) & 0xff;
269 if (smu->is_apu ||
270 amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 6) ||
271 amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 14))
272 adev->pm.fw_version = smu_version;
273
274 /* only for dGPU w/ SMU13*/
275 if (adev->pm.fw)
276 dev_dbg(smu->adev->dev, "smu fw reported program %d, version = 0x%08x (%d.%d.%d)\n",
277 smu_program, smu_version, smu_major, smu_minor, smu_debug);
278
279 /*
280 * 1. if_version mismatch is not critical as our fw is designed
281 * to be backward compatible.
282 * 2. New fw usually brings some optimizations. But that's visible
283 * only on the paired driver.
284 * Considering above, we just leave user a verbal message instead
285 * of halt driver loading.
286 */
287 if (if_version != smu->smc_driver_if_version) {
288 dev_info(adev->dev, "smu driver if version = 0x%08x, smu fw if version = 0x%08x, "
289 "smu fw program = %d, smu fw version = 0x%08x (%d.%d.%d)\n",
290 smu->smc_driver_if_version, if_version,
291 smu_program, smu_version, smu_major, smu_minor, smu_debug);
292 dev_info(adev->dev, "SMU driver if version not matched\n");
293 }
294
295 return ret;
296 }
297
smu_v13_0_set_pptable_v2_0(struct smu_context * smu,void ** table,uint32_t * size)298 static int smu_v13_0_set_pptable_v2_0(struct smu_context *smu, void **table, uint32_t *size)
299 {
300 struct amdgpu_device *adev = smu->adev;
301 uint32_t ppt_offset_bytes;
302 const struct smc_firmware_header_v2_0 *v2;
303
304 v2 = (const struct smc_firmware_header_v2_0 *) adev->pm.fw->data;
305
306 ppt_offset_bytes = le32_to_cpu(v2->ppt_offset_bytes);
307 *size = le32_to_cpu(v2->ppt_size_bytes);
308 *table = (uint8_t *)v2 + ppt_offset_bytes;
309
310 return 0;
311 }
312
smu_v13_0_set_pptable_v2_1(struct smu_context * smu,void ** table,uint32_t * size,uint32_t pptable_id)313 static int smu_v13_0_set_pptable_v2_1(struct smu_context *smu, void **table,
314 uint32_t *size, uint32_t pptable_id)
315 {
316 struct amdgpu_device *adev = smu->adev;
317 const struct smc_firmware_header_v2_1 *v2_1;
318 struct smc_soft_pptable_entry *entries;
319 uint32_t pptable_count = 0;
320 int i = 0;
321
322 v2_1 = (const struct smc_firmware_header_v2_1 *) adev->pm.fw->data;
323 entries = (struct smc_soft_pptable_entry *)
324 ((uint8_t *)v2_1 + le32_to_cpu(v2_1->pptable_entry_offset));
325 pptable_count = le32_to_cpu(v2_1->pptable_count);
326 for (i = 0; i < pptable_count; i++) {
327 if (le32_to_cpu(entries[i].id) == pptable_id) {
328 *table = ((uint8_t *)v2_1 + le32_to_cpu(entries[i].ppt_offset_bytes));
329 *size = le32_to_cpu(entries[i].ppt_size_bytes);
330 break;
331 }
332 }
333
334 if (i == pptable_count)
335 return -EINVAL;
336
337 return 0;
338 }
339
smu_v13_0_get_pptable_from_vbios(struct smu_context * smu,void ** table,uint32_t * size)340 static int smu_v13_0_get_pptable_from_vbios(struct smu_context *smu, void **table, uint32_t *size)
341 {
342 struct amdgpu_device *adev = smu->adev;
343 uint16_t atom_table_size;
344 uint8_t frev, crev;
345 int ret, index;
346
347 dev_info(adev->dev, "use vbios provided pptable\n");
348 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
349 powerplayinfo);
350
351 ret = amdgpu_atombios_get_data_table(adev, index, &atom_table_size, &frev, &crev,
352 (uint8_t **)table);
353 if (ret)
354 return ret;
355
356 if (size)
357 *size = atom_table_size;
358
359 return 0;
360 }
361
smu_v13_0_get_pptable_from_firmware(struct smu_context * smu,void ** table,uint32_t * size,uint32_t pptable_id)362 int smu_v13_0_get_pptable_from_firmware(struct smu_context *smu,
363 void **table,
364 uint32_t *size,
365 uint32_t pptable_id)
366 {
367 const struct smc_firmware_header_v1_0 *hdr;
368 struct amdgpu_device *adev = smu->adev;
369 uint16_t version_major, version_minor;
370 int ret;
371
372 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
373 if (!hdr)
374 return -EINVAL;
375
376 dev_info(adev->dev, "use driver provided pptable %d\n", pptable_id);
377
378 version_major = le16_to_cpu(hdr->header.header_version_major);
379 version_minor = le16_to_cpu(hdr->header.header_version_minor);
380 if (version_major != 2) {
381 dev_err(adev->dev, "Unsupported smu firmware version %d.%d\n",
382 version_major, version_minor);
383 return -EINVAL;
384 }
385
386 switch (version_minor) {
387 case 0:
388 ret = smu_v13_0_set_pptable_v2_0(smu, table, size);
389 break;
390 case 1:
391 ret = smu_v13_0_set_pptable_v2_1(smu, table, size, pptable_id);
392 break;
393 default:
394 ret = -EINVAL;
395 break;
396 }
397
398 return ret;
399 }
400
smu_v13_0_setup_pptable(struct smu_context * smu)401 int smu_v13_0_setup_pptable(struct smu_context *smu)
402 {
403 struct amdgpu_device *adev = smu->adev;
404 uint32_t size = 0, pptable_id = 0;
405 void *table;
406 int ret = 0;
407
408 /* override pptable_id from driver parameter */
409 if (amdgpu_smu_pptable_id >= 0) {
410 pptable_id = amdgpu_smu_pptable_id;
411 dev_info(adev->dev, "override pptable id %d\n", pptable_id);
412 } else {
413 pptable_id = smu->smu_table.boot_values.pp_table_id;
414 }
415
416 /* force using vbios pptable in sriov mode */
417 if ((amdgpu_sriov_vf(adev) || !pptable_id) && (amdgpu_emu_mode != 1))
418 ret = smu_v13_0_get_pptable_from_vbios(smu, &table, &size);
419 else
420 ret = smu_v13_0_get_pptable_from_firmware(smu, &table, &size, pptable_id);
421
422 if (ret)
423 return ret;
424
425 if (!smu->smu_table.power_play_table)
426 smu->smu_table.power_play_table = table;
427 if (!smu->smu_table.power_play_table_size)
428 smu->smu_table.power_play_table_size = size;
429
430 return 0;
431 }
432
smu_v13_0_init_smc_tables(struct smu_context * smu)433 int smu_v13_0_init_smc_tables(struct smu_context *smu)
434 {
435 struct smu_table_context *smu_table = &smu->smu_table;
436 struct smu_table *tables = smu_table->tables;
437 int ret = 0;
438
439 smu_table->driver_pptable =
440 kzalloc(tables[SMU_TABLE_PPTABLE].size, GFP_KERNEL);
441 if (!smu_table->driver_pptable) {
442 ret = -ENOMEM;
443 goto err0_out;
444 }
445
446 smu_table->max_sustainable_clocks =
447 kzalloc(sizeof(struct smu_13_0_max_sustainable_clocks), GFP_KERNEL);
448 if (!smu_table->max_sustainable_clocks) {
449 ret = -ENOMEM;
450 goto err1_out;
451 }
452
453 /* Aldebaran does not support OVERDRIVE */
454 if (tables[SMU_TABLE_OVERDRIVE].size) {
455 smu_table->overdrive_table =
456 kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL);
457 if (!smu_table->overdrive_table) {
458 ret = -ENOMEM;
459 goto err2_out;
460 }
461
462 smu_table->boot_overdrive_table =
463 kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL);
464 if (!smu_table->boot_overdrive_table) {
465 ret = -ENOMEM;
466 goto err3_out;
467 }
468
469 smu_table->user_overdrive_table =
470 kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL);
471 if (!smu_table->user_overdrive_table) {
472 ret = -ENOMEM;
473 goto err4_out;
474 }
475 }
476
477 smu_table->combo_pptable =
478 kzalloc(tables[SMU_TABLE_COMBO_PPTABLE].size, GFP_KERNEL);
479 if (!smu_table->combo_pptable) {
480 ret = -ENOMEM;
481 goto err5_out;
482 }
483
484 return 0;
485
486 err5_out:
487 kfree(smu_table->user_overdrive_table);
488 err4_out:
489 kfree(smu_table->boot_overdrive_table);
490 err3_out:
491 kfree(smu_table->overdrive_table);
492 err2_out:
493 kfree(smu_table->max_sustainable_clocks);
494 err1_out:
495 kfree(smu_table->driver_pptable);
496 err0_out:
497 return ret;
498 }
499
smu_v13_0_fini_smc_tables(struct smu_context * smu)500 int smu_v13_0_fini_smc_tables(struct smu_context *smu)
501 {
502 struct smu_table_context *smu_table = &smu->smu_table;
503 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
504
505 kfree(smu_table->gpu_metrics_table);
506 kfree(smu_table->combo_pptable);
507 kfree(smu_table->user_overdrive_table);
508 kfree(smu_table->boot_overdrive_table);
509 kfree(smu_table->overdrive_table);
510 kfree(smu_table->max_sustainable_clocks);
511 kfree(smu_table->driver_pptable);
512 smu_table->gpu_metrics_table = NULL;
513 smu_table->combo_pptable = NULL;
514 smu_table->user_overdrive_table = NULL;
515 smu_table->boot_overdrive_table = NULL;
516 smu_table->overdrive_table = NULL;
517 smu_table->max_sustainable_clocks = NULL;
518 smu_table->driver_pptable = NULL;
519 kfree(smu_table->hardcode_pptable);
520 smu_table->hardcode_pptable = NULL;
521
522 kfree(smu_table->ecc_table);
523 kfree(smu_table->metrics_table);
524 kfree(smu_table->watermarks_table);
525 smu_table->ecc_table = NULL;
526 smu_table->metrics_table = NULL;
527 smu_table->watermarks_table = NULL;
528 smu_table->metrics_time = 0;
529
530 kfree(smu_dpm->dpm_policies);
531 kfree(smu_dpm->dpm_context);
532 kfree(smu_dpm->golden_dpm_context);
533 kfree(smu_dpm->dpm_current_power_state);
534 kfree(smu_dpm->dpm_request_power_state);
535 smu_dpm->dpm_policies = NULL;
536 smu_dpm->dpm_context = NULL;
537 smu_dpm->golden_dpm_context = NULL;
538 smu_dpm->dpm_context_size = 0;
539 smu_dpm->dpm_current_power_state = NULL;
540 smu_dpm->dpm_request_power_state = NULL;
541
542 return 0;
543 }
544
smu_v13_0_init_power(struct smu_context * smu)545 int smu_v13_0_init_power(struct smu_context *smu)
546 {
547 struct smu_power_context *smu_power = &smu->smu_power;
548
549 if (smu_power->power_context || smu_power->power_context_size != 0)
550 return -EINVAL;
551
552 smu_power->power_context = kzalloc(sizeof(struct smu_13_0_power_context),
553 GFP_KERNEL);
554 if (!smu_power->power_context)
555 return -ENOMEM;
556 smu_power->power_context_size = sizeof(struct smu_13_0_power_context);
557
558 return 0;
559 }
560
smu_v13_0_fini_power(struct smu_context * smu)561 int smu_v13_0_fini_power(struct smu_context *smu)
562 {
563 struct smu_power_context *smu_power = &smu->smu_power;
564
565 if (!smu_power->power_context || smu_power->power_context_size == 0)
566 return -EINVAL;
567
568 kfree(smu_power->power_context);
569 smu_power->power_context = NULL;
570 smu_power->power_context_size = 0;
571
572 return 0;
573 }
574
smu_v13_0_get_vbios_bootup_values(struct smu_context * smu)575 int smu_v13_0_get_vbios_bootup_values(struct smu_context *smu)
576 {
577 int ret, index;
578 uint16_t size;
579 uint8_t frev, crev;
580 struct atom_common_table_header *header;
581 struct atom_firmware_info_v3_4 *v_3_4;
582 struct atom_firmware_info_v3_3 *v_3_3;
583 struct atom_firmware_info_v3_1 *v_3_1;
584 struct atom_smu_info_v3_6 *smu_info_v3_6;
585 struct atom_smu_info_v4_0 *smu_info_v4_0;
586
587 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
588 firmwareinfo);
589
590 ret = amdgpu_atombios_get_data_table(smu->adev, index, &size, &frev, &crev,
591 (uint8_t **)&header);
592 if (ret)
593 return ret;
594
595 if (header->format_revision != 3) {
596 dev_err(smu->adev->dev, "unknown atom_firmware_info version! for smu13\n");
597 return -EINVAL;
598 }
599
600 switch (header->content_revision) {
601 case 0:
602 case 1:
603 case 2:
604 v_3_1 = (struct atom_firmware_info_v3_1 *)header;
605 smu->smu_table.boot_values.revision = v_3_1->firmware_revision;
606 smu->smu_table.boot_values.gfxclk = v_3_1->bootup_sclk_in10khz;
607 smu->smu_table.boot_values.uclk = v_3_1->bootup_mclk_in10khz;
608 smu->smu_table.boot_values.socclk = 0;
609 smu->smu_table.boot_values.dcefclk = 0;
610 smu->smu_table.boot_values.vddc = v_3_1->bootup_vddc_mv;
611 smu->smu_table.boot_values.vddci = v_3_1->bootup_vddci_mv;
612 smu->smu_table.boot_values.mvddc = v_3_1->bootup_mvddc_mv;
613 smu->smu_table.boot_values.vdd_gfx = v_3_1->bootup_vddgfx_mv;
614 smu->smu_table.boot_values.cooling_id = v_3_1->coolingsolution_id;
615 smu->smu_table.boot_values.pp_table_id = 0;
616 break;
617 case 3:
618 v_3_3 = (struct atom_firmware_info_v3_3 *)header;
619 smu->smu_table.boot_values.revision = v_3_3->firmware_revision;
620 smu->smu_table.boot_values.gfxclk = v_3_3->bootup_sclk_in10khz;
621 smu->smu_table.boot_values.uclk = v_3_3->bootup_mclk_in10khz;
622 smu->smu_table.boot_values.socclk = 0;
623 smu->smu_table.boot_values.dcefclk = 0;
624 smu->smu_table.boot_values.vddc = v_3_3->bootup_vddc_mv;
625 smu->smu_table.boot_values.vddci = v_3_3->bootup_vddci_mv;
626 smu->smu_table.boot_values.mvddc = v_3_3->bootup_mvddc_mv;
627 smu->smu_table.boot_values.vdd_gfx = v_3_3->bootup_vddgfx_mv;
628 smu->smu_table.boot_values.cooling_id = v_3_3->coolingsolution_id;
629 smu->smu_table.boot_values.pp_table_id = v_3_3->pplib_pptable_id;
630 break;
631 case 4:
632 default:
633 v_3_4 = (struct atom_firmware_info_v3_4 *)header;
634 smu->smu_table.boot_values.revision = v_3_4->firmware_revision;
635 smu->smu_table.boot_values.gfxclk = v_3_4->bootup_sclk_in10khz;
636 smu->smu_table.boot_values.uclk = v_3_4->bootup_mclk_in10khz;
637 smu->smu_table.boot_values.socclk = 0;
638 smu->smu_table.boot_values.dcefclk = 0;
639 smu->smu_table.boot_values.vddc = v_3_4->bootup_vddc_mv;
640 smu->smu_table.boot_values.vddci = v_3_4->bootup_vddci_mv;
641 smu->smu_table.boot_values.mvddc = v_3_4->bootup_mvddc_mv;
642 smu->smu_table.boot_values.vdd_gfx = v_3_4->bootup_vddgfx_mv;
643 smu->smu_table.boot_values.cooling_id = v_3_4->coolingsolution_id;
644 smu->smu_table.boot_values.pp_table_id = v_3_4->pplib_pptable_id;
645 break;
646 }
647
648 smu->smu_table.boot_values.format_revision = header->format_revision;
649 smu->smu_table.boot_values.content_revision = header->content_revision;
650
651 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
652 smu_info);
653 if (!amdgpu_atombios_get_data_table(smu->adev, index, &size, &frev, &crev,
654 (uint8_t **)&header)) {
655
656 if ((frev == 3) && (crev == 6)) {
657 smu_info_v3_6 = (struct atom_smu_info_v3_6 *)header;
658
659 smu->smu_table.boot_values.socclk = smu_info_v3_6->bootup_socclk_10khz;
660 smu->smu_table.boot_values.vclk = smu_info_v3_6->bootup_vclk_10khz;
661 smu->smu_table.boot_values.dclk = smu_info_v3_6->bootup_dclk_10khz;
662 smu->smu_table.boot_values.fclk = smu_info_v3_6->bootup_fclk_10khz;
663 } else if ((frev == 3) && (crev == 1)) {
664 return 0;
665 } else if ((frev == 4) && (crev == 0)) {
666 smu_info_v4_0 = (struct atom_smu_info_v4_0 *)header;
667
668 smu->smu_table.boot_values.socclk = smu_info_v4_0->bootup_socclk_10khz;
669 smu->smu_table.boot_values.dcefclk = smu_info_v4_0->bootup_dcefclk_10khz;
670 smu->smu_table.boot_values.vclk = smu_info_v4_0->bootup_vclk0_10khz;
671 smu->smu_table.boot_values.dclk = smu_info_v4_0->bootup_dclk0_10khz;
672 smu->smu_table.boot_values.fclk = smu_info_v4_0->bootup_fclk_10khz;
673 } else {
674 dev_warn(smu->adev->dev, "Unexpected and unhandled version: %d.%d\n",
675 (uint32_t)frev, (uint32_t)crev);
676 }
677 }
678
679 return 0;
680 }
681
682
smu_v13_0_notify_memory_pool_location(struct smu_context * smu)683 int smu_v13_0_notify_memory_pool_location(struct smu_context *smu)
684 {
685 struct smu_table_context *smu_table = &smu->smu_table;
686 struct smu_table *memory_pool = &smu_table->memory_pool;
687 int ret = 0;
688 uint64_t address;
689 uint32_t address_low, address_high;
690
691 if (memory_pool->size == 0 || memory_pool->cpu_addr == NULL)
692 return ret;
693
694 address = memory_pool->mc_address;
695 address_high = (uint32_t)upper_32_bits(address);
696 address_low = (uint32_t)lower_32_bits(address);
697
698 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrHigh,
699 address_high, NULL);
700 if (ret)
701 return ret;
702 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrLow,
703 address_low, NULL);
704 if (ret)
705 return ret;
706 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramSize,
707 (uint32_t)memory_pool->size, NULL);
708 if (ret)
709 return ret;
710
711 return ret;
712 }
713
smu_v13_0_set_min_deep_sleep_dcefclk(struct smu_context * smu,uint32_t clk)714 int smu_v13_0_set_min_deep_sleep_dcefclk(struct smu_context *smu, uint32_t clk)
715 {
716 int ret;
717
718 ret = smu_cmn_send_smc_msg_with_param(smu,
719 SMU_MSG_SetMinDeepSleepDcefclk, clk, NULL);
720 if (ret)
721 dev_err(smu->adev->dev, "SMU13 attempt to set divider for DCEFCLK Failed!");
722
723 return ret;
724 }
725
smu_v13_0_set_driver_table_location(struct smu_context * smu)726 int smu_v13_0_set_driver_table_location(struct smu_context *smu)
727 {
728 struct smu_table *driver_table = &smu->smu_table.driver_table;
729 int ret = 0;
730
731 if (driver_table->mc_address) {
732 ret = smu_cmn_send_smc_msg_with_param(smu,
733 SMU_MSG_SetDriverDramAddrHigh,
734 upper_32_bits(driver_table->mc_address),
735 NULL);
736 if (!ret)
737 ret = smu_cmn_send_smc_msg_with_param(smu,
738 SMU_MSG_SetDriverDramAddrLow,
739 lower_32_bits(driver_table->mc_address),
740 NULL);
741 }
742
743 return ret;
744 }
745
smu_v13_0_set_tool_table_location(struct smu_context * smu)746 int smu_v13_0_set_tool_table_location(struct smu_context *smu)
747 {
748 int ret = 0;
749 struct smu_table *tool_table = &smu->smu_table.tables[SMU_TABLE_PMSTATUSLOG];
750
751 if (tool_table->mc_address) {
752 ret = smu_cmn_send_smc_msg_with_param(smu,
753 SMU_MSG_SetToolsDramAddrHigh,
754 upper_32_bits(tool_table->mc_address),
755 NULL);
756 if (!ret)
757 ret = smu_cmn_send_smc_msg_with_param(smu,
758 SMU_MSG_SetToolsDramAddrLow,
759 lower_32_bits(tool_table->mc_address),
760 NULL);
761 }
762
763 return ret;
764 }
765
smu_v13_0_init_display_count(struct smu_context * smu,uint32_t count)766 int smu_v13_0_init_display_count(struct smu_context *smu, uint32_t count)
767 {
768 int ret = 0;
769
770 if (!smu->pm_enabled)
771 return ret;
772
773 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, count, NULL);
774
775 return ret;
776 }
777
smu_v13_0_set_allowed_mask(struct smu_context * smu)778 int smu_v13_0_set_allowed_mask(struct smu_context *smu)
779 {
780 struct smu_feature *feature = &smu->smu_feature;
781 int ret = 0;
782 uint32_t feature_mask[2];
783
784 if (bitmap_empty(feature->allowed, SMU_FEATURE_MAX) ||
785 feature->feature_num < 64)
786 return -EINVAL;
787
788 bitmap_to_arr32(feature_mask, feature->allowed, 64);
789
790 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskHigh,
791 feature_mask[1], NULL);
792 if (ret)
793 return ret;
794
795 return smu_cmn_send_smc_msg_with_param(smu,
796 SMU_MSG_SetAllowedFeaturesMaskLow,
797 feature_mask[0],
798 NULL);
799 }
800
smu_v13_0_gfx_off_control(struct smu_context * smu,bool enable)801 int smu_v13_0_gfx_off_control(struct smu_context *smu, bool enable)
802 {
803 int ret = 0;
804 struct amdgpu_device *adev = smu->adev;
805
806 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
807 case IP_VERSION(13, 0, 0):
808 case IP_VERSION(13, 0, 1):
809 case IP_VERSION(13, 0, 3):
810 case IP_VERSION(13, 0, 4):
811 case IP_VERSION(13, 0, 5):
812 case IP_VERSION(13, 0, 7):
813 case IP_VERSION(13, 0, 8):
814 case IP_VERSION(13, 0, 10):
815 case IP_VERSION(13, 0, 11):
816 if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
817 return 0;
818 if (enable)
819 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_AllowGfxOff, NULL);
820 else
821 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_DisallowGfxOff, NULL);
822 break;
823 default:
824 break;
825 }
826
827 return ret;
828 }
829
smu_v13_0_system_features_control(struct smu_context * smu,bool en)830 int smu_v13_0_system_features_control(struct smu_context *smu,
831 bool en)
832 {
833 return smu_cmn_send_smc_msg(smu, (en ? SMU_MSG_EnableAllSmuFeatures :
834 SMU_MSG_DisableAllSmuFeatures), NULL);
835 }
836
smu_v13_0_notify_display_change(struct smu_context * smu)837 int smu_v13_0_notify_display_change(struct smu_context *smu)
838 {
839 int ret = 0;
840
841 if (!amdgpu_device_has_dc_support(smu->adev))
842 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_DALNotPresent, NULL);
843
844 return ret;
845 }
846
847 static int
smu_v13_0_get_max_sustainable_clock(struct smu_context * smu,uint32_t * clock,enum smu_clk_type clock_select)848 smu_v13_0_get_max_sustainable_clock(struct smu_context *smu, uint32_t *clock,
849 enum smu_clk_type clock_select)
850 {
851 int ret = 0;
852 int clk_id;
853
854 if ((smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, SMU_MSG_GetDcModeMaxDpmFreq) < 0) ||
855 (smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, SMU_MSG_GetMaxDpmFreq) < 0))
856 return 0;
857
858 clk_id = smu_cmn_to_asic_specific_index(smu,
859 CMN2ASIC_MAPPING_CLK,
860 clock_select);
861 if (clk_id < 0)
862 return -EINVAL;
863
864 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetDcModeMaxDpmFreq,
865 clk_id << 16, clock);
866 if (ret) {
867 dev_err(smu->adev->dev, "[GetMaxSustainableClock] Failed to get max DC clock from SMC!");
868 return ret;
869 }
870
871 if (*clock != 0)
872 return 0;
873
874 /* if DC limit is zero, return AC limit */
875 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq,
876 clk_id << 16, clock);
877 if (ret) {
878 dev_err(smu->adev->dev, "[GetMaxSustainableClock] failed to get max AC clock from SMC!");
879 return ret;
880 }
881
882 return 0;
883 }
884
smu_v13_0_init_max_sustainable_clocks(struct smu_context * smu)885 int smu_v13_0_init_max_sustainable_clocks(struct smu_context *smu)
886 {
887 struct smu_13_0_max_sustainable_clocks *max_sustainable_clocks =
888 smu->smu_table.max_sustainable_clocks;
889 int ret = 0;
890
891 max_sustainable_clocks->uclock = smu->smu_table.boot_values.uclk / 100;
892 max_sustainable_clocks->soc_clock = smu->smu_table.boot_values.socclk / 100;
893 max_sustainable_clocks->dcef_clock = smu->smu_table.boot_values.dcefclk / 100;
894 max_sustainable_clocks->display_clock = 0xFFFFFFFF;
895 max_sustainable_clocks->phy_clock = 0xFFFFFFFF;
896 max_sustainable_clocks->pixel_clock = 0xFFFFFFFF;
897
898 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
899 ret = smu_v13_0_get_max_sustainable_clock(smu,
900 &(max_sustainable_clocks->uclock),
901 SMU_UCLK);
902 if (ret) {
903 dev_err(smu->adev->dev, "[%s] failed to get max UCLK from SMC!",
904 __func__);
905 return ret;
906 }
907 }
908
909 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
910 ret = smu_v13_0_get_max_sustainable_clock(smu,
911 &(max_sustainable_clocks->soc_clock),
912 SMU_SOCCLK);
913 if (ret) {
914 dev_err(smu->adev->dev, "[%s] failed to get max SOCCLK from SMC!",
915 __func__);
916 return ret;
917 }
918 }
919
920 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
921 ret = smu_v13_0_get_max_sustainable_clock(smu,
922 &(max_sustainable_clocks->dcef_clock),
923 SMU_DCEFCLK);
924 if (ret) {
925 dev_err(smu->adev->dev, "[%s] failed to get max DCEFCLK from SMC!",
926 __func__);
927 return ret;
928 }
929
930 ret = smu_v13_0_get_max_sustainable_clock(smu,
931 &(max_sustainable_clocks->display_clock),
932 SMU_DISPCLK);
933 if (ret) {
934 dev_err(smu->adev->dev, "[%s] failed to get max DISPCLK from SMC!",
935 __func__);
936 return ret;
937 }
938 ret = smu_v13_0_get_max_sustainable_clock(smu,
939 &(max_sustainable_clocks->phy_clock),
940 SMU_PHYCLK);
941 if (ret) {
942 dev_err(smu->adev->dev, "[%s] failed to get max PHYCLK from SMC!",
943 __func__);
944 return ret;
945 }
946 ret = smu_v13_0_get_max_sustainable_clock(smu,
947 &(max_sustainable_clocks->pixel_clock),
948 SMU_PIXCLK);
949 if (ret) {
950 dev_err(smu->adev->dev, "[%s] failed to get max PIXCLK from SMC!",
951 __func__);
952 return ret;
953 }
954 }
955
956 if (max_sustainable_clocks->soc_clock < max_sustainable_clocks->uclock)
957 max_sustainable_clocks->uclock = max_sustainable_clocks->soc_clock;
958
959 return 0;
960 }
961
smu_v13_0_get_current_power_limit(struct smu_context * smu,uint32_t * power_limit)962 int smu_v13_0_get_current_power_limit(struct smu_context *smu,
963 uint32_t *power_limit)
964 {
965 int power_src;
966 int ret = 0;
967
968 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT))
969 return -EINVAL;
970
971 power_src = smu_cmn_to_asic_specific_index(smu,
972 CMN2ASIC_MAPPING_PWR,
973 smu->adev->pm.ac_power ?
974 SMU_POWER_SOURCE_AC :
975 SMU_POWER_SOURCE_DC);
976 if (power_src < 0)
977 return -EINVAL;
978
979 ret = smu_cmn_send_smc_msg_with_param(smu,
980 SMU_MSG_GetPptLimit,
981 power_src << 16,
982 power_limit);
983 if (ret)
984 dev_err(smu->adev->dev, "[%s] get PPT limit failed!", __func__);
985
986 return ret;
987 }
988
smu_v13_0_set_power_limit(struct smu_context * smu,enum smu_ppt_limit_type limit_type,uint32_t limit)989 int smu_v13_0_set_power_limit(struct smu_context *smu,
990 enum smu_ppt_limit_type limit_type,
991 uint32_t limit)
992 {
993 int ret = 0;
994
995 if (limit_type != SMU_DEFAULT_PPT_LIMIT)
996 return -EINVAL;
997
998 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) {
999 dev_err(smu->adev->dev, "Setting new power limit is not supported!\n");
1000 return -EOPNOTSUPP;
1001 }
1002
1003 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetPptLimit, limit, NULL);
1004 if (ret) {
1005 dev_err(smu->adev->dev, "[%s] Set power limit Failed!\n", __func__);
1006 return ret;
1007 }
1008
1009 smu->current_power_limit = limit;
1010
1011 return 0;
1012 }
1013
smu_v13_0_allow_ih_interrupt(struct smu_context * smu)1014 static int smu_v13_0_allow_ih_interrupt(struct smu_context *smu)
1015 {
1016 return smu_cmn_send_smc_msg(smu,
1017 SMU_MSG_AllowIHHostInterrupt,
1018 NULL);
1019 }
1020
smu_v13_0_process_pending_interrupt(struct smu_context * smu)1021 static int smu_v13_0_process_pending_interrupt(struct smu_context *smu)
1022 {
1023 int ret = 0;
1024
1025 if (smu->dc_controlled_by_gpio &&
1026 smu_cmn_feature_is_enabled(smu, SMU_FEATURE_ACDC_BIT))
1027 ret = smu_v13_0_allow_ih_interrupt(smu);
1028
1029 return ret;
1030 }
1031
smu_v13_0_enable_thermal_alert(struct smu_context * smu)1032 int smu_v13_0_enable_thermal_alert(struct smu_context *smu)
1033 {
1034 int ret = 0;
1035
1036 if (!smu->irq_source.num_types)
1037 return 0;
1038
1039 ret = amdgpu_irq_get(smu->adev, &smu->irq_source, 0);
1040 if (ret)
1041 return ret;
1042
1043 return smu_v13_0_process_pending_interrupt(smu);
1044 }
1045
smu_v13_0_disable_thermal_alert(struct smu_context * smu)1046 int smu_v13_0_disable_thermal_alert(struct smu_context *smu)
1047 {
1048 if (!smu->irq_source.num_types)
1049 return 0;
1050
1051 return amdgpu_irq_put(smu->adev, &smu->irq_source, 0);
1052 }
1053
convert_to_vddc(uint8_t vid)1054 static uint16_t convert_to_vddc(uint8_t vid)
1055 {
1056 return (uint16_t) ((6200 - (vid * 25)) / SMU13_VOLTAGE_SCALE);
1057 }
1058
smu_v13_0_get_gfx_vdd(struct smu_context * smu,uint32_t * value)1059 int smu_v13_0_get_gfx_vdd(struct smu_context *smu, uint32_t *value)
1060 {
1061 struct amdgpu_device *adev = smu->adev;
1062 uint32_t vdd = 0, val_vid = 0;
1063
1064 if (!value)
1065 return -EINVAL;
1066 val_vid = (RREG32_SOC15(SMUIO, 0, regSMUSVI0_TEL_PLANE0) &
1067 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR_MASK) >>
1068 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR__SHIFT;
1069
1070 vdd = (uint32_t)convert_to_vddc((uint8_t)val_vid);
1071
1072 *value = vdd;
1073
1074 return 0;
1075
1076 }
1077
1078 int
smu_v13_0_display_clock_voltage_request(struct smu_context * smu,struct pp_display_clock_request * clock_req)1079 smu_v13_0_display_clock_voltage_request(struct smu_context *smu,
1080 struct pp_display_clock_request
1081 *clock_req)
1082 {
1083 enum amd_pp_clock_type clk_type = clock_req->clock_type;
1084 int ret = 0;
1085 enum smu_clk_type clk_select = 0;
1086 uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000;
1087
1088 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) ||
1089 smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1090 switch (clk_type) {
1091 case amd_pp_dcef_clock:
1092 clk_select = SMU_DCEFCLK;
1093 break;
1094 case amd_pp_disp_clock:
1095 clk_select = SMU_DISPCLK;
1096 break;
1097 case amd_pp_pixel_clock:
1098 clk_select = SMU_PIXCLK;
1099 break;
1100 case amd_pp_phy_clock:
1101 clk_select = SMU_PHYCLK;
1102 break;
1103 case amd_pp_mem_clock:
1104 clk_select = SMU_UCLK;
1105 break;
1106 default:
1107 dev_info(smu->adev->dev, "[%s] Invalid Clock Type!", __func__);
1108 ret = -EINVAL;
1109 break;
1110 }
1111
1112 if (ret)
1113 goto failed;
1114
1115 if (clk_select == SMU_UCLK && smu->disable_uclk_switch)
1116 return 0;
1117
1118 ret = smu_v13_0_set_hard_freq_limited_range(smu, clk_select, clk_freq, 0);
1119
1120 if (clk_select == SMU_UCLK)
1121 smu->hard_min_uclk_req_from_dal = clk_freq;
1122 }
1123
1124 failed:
1125 return ret;
1126 }
1127
smu_v13_0_get_fan_control_mode(struct smu_context * smu)1128 uint32_t smu_v13_0_get_fan_control_mode(struct smu_context *smu)
1129 {
1130 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT))
1131 return AMD_FAN_CTRL_MANUAL;
1132 else
1133 return AMD_FAN_CTRL_AUTO;
1134 }
1135
1136 static int
smu_v13_0_auto_fan_control(struct smu_context * smu,bool auto_fan_control)1137 smu_v13_0_auto_fan_control(struct smu_context *smu, bool auto_fan_control)
1138 {
1139 int ret = 0;
1140
1141 if (!smu_cmn_feature_is_supported(smu, SMU_FEATURE_FAN_CONTROL_BIT))
1142 return 0;
1143
1144 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT, auto_fan_control);
1145 if (ret)
1146 dev_err(smu->adev->dev, "[%s]%s smc FAN CONTROL feature failed!",
1147 __func__, (auto_fan_control ? "Start" : "Stop"));
1148
1149 return ret;
1150 }
1151
1152 static int
smu_v13_0_set_fan_static_mode(struct smu_context * smu,uint32_t mode)1153 smu_v13_0_set_fan_static_mode(struct smu_context *smu, uint32_t mode)
1154 {
1155 struct amdgpu_device *adev = smu->adev;
1156
1157 WREG32_SOC15(THM, 0, regCG_FDO_CTRL2,
1158 REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL2),
1159 CG_FDO_CTRL2, TMIN, 0));
1160 WREG32_SOC15(THM, 0, regCG_FDO_CTRL2,
1161 REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL2),
1162 CG_FDO_CTRL2, FDO_PWM_MODE, mode));
1163
1164 return 0;
1165 }
1166
smu_v13_0_set_fan_speed_pwm(struct smu_context * smu,uint32_t speed)1167 int smu_v13_0_set_fan_speed_pwm(struct smu_context *smu,
1168 uint32_t speed)
1169 {
1170 struct amdgpu_device *adev = smu->adev;
1171 uint32_t duty100, duty;
1172 uint64_t tmp64;
1173
1174 speed = min_t(uint32_t, speed, 255);
1175
1176 if (smu_v13_0_auto_fan_control(smu, 0))
1177 return -EINVAL;
1178
1179 duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL1),
1180 CG_FDO_CTRL1, FMAX_DUTY100);
1181 if (!duty100)
1182 return -EINVAL;
1183
1184 tmp64 = (uint64_t)speed * duty100;
1185 do_div(tmp64, 255);
1186 duty = (uint32_t)tmp64;
1187
1188 WREG32_SOC15(THM, 0, regCG_FDO_CTRL0,
1189 REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL0),
1190 CG_FDO_CTRL0, FDO_STATIC_DUTY, duty));
1191
1192 return smu_v13_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC);
1193 }
1194
1195 int
smu_v13_0_set_fan_control_mode(struct smu_context * smu,uint32_t mode)1196 smu_v13_0_set_fan_control_mode(struct smu_context *smu,
1197 uint32_t mode)
1198 {
1199 int ret = 0;
1200
1201 switch (mode) {
1202 case AMD_FAN_CTRL_NONE:
1203 ret = smu_v13_0_set_fan_speed_pwm(smu, 255);
1204 break;
1205 case AMD_FAN_CTRL_MANUAL:
1206 ret = smu_v13_0_auto_fan_control(smu, 0);
1207 break;
1208 case AMD_FAN_CTRL_AUTO:
1209 ret = smu_v13_0_auto_fan_control(smu, 1);
1210 break;
1211 default:
1212 break;
1213 }
1214
1215 if (ret) {
1216 dev_err(smu->adev->dev, "[%s]Set fan control mode failed!", __func__);
1217 return -EINVAL;
1218 }
1219
1220 return ret;
1221 }
1222
smu_v13_0_set_fan_speed_rpm(struct smu_context * smu,uint32_t speed)1223 int smu_v13_0_set_fan_speed_rpm(struct smu_context *smu,
1224 uint32_t speed)
1225 {
1226 struct amdgpu_device *adev = smu->adev;
1227 uint32_t crystal_clock_freq = 2500;
1228 uint32_t tach_period;
1229 int ret;
1230
1231 if (!speed)
1232 return -EINVAL;
1233
1234 ret = smu_v13_0_auto_fan_control(smu, 0);
1235 if (ret)
1236 return ret;
1237
1238 tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed);
1239 WREG32_SOC15(THM, 0, regCG_TACH_CTRL,
1240 REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_TACH_CTRL),
1241 CG_TACH_CTRL, TARGET_PERIOD,
1242 tach_period));
1243
1244 return smu_v13_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC_RPM);
1245 }
1246
smu_v13_0_set_xgmi_pstate(struct smu_context * smu,uint32_t pstate)1247 int smu_v13_0_set_xgmi_pstate(struct smu_context *smu,
1248 uint32_t pstate)
1249 {
1250 int ret = 0;
1251 ret = smu_cmn_send_smc_msg_with_param(smu,
1252 SMU_MSG_SetXgmiMode,
1253 pstate ? XGMI_MODE_PSTATE_D0 : XGMI_MODE_PSTATE_D3,
1254 NULL);
1255 return ret;
1256 }
1257
smu_v13_0_set_irq_state(struct amdgpu_device * adev,struct amdgpu_irq_src * source,unsigned tyep,enum amdgpu_interrupt_state state)1258 static int smu_v13_0_set_irq_state(struct amdgpu_device *adev,
1259 struct amdgpu_irq_src *source,
1260 unsigned tyep,
1261 enum amdgpu_interrupt_state state)
1262 {
1263 struct smu_context *smu = adev->powerplay.pp_handle;
1264 uint32_t low, high;
1265 uint32_t val = 0;
1266
1267 switch (state) {
1268 case AMDGPU_IRQ_STATE_DISABLE:
1269 /* For THM irqs */
1270 val = RREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL);
1271 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 1);
1272 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 1);
1273 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL, val);
1274
1275 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_ENA, 0);
1276
1277 /* For MP1 SW irqs */
1278 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);
1279 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 1);
1280 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val);
1281
1282 break;
1283 case AMDGPU_IRQ_STATE_ENABLE:
1284 /* For THM irqs */
1285 low = max(SMU_THERMAL_MINIMUM_ALERT_TEMP,
1286 smu->thermal_range.min / SMU_TEMPERATURE_UNITS_PER_CENTIGRADES);
1287 high = min(SMU_THERMAL_MAXIMUM_ALERT_TEMP,
1288 smu->thermal_range.software_shutdown_temp);
1289
1290 val = RREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL);
1291 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5);
1292 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1);
1293 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 0);
1294 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 0);
1295 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high & 0xff));
1296 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low & 0xff));
1297 val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK);
1298 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL, val);
1299
1300 val = (1 << THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT);
1301 val |= (1 << THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT);
1302 val |= (1 << THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT);
1303 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_ENA, val);
1304
1305 /* For MP1 SW irqs */
1306 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT);
1307 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, ID, 0xFE);
1308 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, VALID, 0);
1309 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT, val);
1310
1311 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);
1312 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 0);
1313 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val);
1314
1315 break;
1316 default:
1317 break;
1318 }
1319
1320 return 0;
1321 }
1322
smu_v13_0_ack_ac_dc_interrupt(struct smu_context * smu)1323 static int smu_v13_0_ack_ac_dc_interrupt(struct smu_context *smu)
1324 {
1325 return smu_cmn_send_smc_msg(smu,
1326 SMU_MSG_ReenableAcDcInterrupt,
1327 NULL);
1328 }
1329
1330 #define THM_11_0__SRCID__THM_DIG_THERM_L2H 0 /* ASIC_TEMP > CG_THERMAL_INT.DIG_THERM_INTH */
1331 #define THM_11_0__SRCID__THM_DIG_THERM_H2L 1 /* ASIC_TEMP < CG_THERMAL_INT.DIG_THERM_INTL */
1332 #define SMUIO_11_0__SRCID__SMUIO_GPIO19 83
1333
smu_v13_0_irq_process(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)1334 static int smu_v13_0_irq_process(struct amdgpu_device *adev,
1335 struct amdgpu_irq_src *source,
1336 struct amdgpu_iv_entry *entry)
1337 {
1338 struct smu_context *smu = adev->powerplay.pp_handle;
1339 uint32_t client_id = entry->client_id;
1340 uint32_t src_id = entry->src_id;
1341 /*
1342 * ctxid is used to distinguish different
1343 * events for SMCToHost interrupt.
1344 */
1345 uint32_t ctxid = entry->src_data[0];
1346 uint32_t data;
1347 uint32_t high;
1348
1349 if (client_id == SOC15_IH_CLIENTID_THM) {
1350 switch (src_id) {
1351 case THM_11_0__SRCID__THM_DIG_THERM_L2H:
1352 schedule_delayed_work(&smu->swctf_delayed_work,
1353 msecs_to_jiffies(AMDGPU_SWCTF_EXTRA_DELAY));
1354 break;
1355 case THM_11_0__SRCID__THM_DIG_THERM_H2L:
1356 dev_emerg(adev->dev, "ERROR: GPU under temperature range detected\n");
1357 break;
1358 default:
1359 dev_emerg(adev->dev, "ERROR: GPU under temperature range unknown src id (%d)\n",
1360 src_id);
1361 break;
1362 }
1363 } else if (client_id == SOC15_IH_CLIENTID_ROM_SMUIO) {
1364 dev_emerg(adev->dev, "ERROR: GPU HW Critical Temperature Fault(aka CTF) detected!\n");
1365 /*
1366 * HW CTF just occurred. Shutdown to prevent further damage.
1367 */
1368 dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU HW CTF!\n");
1369 orderly_poweroff(true);
1370 } else if (client_id == SOC15_IH_CLIENTID_MP1) {
1371 if (src_id == SMU_IH_INTERRUPT_ID_TO_DRIVER) {
1372 /* ACK SMUToHost interrupt */
1373 data = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);
1374 data = REG_SET_FIELD(data, MP1_SMN_IH_SW_INT_CTRL, INT_ACK, 1);
1375 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, data);
1376
1377 switch (ctxid) {
1378 case SMU_IH_INTERRUPT_CONTEXT_ID_AC:
1379 dev_dbg(adev->dev, "Switched to AC mode!\n");
1380 smu_v13_0_ack_ac_dc_interrupt(smu);
1381 adev->pm.ac_power = true;
1382 break;
1383 case SMU_IH_INTERRUPT_CONTEXT_ID_DC:
1384 dev_dbg(adev->dev, "Switched to DC mode!\n");
1385 smu_v13_0_ack_ac_dc_interrupt(smu);
1386 adev->pm.ac_power = false;
1387 break;
1388 case SMU_IH_INTERRUPT_CONTEXT_ID_THERMAL_THROTTLING:
1389 /*
1390 * Increment the throttle interrupt counter
1391 */
1392 atomic64_inc(&smu->throttle_int_counter);
1393
1394 if (!atomic_read(&adev->throttling_logging_enabled))
1395 return 0;
1396
1397 if (__ratelimit(&adev->throttling_logging_rs))
1398 schedule_work(&smu->throttling_logging_work);
1399
1400 break;
1401 case SMU_IH_INTERRUPT_CONTEXT_ID_FAN_ABNORMAL:
1402 high = smu->thermal_range.software_shutdown_temp +
1403 smu->thermal_range.software_shutdown_temp_offset;
1404 high = min_t(typeof(high),
1405 SMU_THERMAL_MAXIMUM_ALERT_TEMP,
1406 high);
1407 dev_emerg(adev->dev, "Reduce soft CTF limit to %d (by an offset %d)\n",
1408 high,
1409 smu->thermal_range.software_shutdown_temp_offset);
1410
1411 data = RREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL);
1412 data = REG_SET_FIELD(data, THM_THERMAL_INT_CTRL,
1413 DIG_THERM_INTH,
1414 (high & 0xff));
1415 data = data & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK);
1416 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL, data);
1417 break;
1418 case SMU_IH_INTERRUPT_CONTEXT_ID_FAN_RECOVERY:
1419 high = min_t(typeof(high),
1420 SMU_THERMAL_MAXIMUM_ALERT_TEMP,
1421 smu->thermal_range.software_shutdown_temp);
1422 dev_emerg(adev->dev, "Recover soft CTF limit to %d\n", high);
1423
1424 data = RREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL);
1425 data = REG_SET_FIELD(data, THM_THERMAL_INT_CTRL,
1426 DIG_THERM_INTH,
1427 (high & 0xff));
1428 data = data & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK);
1429 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL, data);
1430 break;
1431 default:
1432 dev_dbg(adev->dev, "Unhandled context id %d from client:%d!\n",
1433 ctxid, client_id);
1434 break;
1435 }
1436 }
1437 }
1438
1439 return 0;
1440 }
1441
1442 static const struct amdgpu_irq_src_funcs smu_v13_0_irq_funcs = {
1443 .set = smu_v13_0_set_irq_state,
1444 .process = smu_v13_0_irq_process,
1445 };
1446
smu_v13_0_register_irq_handler(struct smu_context * smu)1447 int smu_v13_0_register_irq_handler(struct smu_context *smu)
1448 {
1449 struct amdgpu_device *adev = smu->adev;
1450 struct amdgpu_irq_src *irq_src = &smu->irq_source;
1451 int ret = 0;
1452
1453 if (amdgpu_sriov_vf(adev))
1454 return 0;
1455
1456 irq_src->num_types = 1;
1457 irq_src->funcs = &smu_v13_0_irq_funcs;
1458
1459 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM,
1460 THM_11_0__SRCID__THM_DIG_THERM_L2H,
1461 irq_src);
1462 if (ret)
1463 return ret;
1464
1465 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM,
1466 THM_11_0__SRCID__THM_DIG_THERM_H2L,
1467 irq_src);
1468 if (ret)
1469 return ret;
1470
1471 /* Register CTF(GPIO_19) interrupt */
1472 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_ROM_SMUIO,
1473 SMUIO_11_0__SRCID__SMUIO_GPIO19,
1474 irq_src);
1475 if (ret)
1476 return ret;
1477
1478 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_MP1,
1479 SMU_IH_INTERRUPT_ID_TO_DRIVER,
1480 irq_src);
1481 if (ret)
1482 return ret;
1483
1484 return ret;
1485 }
1486
smu_v13_0_get_max_sustainable_clocks_by_dc(struct smu_context * smu,struct pp_smu_nv_clock_table * max_clocks)1487 int smu_v13_0_get_max_sustainable_clocks_by_dc(struct smu_context *smu,
1488 struct pp_smu_nv_clock_table *max_clocks)
1489 {
1490 struct smu_table_context *table_context = &smu->smu_table;
1491 struct smu_13_0_max_sustainable_clocks *sustainable_clocks = NULL;
1492
1493 if (!max_clocks || !table_context->max_sustainable_clocks)
1494 return -EINVAL;
1495
1496 sustainable_clocks = table_context->max_sustainable_clocks;
1497
1498 max_clocks->dcfClockInKhz =
1499 (unsigned int) sustainable_clocks->dcef_clock * 1000;
1500 max_clocks->displayClockInKhz =
1501 (unsigned int) sustainable_clocks->display_clock * 1000;
1502 max_clocks->phyClockInKhz =
1503 (unsigned int) sustainable_clocks->phy_clock * 1000;
1504 max_clocks->pixelClockInKhz =
1505 (unsigned int) sustainable_clocks->pixel_clock * 1000;
1506 max_clocks->uClockInKhz =
1507 (unsigned int) sustainable_clocks->uclock * 1000;
1508 max_clocks->socClockInKhz =
1509 (unsigned int) sustainable_clocks->soc_clock * 1000;
1510 max_clocks->dscClockInKhz = 0;
1511 max_clocks->dppClockInKhz = 0;
1512 max_clocks->fabricClockInKhz = 0;
1513
1514 return 0;
1515 }
1516
smu_v13_0_set_azalia_d3_pme(struct smu_context * smu)1517 int smu_v13_0_set_azalia_d3_pme(struct smu_context *smu)
1518 {
1519 int ret = 0;
1520
1521 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_BacoAudioD3PME, NULL);
1522
1523 return ret;
1524 }
1525
smu_v13_0_wait_for_reset_complete(struct smu_context * smu,uint64_t event_arg)1526 static int smu_v13_0_wait_for_reset_complete(struct smu_context *smu,
1527 uint64_t event_arg)
1528 {
1529 int ret = 0;
1530
1531 dev_dbg(smu->adev->dev, "waiting for smu reset complete\n");
1532 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GfxDriverResetRecovery, NULL);
1533
1534 return ret;
1535 }
1536
smu_v13_0_wait_for_event(struct smu_context * smu,enum smu_event_type event,uint64_t event_arg)1537 int smu_v13_0_wait_for_event(struct smu_context *smu, enum smu_event_type event,
1538 uint64_t event_arg)
1539 {
1540 int ret = -EINVAL;
1541
1542 switch (event) {
1543 case SMU_EVENT_RESET_COMPLETE:
1544 ret = smu_v13_0_wait_for_reset_complete(smu, event_arg);
1545 break;
1546 default:
1547 break;
1548 }
1549
1550 return ret;
1551 }
1552
smu_v13_0_get_dpm_ultimate_freq(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * min,uint32_t * max)1553 int smu_v13_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
1554 uint32_t *min, uint32_t *max)
1555 {
1556 int ret = 0, clk_id = 0;
1557 uint32_t param = 0;
1558 uint32_t clock_limit;
1559
1560 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) {
1561 ret = smu_v13_0_get_boot_freq_by_index(smu, clk_type, &clock_limit);
1562 if (ret)
1563 return ret;
1564
1565 /* clock in Mhz unit */
1566 if (min)
1567 *min = clock_limit / 100;
1568 if (max)
1569 *max = clock_limit / 100;
1570
1571 return 0;
1572 }
1573
1574 clk_id = smu_cmn_to_asic_specific_index(smu,
1575 CMN2ASIC_MAPPING_CLK,
1576 clk_type);
1577 if (clk_id < 0) {
1578 ret = -EINVAL;
1579 goto failed;
1580 }
1581 param = (clk_id & 0xffff) << 16;
1582
1583 if (max) {
1584 if (smu->adev->pm.ac_power)
1585 ret = smu_cmn_send_smc_msg_with_param(smu,
1586 SMU_MSG_GetMaxDpmFreq,
1587 param,
1588 max);
1589 else
1590 ret = smu_cmn_send_smc_msg_with_param(smu,
1591 SMU_MSG_GetDcModeMaxDpmFreq,
1592 param,
1593 max);
1594 if (ret)
1595 goto failed;
1596 }
1597
1598 if (min) {
1599 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMinDpmFreq, param, min);
1600 if (ret)
1601 goto failed;
1602 }
1603
1604 failed:
1605 return ret;
1606 }
1607
smu_v13_0_set_soft_freq_limited_range(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t min,uint32_t max)1608 int smu_v13_0_set_soft_freq_limited_range(struct smu_context *smu,
1609 enum smu_clk_type clk_type,
1610 uint32_t min,
1611 uint32_t max)
1612 {
1613 int ret = 0, clk_id = 0;
1614 uint32_t param;
1615
1616 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1617 return 0;
1618
1619 clk_id = smu_cmn_to_asic_specific_index(smu,
1620 CMN2ASIC_MAPPING_CLK,
1621 clk_type);
1622 if (clk_id < 0)
1623 return clk_id;
1624
1625 if (max > 0) {
1626 param = (uint32_t)((clk_id << 16) | (max & 0xffff));
1627 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxByFreq,
1628 param, NULL);
1629 if (ret)
1630 goto out;
1631 }
1632
1633 if (min > 0) {
1634 param = (uint32_t)((clk_id << 16) | (min & 0xffff));
1635 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinByFreq,
1636 param, NULL);
1637 if (ret)
1638 goto out;
1639 }
1640
1641 out:
1642 return ret;
1643 }
1644
smu_v13_0_set_hard_freq_limited_range(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t min,uint32_t max)1645 int smu_v13_0_set_hard_freq_limited_range(struct smu_context *smu,
1646 enum smu_clk_type clk_type,
1647 uint32_t min,
1648 uint32_t max)
1649 {
1650 int ret = 0, clk_id = 0;
1651 uint32_t param;
1652
1653 if (min <= 0 && max <= 0)
1654 return -EINVAL;
1655
1656 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1657 return 0;
1658
1659 clk_id = smu_cmn_to_asic_specific_index(smu,
1660 CMN2ASIC_MAPPING_CLK,
1661 clk_type);
1662 if (clk_id < 0)
1663 return clk_id;
1664
1665 if (max > 0) {
1666 param = (uint32_t)((clk_id << 16) | (max & 0xffff));
1667 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMaxByFreq,
1668 param, NULL);
1669 if (ret)
1670 return ret;
1671 }
1672
1673 if (min > 0) {
1674 param = (uint32_t)((clk_id << 16) | (min & 0xffff));
1675 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinByFreq,
1676 param, NULL);
1677 if (ret)
1678 return ret;
1679 }
1680
1681 return ret;
1682 }
1683
smu_v13_0_set_performance_level(struct smu_context * smu,enum amd_dpm_forced_level level)1684 int smu_v13_0_set_performance_level(struct smu_context *smu,
1685 enum amd_dpm_forced_level level)
1686 {
1687 struct smu_13_0_dpm_context *dpm_context =
1688 smu->smu_dpm.dpm_context;
1689 struct smu_13_0_dpm_table *gfx_table =
1690 &dpm_context->dpm_tables.gfx_table;
1691 struct smu_13_0_dpm_table *mem_table =
1692 &dpm_context->dpm_tables.uclk_table;
1693 struct smu_13_0_dpm_table *soc_table =
1694 &dpm_context->dpm_tables.soc_table;
1695 struct smu_13_0_dpm_table *vclk_table =
1696 &dpm_context->dpm_tables.vclk_table;
1697 struct smu_13_0_dpm_table *dclk_table =
1698 &dpm_context->dpm_tables.dclk_table;
1699 struct smu_13_0_dpm_table *fclk_table =
1700 &dpm_context->dpm_tables.fclk_table;
1701 struct smu_umd_pstate_table *pstate_table =
1702 &smu->pstate_table;
1703 struct amdgpu_device *adev = smu->adev;
1704 uint32_t sclk_min = 0, sclk_max = 0;
1705 uint32_t mclk_min = 0, mclk_max = 0;
1706 uint32_t socclk_min = 0, socclk_max = 0;
1707 uint32_t vclk_min = 0, vclk_max = 0;
1708 uint32_t dclk_min = 0, dclk_max = 0;
1709 uint32_t fclk_min = 0, fclk_max = 0;
1710 int ret = 0, i;
1711
1712 switch (level) {
1713 case AMD_DPM_FORCED_LEVEL_HIGH:
1714 sclk_min = sclk_max = gfx_table->max;
1715 mclk_min = mclk_max = mem_table->max;
1716 socclk_min = socclk_max = soc_table->max;
1717 vclk_min = vclk_max = vclk_table->max;
1718 dclk_min = dclk_max = dclk_table->max;
1719 fclk_min = fclk_max = fclk_table->max;
1720 break;
1721 case AMD_DPM_FORCED_LEVEL_LOW:
1722 sclk_min = sclk_max = gfx_table->min;
1723 mclk_min = mclk_max = mem_table->min;
1724 socclk_min = socclk_max = soc_table->min;
1725 vclk_min = vclk_max = vclk_table->min;
1726 dclk_min = dclk_max = dclk_table->min;
1727 fclk_min = fclk_max = fclk_table->min;
1728 break;
1729 case AMD_DPM_FORCED_LEVEL_AUTO:
1730 sclk_min = gfx_table->min;
1731 sclk_max = gfx_table->max;
1732 mclk_min = mem_table->min;
1733 mclk_max = mem_table->max;
1734 socclk_min = soc_table->min;
1735 socclk_max = soc_table->max;
1736 vclk_min = vclk_table->min;
1737 vclk_max = vclk_table->max;
1738 dclk_min = dclk_table->min;
1739 dclk_max = dclk_table->max;
1740 fclk_min = fclk_table->min;
1741 fclk_max = fclk_table->max;
1742 break;
1743 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1744 sclk_min = sclk_max = pstate_table->gfxclk_pstate.standard;
1745 mclk_min = mclk_max = pstate_table->uclk_pstate.standard;
1746 socclk_min = socclk_max = pstate_table->socclk_pstate.standard;
1747 vclk_min = vclk_max = pstate_table->vclk_pstate.standard;
1748 dclk_min = dclk_max = pstate_table->dclk_pstate.standard;
1749 fclk_min = fclk_max = pstate_table->fclk_pstate.standard;
1750 break;
1751 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1752 sclk_min = sclk_max = pstate_table->gfxclk_pstate.min;
1753 break;
1754 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1755 mclk_min = mclk_max = pstate_table->uclk_pstate.min;
1756 break;
1757 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1758 sclk_min = sclk_max = pstate_table->gfxclk_pstate.peak;
1759 mclk_min = mclk_max = pstate_table->uclk_pstate.peak;
1760 socclk_min = socclk_max = pstate_table->socclk_pstate.peak;
1761 vclk_min = vclk_max = pstate_table->vclk_pstate.peak;
1762 dclk_min = dclk_max = pstate_table->dclk_pstate.peak;
1763 fclk_min = fclk_max = pstate_table->fclk_pstate.peak;
1764 break;
1765 case AMD_DPM_FORCED_LEVEL_MANUAL:
1766 case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
1767 return 0;
1768 default:
1769 dev_err(adev->dev, "Invalid performance level %d\n", level);
1770 return -EINVAL;
1771 }
1772
1773 /*
1774 * Unset those settings for SMU 13.0.2. As soft limits settings
1775 * for those clock domains are not supported.
1776 */
1777 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 2)) {
1778 mclk_min = mclk_max = 0;
1779 socclk_min = socclk_max = 0;
1780 vclk_min = vclk_max = 0;
1781 dclk_min = dclk_max = 0;
1782 fclk_min = fclk_max = 0;
1783 }
1784
1785 if (sclk_min && sclk_max) {
1786 ret = smu_v13_0_set_soft_freq_limited_range(smu,
1787 SMU_GFXCLK,
1788 sclk_min,
1789 sclk_max);
1790 if (ret)
1791 return ret;
1792
1793 pstate_table->gfxclk_pstate.curr.min = sclk_min;
1794 pstate_table->gfxclk_pstate.curr.max = sclk_max;
1795 }
1796
1797 if (mclk_min && mclk_max) {
1798 ret = smu_v13_0_set_soft_freq_limited_range(smu,
1799 SMU_MCLK,
1800 mclk_min,
1801 mclk_max);
1802 if (ret)
1803 return ret;
1804
1805 pstate_table->uclk_pstate.curr.min = mclk_min;
1806 pstate_table->uclk_pstate.curr.max = mclk_max;
1807 }
1808
1809 if (socclk_min && socclk_max) {
1810 ret = smu_v13_0_set_soft_freq_limited_range(smu,
1811 SMU_SOCCLK,
1812 socclk_min,
1813 socclk_max);
1814 if (ret)
1815 return ret;
1816
1817 pstate_table->socclk_pstate.curr.min = socclk_min;
1818 pstate_table->socclk_pstate.curr.max = socclk_max;
1819 }
1820
1821 if (vclk_min && vclk_max) {
1822 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
1823 if (adev->vcn.harvest_config & (1 << i))
1824 continue;
1825 ret = smu_v13_0_set_soft_freq_limited_range(smu,
1826 i ? SMU_VCLK1 : SMU_VCLK,
1827 vclk_min,
1828 vclk_max);
1829 if (ret)
1830 return ret;
1831 }
1832 pstate_table->vclk_pstate.curr.min = vclk_min;
1833 pstate_table->vclk_pstate.curr.max = vclk_max;
1834 }
1835
1836 if (dclk_min && dclk_max) {
1837 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
1838 if (adev->vcn.harvest_config & (1 << i))
1839 continue;
1840 ret = smu_v13_0_set_soft_freq_limited_range(smu,
1841 i ? SMU_DCLK1 : SMU_DCLK,
1842 dclk_min,
1843 dclk_max);
1844 if (ret)
1845 return ret;
1846 }
1847 pstate_table->dclk_pstate.curr.min = dclk_min;
1848 pstate_table->dclk_pstate.curr.max = dclk_max;
1849 }
1850
1851 if (fclk_min && fclk_max) {
1852 ret = smu_v13_0_set_soft_freq_limited_range(smu,
1853 SMU_FCLK,
1854 fclk_min,
1855 fclk_max);
1856 if (ret)
1857 return ret;
1858
1859 pstate_table->fclk_pstate.curr.min = fclk_min;
1860 pstate_table->fclk_pstate.curr.max = fclk_max;
1861 }
1862
1863 return ret;
1864 }
1865
smu_v13_0_set_power_source(struct smu_context * smu,enum smu_power_src_type power_src)1866 int smu_v13_0_set_power_source(struct smu_context *smu,
1867 enum smu_power_src_type power_src)
1868 {
1869 int pwr_source;
1870
1871 pwr_source = smu_cmn_to_asic_specific_index(smu,
1872 CMN2ASIC_MAPPING_PWR,
1873 (uint32_t)power_src);
1874 if (pwr_source < 0)
1875 return -EINVAL;
1876
1877 return smu_cmn_send_smc_msg_with_param(smu,
1878 SMU_MSG_NotifyPowerSource,
1879 pwr_source,
1880 NULL);
1881 }
1882
smu_v13_0_get_boot_freq_by_index(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * value)1883 int smu_v13_0_get_boot_freq_by_index(struct smu_context *smu,
1884 enum smu_clk_type clk_type,
1885 uint32_t *value)
1886 {
1887 int ret = 0;
1888
1889 switch (clk_type) {
1890 case SMU_MCLK:
1891 case SMU_UCLK:
1892 *value = smu->smu_table.boot_values.uclk;
1893 break;
1894 case SMU_FCLK:
1895 *value = smu->smu_table.boot_values.fclk;
1896 break;
1897 case SMU_GFXCLK:
1898 case SMU_SCLK:
1899 *value = smu->smu_table.boot_values.gfxclk;
1900 break;
1901 case SMU_SOCCLK:
1902 *value = smu->smu_table.boot_values.socclk;
1903 break;
1904 case SMU_VCLK:
1905 *value = smu->smu_table.boot_values.vclk;
1906 break;
1907 case SMU_DCLK:
1908 *value = smu->smu_table.boot_values.dclk;
1909 break;
1910 default:
1911 ret = -EINVAL;
1912 break;
1913 }
1914 return ret;
1915 }
1916
smu_v13_0_get_dpm_freq_by_index(struct smu_context * smu,enum smu_clk_type clk_type,uint16_t level,uint32_t * value)1917 int smu_v13_0_get_dpm_freq_by_index(struct smu_context *smu,
1918 enum smu_clk_type clk_type, uint16_t level,
1919 uint32_t *value)
1920 {
1921 int ret = 0, clk_id = 0;
1922 uint32_t param;
1923
1924 if (!value)
1925 return -EINVAL;
1926
1927 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1928 return smu_v13_0_get_boot_freq_by_index(smu, clk_type, value);
1929
1930 clk_id = smu_cmn_to_asic_specific_index(smu,
1931 CMN2ASIC_MAPPING_CLK,
1932 clk_type);
1933 if (clk_id < 0)
1934 return clk_id;
1935
1936 param = (uint32_t)(((clk_id & 0xffff) << 16) | (level & 0xffff));
1937
1938 ret = smu_cmn_send_smc_msg_with_param(smu,
1939 SMU_MSG_GetDpmFreqByIndex,
1940 param,
1941 value);
1942 if (ret)
1943 return ret;
1944
1945 *value = *value & 0x7fffffff;
1946
1947 return ret;
1948 }
1949
smu_v13_0_get_dpm_level_count(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * value)1950 static int smu_v13_0_get_dpm_level_count(struct smu_context *smu,
1951 enum smu_clk_type clk_type,
1952 uint32_t *value)
1953 {
1954 int ret;
1955
1956 ret = smu_v13_0_get_dpm_freq_by_index(smu, clk_type, 0xff, value);
1957 /* SMU v13.0.2 FW returns 0 based max level, increment by one for it */
1958 if ((amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 2)) && (!ret && value))
1959 ++(*value);
1960
1961 return ret;
1962 }
1963
smu_v13_0_get_fine_grained_status(struct smu_context * smu,enum smu_clk_type clk_type,bool * is_fine_grained_dpm)1964 static int smu_v13_0_get_fine_grained_status(struct smu_context *smu,
1965 enum smu_clk_type clk_type,
1966 bool *is_fine_grained_dpm)
1967 {
1968 int ret = 0, clk_id = 0;
1969 uint32_t param;
1970 uint32_t value;
1971
1972 if (!is_fine_grained_dpm)
1973 return -EINVAL;
1974
1975 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1976 return 0;
1977
1978 clk_id = smu_cmn_to_asic_specific_index(smu,
1979 CMN2ASIC_MAPPING_CLK,
1980 clk_type);
1981 if (clk_id < 0)
1982 return clk_id;
1983
1984 param = (uint32_t)(((clk_id & 0xffff) << 16) | 0xff);
1985
1986 ret = smu_cmn_send_smc_msg_with_param(smu,
1987 SMU_MSG_GetDpmFreqByIndex,
1988 param,
1989 &value);
1990 if (ret)
1991 return ret;
1992
1993 /*
1994 * BIT31: 1 - Fine grained DPM, 0 - Dicrete DPM
1995 * now, we un-support it
1996 */
1997 *is_fine_grained_dpm = value & 0x80000000;
1998
1999 return 0;
2000 }
2001
smu_v13_0_set_single_dpm_table(struct smu_context * smu,enum smu_clk_type clk_type,struct smu_13_0_dpm_table * single_dpm_table)2002 int smu_v13_0_set_single_dpm_table(struct smu_context *smu,
2003 enum smu_clk_type clk_type,
2004 struct smu_13_0_dpm_table *single_dpm_table)
2005 {
2006 int ret = 0;
2007 uint32_t clk;
2008 int i;
2009
2010 ret = smu_v13_0_get_dpm_level_count(smu,
2011 clk_type,
2012 &single_dpm_table->count);
2013 if (ret) {
2014 dev_err(smu->adev->dev, "[%s] failed to get dpm levels!\n", __func__);
2015 return ret;
2016 }
2017
2018 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) != IP_VERSION(13, 0, 2)) {
2019 ret = smu_v13_0_get_fine_grained_status(smu,
2020 clk_type,
2021 &single_dpm_table->is_fine_grained);
2022 if (ret) {
2023 dev_err(smu->adev->dev, "[%s] failed to get fine grained status!\n", __func__);
2024 return ret;
2025 }
2026 }
2027
2028 for (i = 0; i < single_dpm_table->count; i++) {
2029 ret = smu_v13_0_get_dpm_freq_by_index(smu,
2030 clk_type,
2031 i,
2032 &clk);
2033 if (ret) {
2034 dev_err(smu->adev->dev, "[%s] failed to get dpm freq by index!\n", __func__);
2035 return ret;
2036 }
2037
2038 single_dpm_table->dpm_levels[i].value = clk;
2039 single_dpm_table->dpm_levels[i].enabled = true;
2040
2041 if (i == 0)
2042 single_dpm_table->min = clk;
2043 else if (i == single_dpm_table->count - 1)
2044 single_dpm_table->max = clk;
2045 }
2046
2047 return 0;
2048 }
2049
smu_v13_0_get_current_pcie_link_width_level(struct smu_context * smu)2050 int smu_v13_0_get_current_pcie_link_width_level(struct smu_context *smu)
2051 {
2052 struct amdgpu_device *adev = smu->adev;
2053
2054 return (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) &
2055 PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK)
2056 >> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT;
2057 }
2058
smu_v13_0_get_current_pcie_link_width(struct smu_context * smu)2059 int smu_v13_0_get_current_pcie_link_width(struct smu_context *smu)
2060 {
2061 uint32_t width_level;
2062
2063 width_level = smu_v13_0_get_current_pcie_link_width_level(smu);
2064 if (width_level > LINK_WIDTH_MAX)
2065 width_level = 0;
2066
2067 return link_width[width_level];
2068 }
2069
smu_v13_0_get_current_pcie_link_speed_level(struct smu_context * smu)2070 int smu_v13_0_get_current_pcie_link_speed_level(struct smu_context *smu)
2071 {
2072 struct amdgpu_device *adev = smu->adev;
2073
2074 return (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) &
2075 PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK)
2076 >> PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;
2077 }
2078
smu_v13_0_get_current_pcie_link_speed(struct smu_context * smu)2079 int smu_v13_0_get_current_pcie_link_speed(struct smu_context *smu)
2080 {
2081 uint32_t speed_level;
2082
2083 speed_level = smu_v13_0_get_current_pcie_link_speed_level(smu);
2084 if (speed_level > LINK_SPEED_MAX)
2085 speed_level = 0;
2086
2087 return link_speed[speed_level];
2088 }
2089
smu_v13_0_set_vcn_enable(struct smu_context * smu,bool enable)2090 int smu_v13_0_set_vcn_enable(struct smu_context *smu,
2091 bool enable)
2092 {
2093 struct amdgpu_device *adev = smu->adev;
2094 int i, ret = 0;
2095
2096 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
2097 if (adev->vcn.harvest_config & (1 << i))
2098 continue;
2099
2100 ret = smu_cmn_send_smc_msg_with_param(smu, enable ?
2101 SMU_MSG_PowerUpVcn : SMU_MSG_PowerDownVcn,
2102 i << 16U, NULL);
2103 if (ret)
2104 return ret;
2105 }
2106
2107 return ret;
2108 }
2109
smu_v13_0_set_jpeg_enable(struct smu_context * smu,bool enable)2110 int smu_v13_0_set_jpeg_enable(struct smu_context *smu,
2111 bool enable)
2112 {
2113 return smu_cmn_send_smc_msg_with_param(smu, enable ?
2114 SMU_MSG_PowerUpJpeg : SMU_MSG_PowerDownJpeg,
2115 0, NULL);
2116 }
2117
smu_v13_0_run_btc(struct smu_context * smu)2118 int smu_v13_0_run_btc(struct smu_context *smu)
2119 {
2120 int res;
2121
2122 res = smu_cmn_send_smc_msg(smu, SMU_MSG_RunDcBtc, NULL);
2123 if (res)
2124 dev_err(smu->adev->dev, "RunDcBtc failed!\n");
2125
2126 return res;
2127 }
2128
smu_v13_0_gpo_control(struct smu_context * smu,bool enablement)2129 int smu_v13_0_gpo_control(struct smu_context *smu,
2130 bool enablement)
2131 {
2132 int res;
2133
2134 res = smu_cmn_send_smc_msg_with_param(smu,
2135 SMU_MSG_AllowGpo,
2136 enablement ? 1 : 0,
2137 NULL);
2138 if (res)
2139 dev_err(smu->adev->dev, "SetGpoAllow %d failed!\n", enablement);
2140
2141 return res;
2142 }
2143
smu_v13_0_deep_sleep_control(struct smu_context * smu,bool enablement)2144 int smu_v13_0_deep_sleep_control(struct smu_context *smu,
2145 bool enablement)
2146 {
2147 struct amdgpu_device *adev = smu->adev;
2148 int ret = 0;
2149
2150 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_GFXCLK_BIT)) {
2151 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_GFXCLK_BIT, enablement);
2152 if (ret) {
2153 dev_err(adev->dev, "Failed to %s GFXCLK DS!\n", enablement ? "enable" : "disable");
2154 return ret;
2155 }
2156 }
2157
2158 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_UCLK_BIT)) {
2159 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_UCLK_BIT, enablement);
2160 if (ret) {
2161 dev_err(adev->dev, "Failed to %s UCLK DS!\n", enablement ? "enable" : "disable");
2162 return ret;
2163 }
2164 }
2165
2166 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_FCLK_BIT)) {
2167 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_FCLK_BIT, enablement);
2168 if (ret) {
2169 dev_err(adev->dev, "Failed to %s FCLK DS!\n", enablement ? "enable" : "disable");
2170 return ret;
2171 }
2172 }
2173
2174 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_SOCCLK_BIT)) {
2175 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_SOCCLK_BIT, enablement);
2176 if (ret) {
2177 dev_err(adev->dev, "Failed to %s SOCCLK DS!\n", enablement ? "enable" : "disable");
2178 return ret;
2179 }
2180 }
2181
2182 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_LCLK_BIT)) {
2183 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_LCLK_BIT, enablement);
2184 if (ret) {
2185 dev_err(adev->dev, "Failed to %s LCLK DS!\n", enablement ? "enable" : "disable");
2186 return ret;
2187 }
2188 }
2189
2190 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_VCN_BIT)) {
2191 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_VCN_BIT, enablement);
2192 if (ret) {
2193 dev_err(adev->dev, "Failed to %s VCN DS!\n", enablement ? "enable" : "disable");
2194 return ret;
2195 }
2196 }
2197
2198 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_MP0CLK_BIT)) {
2199 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_MP0CLK_BIT, enablement);
2200 if (ret) {
2201 dev_err(adev->dev, "Failed to %s MP0/MPIOCLK DS!\n", enablement ? "enable" : "disable");
2202 return ret;
2203 }
2204 }
2205
2206 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_MP1CLK_BIT)) {
2207 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_MP1CLK_BIT, enablement);
2208 if (ret) {
2209 dev_err(adev->dev, "Failed to %s MP1CLK DS!\n", enablement ? "enable" : "disable");
2210 return ret;
2211 }
2212 }
2213
2214 return ret;
2215 }
2216
smu_v13_0_gfx_ulv_control(struct smu_context * smu,bool enablement)2217 int smu_v13_0_gfx_ulv_control(struct smu_context *smu,
2218 bool enablement)
2219 {
2220 int ret = 0;
2221
2222 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_GFX_ULV_BIT))
2223 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_GFX_ULV_BIT, enablement);
2224
2225 return ret;
2226 }
2227
smu_v13_0_baco_set_armd3_sequence(struct smu_context * smu,enum smu_baco_seq baco_seq)2228 static int smu_v13_0_baco_set_armd3_sequence(struct smu_context *smu,
2229 enum smu_baco_seq baco_seq)
2230 {
2231 struct smu_baco_context *smu_baco = &smu->smu_baco;
2232 int ret;
2233
2234 ret = smu_cmn_send_smc_msg_with_param(smu,
2235 SMU_MSG_ArmD3,
2236 baco_seq,
2237 NULL);
2238 if (ret)
2239 return ret;
2240
2241 if (baco_seq == BACO_SEQ_BAMACO ||
2242 baco_seq == BACO_SEQ_BACO)
2243 smu_baco->state = SMU_BACO_STATE_ENTER;
2244 else
2245 smu_baco->state = SMU_BACO_STATE_EXIT;
2246
2247 return 0;
2248 }
2249
smu_v13_0_baco_get_state(struct smu_context * smu)2250 static enum smu_baco_state smu_v13_0_baco_get_state(struct smu_context *smu)
2251 {
2252 struct smu_baco_context *smu_baco = &smu->smu_baco;
2253
2254 return smu_baco->state;
2255 }
2256
smu_v13_0_baco_set_state(struct smu_context * smu,enum smu_baco_state state)2257 static int smu_v13_0_baco_set_state(struct smu_context *smu,
2258 enum smu_baco_state state)
2259 {
2260 struct smu_baco_context *smu_baco = &smu->smu_baco;
2261 struct amdgpu_device *adev = smu->adev;
2262 int ret = 0;
2263
2264 if (smu_v13_0_baco_get_state(smu) == state)
2265 return 0;
2266
2267 if (state == SMU_BACO_STATE_ENTER) {
2268 ret = smu_cmn_send_smc_msg_with_param(smu,
2269 SMU_MSG_EnterBaco,
2270 (adev->pm.rpm_mode == AMDGPU_RUNPM_BAMACO) ?
2271 BACO_SEQ_BAMACO : BACO_SEQ_BACO,
2272 NULL);
2273 } else {
2274 ret = smu_cmn_send_smc_msg(smu,
2275 SMU_MSG_ExitBaco,
2276 NULL);
2277 if (ret)
2278 return ret;
2279
2280 /* clear vbios scratch 6 and 7 for coming asic reinit */
2281 WREG32(adev->bios_scratch_reg_offset + 6, 0);
2282 WREG32(adev->bios_scratch_reg_offset + 7, 0);
2283 }
2284
2285 if (!ret)
2286 smu_baco->state = state;
2287
2288 return ret;
2289 }
2290
smu_v13_0_get_bamaco_support(struct smu_context * smu)2291 int smu_v13_0_get_bamaco_support(struct smu_context *smu)
2292 {
2293 struct smu_baco_context *smu_baco = &smu->smu_baco;
2294 int bamaco_support = 0;
2295
2296 if (amdgpu_sriov_vf(smu->adev) || !smu_baco->platform_support)
2297 return 0;
2298
2299 if (smu_baco->maco_support)
2300 bamaco_support |= MACO_SUPPORT;
2301
2302 /* return true if ASIC is in BACO state already */
2303 if (smu_v13_0_baco_get_state(smu) == SMU_BACO_STATE_ENTER)
2304 return bamaco_support |= BACO_SUPPORT;
2305
2306 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_BACO_BIT) &&
2307 !smu_cmn_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT))
2308 return 0;
2309
2310 return (bamaco_support |= BACO_SUPPORT);
2311 }
2312
smu_v13_0_baco_enter(struct smu_context * smu)2313 int smu_v13_0_baco_enter(struct smu_context *smu)
2314 {
2315 struct amdgpu_device *adev = smu->adev;
2316 int ret;
2317
2318 if (adev->in_runpm && smu_cmn_is_audio_func_enabled(adev)) {
2319 return smu_v13_0_baco_set_armd3_sequence(smu,
2320 (adev->pm.rpm_mode == AMDGPU_RUNPM_BAMACO) ?
2321 BACO_SEQ_BAMACO : BACO_SEQ_BACO);
2322 } else {
2323 ret = smu_v13_0_baco_set_state(smu, SMU_BACO_STATE_ENTER);
2324 if (!ret)
2325 usleep_range(10000, 11000);
2326
2327 return ret;
2328 }
2329 }
2330
smu_v13_0_baco_exit(struct smu_context * smu)2331 int smu_v13_0_baco_exit(struct smu_context *smu)
2332 {
2333 struct amdgpu_device *adev = smu->adev;
2334 int ret;
2335
2336 if (adev->in_runpm && smu_cmn_is_audio_func_enabled(adev)) {
2337 /* Wait for PMFW handling for the Dstate change */
2338 usleep_range(10000, 11000);
2339 ret = smu_v13_0_baco_set_armd3_sequence(smu, BACO_SEQ_ULPS);
2340 } else {
2341 ret = smu_v13_0_baco_set_state(smu, SMU_BACO_STATE_EXIT);
2342 }
2343
2344 if (!ret)
2345 adev->gfx.is_poweron = false;
2346
2347 return ret;
2348 }
2349
smu_v13_0_set_gfx_power_up_by_imu(struct smu_context * smu)2350 int smu_v13_0_set_gfx_power_up_by_imu(struct smu_context *smu)
2351 {
2352 uint16_t index;
2353 struct amdgpu_device *adev = smu->adev;
2354
2355 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
2356 return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_EnableGfxImu,
2357 ENABLE_IMU_ARG_GFXOFF_ENABLE, NULL);
2358 }
2359
2360 index = smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG,
2361 SMU_MSG_EnableGfxImu);
2362 return smu_cmn_send_msg_without_waiting(smu, index,
2363 ENABLE_IMU_ARG_GFXOFF_ENABLE);
2364 }
2365
smu_v13_0_od_edit_dpm_table(struct smu_context * smu,enum PP_OD_DPM_TABLE_COMMAND type,long input[],uint32_t size)2366 int smu_v13_0_od_edit_dpm_table(struct smu_context *smu,
2367 enum PP_OD_DPM_TABLE_COMMAND type,
2368 long input[], uint32_t size)
2369 {
2370 struct smu_dpm_context *smu_dpm = &(smu->smu_dpm);
2371 int ret = 0;
2372
2373 /* Only allowed in manual mode */
2374 if (smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
2375 return -EINVAL;
2376
2377 switch (type) {
2378 case PP_OD_EDIT_SCLK_VDDC_TABLE:
2379 if (size != 2) {
2380 dev_err(smu->adev->dev, "Input parameter number not correct\n");
2381 return -EINVAL;
2382 }
2383
2384 if (input[0] == 0) {
2385 if (input[1] < smu->gfx_default_hard_min_freq) {
2386 dev_warn(smu->adev->dev,
2387 "Fine grain setting minimum sclk (%ld) MHz is less than the minimum allowed (%d) MHz\n",
2388 input[1], smu->gfx_default_hard_min_freq);
2389 return -EINVAL;
2390 }
2391 smu->gfx_actual_hard_min_freq = input[1];
2392 } else if (input[0] == 1) {
2393 if (input[1] > smu->gfx_default_soft_max_freq) {
2394 dev_warn(smu->adev->dev,
2395 "Fine grain setting maximum sclk (%ld) MHz is greater than the maximum allowed (%d) MHz\n",
2396 input[1], smu->gfx_default_soft_max_freq);
2397 return -EINVAL;
2398 }
2399 smu->gfx_actual_soft_max_freq = input[1];
2400 } else {
2401 return -EINVAL;
2402 }
2403 break;
2404 case PP_OD_RESTORE_DEFAULT_TABLE:
2405 if (size != 0) {
2406 dev_err(smu->adev->dev, "Input parameter number not correct\n");
2407 return -EINVAL;
2408 }
2409 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
2410 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
2411 break;
2412 case PP_OD_COMMIT_DPM_TABLE:
2413 if (size != 0) {
2414 dev_err(smu->adev->dev, "Input parameter number not correct\n");
2415 return -EINVAL;
2416 }
2417 if (smu->gfx_actual_hard_min_freq > smu->gfx_actual_soft_max_freq) {
2418 dev_err(smu->adev->dev,
2419 "The setting minimum sclk (%d) MHz is greater than the setting maximum sclk (%d) MHz\n",
2420 smu->gfx_actual_hard_min_freq,
2421 smu->gfx_actual_soft_max_freq);
2422 return -EINVAL;
2423 }
2424
2425 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk,
2426 smu->gfx_actual_hard_min_freq,
2427 NULL);
2428 if (ret) {
2429 dev_err(smu->adev->dev, "Set hard min sclk failed!");
2430 return ret;
2431 }
2432
2433 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk,
2434 smu->gfx_actual_soft_max_freq,
2435 NULL);
2436 if (ret) {
2437 dev_err(smu->adev->dev, "Set soft max sclk failed!");
2438 return ret;
2439 }
2440 break;
2441 default:
2442 return -ENOSYS;
2443 }
2444
2445 return ret;
2446 }
2447
smu_v13_0_set_default_dpm_tables(struct smu_context * smu)2448 int smu_v13_0_set_default_dpm_tables(struct smu_context *smu)
2449 {
2450 struct smu_table_context *smu_table = &smu->smu_table;
2451
2452 return smu_cmn_update_table(smu, SMU_TABLE_DPMCLOCKS, 0,
2453 smu_table->clocks_table, false);
2454 }
2455
smu_v13_0_set_smu_mailbox_registers(struct smu_context * smu)2456 void smu_v13_0_set_smu_mailbox_registers(struct smu_context *smu)
2457 {
2458 struct amdgpu_device *adev = smu->adev;
2459
2460 smu->param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_82);
2461 smu->msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_66);
2462 smu->resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90);
2463 }
2464
smu_v13_0_mode1_reset(struct smu_context * smu)2465 int smu_v13_0_mode1_reset(struct smu_context *smu)
2466 {
2467 int ret = 0;
2468
2469 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_Mode1Reset, NULL);
2470 if (!ret)
2471 msleep(SMU13_MODE1_RESET_WAIT_TIME_IN_MS);
2472
2473 return ret;
2474 }
2475
smu_v13_0_update_pcie_parameters(struct smu_context * smu,uint8_t pcie_gen_cap,uint8_t pcie_width_cap)2476 int smu_v13_0_update_pcie_parameters(struct smu_context *smu,
2477 uint8_t pcie_gen_cap,
2478 uint8_t pcie_width_cap)
2479 {
2480 struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
2481 struct smu_13_0_pcie_table *pcie_table =
2482 &dpm_context->dpm_tables.pcie_table;
2483 int num_of_levels = pcie_table->num_of_link_levels;
2484 uint32_t smu_pcie_arg;
2485 int ret, i;
2486
2487 if (!num_of_levels)
2488 return 0;
2489
2490 if (!(smu->adev->pm.pp_feature & PP_PCIE_DPM_MASK)) {
2491 if (pcie_table->pcie_gen[num_of_levels - 1] < pcie_gen_cap)
2492 pcie_gen_cap = pcie_table->pcie_gen[num_of_levels - 1];
2493
2494 if (pcie_table->pcie_lane[num_of_levels - 1] < pcie_width_cap)
2495 pcie_width_cap = pcie_table->pcie_lane[num_of_levels - 1];
2496
2497 /* Force all levels to use the same settings */
2498 for (i = 0; i < num_of_levels; i++) {
2499 pcie_table->pcie_gen[i] = pcie_gen_cap;
2500 pcie_table->pcie_lane[i] = pcie_width_cap;
2501 }
2502 } else {
2503 for (i = 0; i < num_of_levels; i++) {
2504 if (pcie_table->pcie_gen[i] > pcie_gen_cap)
2505 pcie_table->pcie_gen[i] = pcie_gen_cap;
2506 if (pcie_table->pcie_lane[i] > pcie_width_cap)
2507 pcie_table->pcie_lane[i] = pcie_width_cap;
2508 }
2509 }
2510
2511 for (i = 0; i < num_of_levels; i++) {
2512 smu_pcie_arg = i << 16;
2513 smu_pcie_arg |= pcie_table->pcie_gen[i] << 8;
2514 smu_pcie_arg |= pcie_table->pcie_lane[i];
2515
2516 ret = smu_cmn_send_smc_msg_with_param(smu,
2517 SMU_MSG_OverridePcieParameters,
2518 smu_pcie_arg,
2519 NULL);
2520 if (ret)
2521 return ret;
2522 }
2523
2524 return 0;
2525 }
2526
smu_v13_0_disable_pmfw_state(struct smu_context * smu)2527 int smu_v13_0_disable_pmfw_state(struct smu_context *smu)
2528 {
2529 int ret;
2530 struct amdgpu_device *adev = smu->adev;
2531
2532 WREG32_PCIE(MP1_Public | (smnMP1_FIRMWARE_FLAGS & 0xffffffff), 0);
2533
2534 ret = RREG32_PCIE(MP1_Public |
2535 (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
2536
2537 return ret == 0 ? 0 : -EINVAL;
2538 }
2539
smu_v13_0_enable_uclk_shadow(struct smu_context * smu,bool enable)2540 int smu_v13_0_enable_uclk_shadow(struct smu_context *smu, bool enable)
2541 {
2542 return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_EnableUCLKShadow, enable, NULL);
2543 }
2544
smu_v13_0_set_wbrf_exclusion_ranges(struct smu_context * smu,struct freq_band_range * exclusion_ranges)2545 int smu_v13_0_set_wbrf_exclusion_ranges(struct smu_context *smu,
2546 struct freq_band_range *exclusion_ranges)
2547 {
2548 WifiBandEntryTable_t wifi_bands;
2549 int valid_entries = 0;
2550 int ret, i;
2551
2552 memset(&wifi_bands, 0, sizeof(wifi_bands));
2553 for (i = 0; i < ARRAY_SIZE(wifi_bands.WifiBandEntry); i++) {
2554 if (!exclusion_ranges[i].start && !exclusion_ranges[i].end)
2555 break;
2556
2557 /* PMFW expects the inputs to be in Mhz unit */
2558 wifi_bands.WifiBandEntry[valid_entries].LowFreq =
2559 DIV_ROUND_DOWN_ULL(exclusion_ranges[i].start, HZ_PER_MHZ);
2560 wifi_bands.WifiBandEntry[valid_entries++].HighFreq =
2561 DIV_ROUND_UP_ULL(exclusion_ranges[i].end, HZ_PER_MHZ);
2562 }
2563 wifi_bands.WifiBandEntryNum = valid_entries;
2564
2565 /*
2566 * Per confirm with PMFW team, WifiBandEntryNum = 0
2567 * is a valid setting.
2568 *
2569 * Considering the scenarios below:
2570 * - At first the wifi device adds an exclusion range e.g. (2400,2500) to
2571 * BIOS and our driver gets notified. We will set WifiBandEntryNum = 1
2572 * and pass the WifiBandEntry (2400, 2500) to PMFW.
2573 *
2574 * - Later the wifi device removes the wifiband list added above and
2575 * our driver gets notified again. At this time, driver will set
2576 * WifiBandEntryNum = 0 and pass an empty WifiBandEntry list to PMFW.
2577 *
2578 * - PMFW may still need to do some uclk shadow update(e.g. switching
2579 * from shadow clock back to primary clock) on receiving this.
2580 */
2581 ret = smu_cmn_update_table(smu, SMU_TABLE_WIFIBAND, 0, &wifi_bands, true);
2582 if (ret)
2583 dev_warn(smu->adev->dev, "Failed to set wifiband!");
2584
2585 return ret;
2586 }
2587