1 /*
2 * Copyright 2020 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #define SWSMU_CODE_LAYER_L2
25
26 #include "amdgpu.h"
27 #include "amdgpu_smu.h"
28 #include "smu_v13_0.h"
29 #include "smu13_driver_if_v13_0_5.h"
30 #include "smu_v13_0_5_ppt.h"
31 #include "smu_v13_0_5_ppsmc.h"
32 #include "smu_v13_0_5_pmfw.h"
33 #include "smu_cmn.h"
34
35 /*
36 * DO NOT use these for err/warn/info/debug messages.
37 * Use dev_err, dev_warn, dev_info and dev_dbg instead.
38 * They are more MGPU friendly.
39 */
40 #undef pr_err
41 #undef pr_warn
42 #undef pr_info
43 #undef pr_debug
44
45 #define mmMP1_C2PMSG_2 (0xbee142 + 0xb00000 / 4)
46 #define mmMP1_C2PMSG_2_BASE_IDX 0
47
48 #define mmMP1_C2PMSG_34 (0xbee262 + 0xb00000 / 4)
49 #define mmMP1_C2PMSG_34_BASE_IDX 0
50
51 #define mmMP1_C2PMSG_33 (0xbee261 + 0xb00000 / 4)
52 #define mmMP1_C2PMSG_33_BASE_IDX 0
53
54 #define FEATURE_MASK(feature) (1ULL << feature)
55 #define SMC_DPM_FEATURE ( \
56 FEATURE_MASK(FEATURE_CCLK_DPM_BIT) | \
57 FEATURE_MASK(FEATURE_FCLK_DPM_BIT) | \
58 FEATURE_MASK(FEATURE_LCLK_DPM_BIT) | \
59 FEATURE_MASK(FEATURE_GFX_DPM_BIT) | \
60 FEATURE_MASK(FEATURE_VCN_DPM_BIT) | \
61 FEATURE_MASK(FEATURE_DCFCLK_DPM_BIT) | \
62 FEATURE_MASK(FEATURE_SOCCLK_DPM_BIT)| \
63 FEATURE_MASK(FEATURE_MP0CLK_DPM_BIT)| \
64 FEATURE_MASK(FEATURE_SHUBCLK_DPM_BIT))
65
66 static struct cmn2asic_msg_mapping smu_v13_0_5_message_map[SMU_MSG_MAX_COUNT] = {
67 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 1),
68 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1),
69 MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn, 1),
70 MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn, 1),
71 MSG_MAP(SetHardMinVcn, PPSMC_MSG_SetHardMinVcn, 1),
72 MSG_MAP(SetSoftMinGfxclk, PPSMC_MSG_SetSoftMinGfxclk, 1),
73 MSG_MAP(Spare0, PPSMC_MSG_Spare0, 1),
74 MSG_MAP(GfxDeviceDriverReset, PPSMC_MSG_GfxDeviceDriverReset, 1),
75 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 1),
76 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 1),
77 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 1),
78 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 1),
79 MSG_MAP(GetGfxclkFrequency, PPSMC_MSG_GetGfxclkFrequency, 1),
80 MSG_MAP(GetEnabledSmuFeatures, PPSMC_MSG_GetEnabledSmuFeatures, 1),
81 MSG_MAP(SetSoftMaxVcn, PPSMC_MSG_SetSoftMaxVcn, 1),
82 MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg, 1),
83 MSG_MAP(PowerUpJpeg, PPSMC_MSG_PowerUpJpeg, 1),
84 MSG_MAP(SetSoftMaxGfxClk, PPSMC_MSG_SetSoftMaxGfxClk, 1),
85 MSG_MAP(SetHardMinGfxClk, PPSMC_MSG_SetHardMinGfxClk, 1),
86 MSG_MAP(AllowGfxOff, PPSMC_MSG_AllowGfxOff, 1),
87 MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisallowGfxOff, 1),
88 MSG_MAP(SetSoftMinVcn, PPSMC_MSG_SetSoftMinVcn, 1),
89 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1),
90 MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload, 1),
91 };
92
93 static struct cmn2asic_mapping smu_v13_0_5_feature_mask_map[SMU_FEATURE_COUNT] = {
94 FEA_MAP(DATA_CALCULATION),
95 FEA_MAP(PPT),
96 FEA_MAP(TDC),
97 FEA_MAP(THERMAL),
98 FEA_MAP(PROCHOT),
99 FEA_MAP(CCLK_DPM),
100 FEA_MAP_REVERSE(FCLK),
101 FEA_MAP(LCLK_DPM),
102 FEA_MAP(DF_CSTATES),
103 FEA_MAP(FAN_CONTROLLER),
104 FEA_MAP(CPPC),
105 FEA_MAP_HALF_REVERSE(GFX),
106 FEA_MAP(DS_GFXCLK),
107 FEA_MAP(S0I3),
108 FEA_MAP(VCN_DPM),
109 FEA_MAP(DS_VCN),
110 FEA_MAP(DCFCLK_DPM),
111 FEA_MAP(ATHUB_PG),
112 FEA_MAP_REVERSE(SOCCLK),
113 FEA_MAP(SHUBCLK_DPM),
114 FEA_MAP(GFXOFF),
115 };
116
117 static struct cmn2asic_mapping smu_v13_0_5_table_map[SMU_TABLE_COUNT] = {
118 TAB_MAP_VALID(WATERMARKS),
119 TAB_MAP_VALID(SMU_METRICS),
120 TAB_MAP_VALID(CUSTOM_DPM),
121 TAB_MAP_VALID(DPMCLOCKS),
122 };
123
smu_v13_0_5_init_smc_tables(struct smu_context * smu)124 static int smu_v13_0_5_init_smc_tables(struct smu_context *smu)
125 {
126 struct smu_table_context *smu_table = &smu->smu_table;
127 struct smu_table *tables = smu_table->tables;
128
129 SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
130 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
131 SMU_TABLE_INIT(tables, SMU_TABLE_DPMCLOCKS, sizeof(DpmClocks_t),
132 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
133 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
134 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
135
136 smu_table->clocks_table = kzalloc(sizeof(DpmClocks_t), GFP_KERNEL);
137 if (!smu_table->clocks_table)
138 goto err0_out;
139
140 smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
141 if (!smu_table->metrics_table)
142 goto err1_out;
143 smu_table->metrics_time = 0;
144
145 smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL);
146 if (!smu_table->watermarks_table)
147 goto err2_out;
148
149 smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v2_1);
150 smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
151 if (!smu_table->gpu_metrics_table)
152 goto err3_out;
153
154 return 0;
155
156 err3_out:
157 kfree(smu_table->watermarks_table);
158 err2_out:
159 kfree(smu_table->metrics_table);
160 err1_out:
161 kfree(smu_table->clocks_table);
162 err0_out:
163 return -ENOMEM;
164 }
165
smu_v13_0_5_fini_smc_tables(struct smu_context * smu)166 static int smu_v13_0_5_fini_smc_tables(struct smu_context *smu)
167 {
168 struct smu_table_context *smu_table = &smu->smu_table;
169
170 kfree(smu_table->clocks_table);
171 smu_table->clocks_table = NULL;
172
173 kfree(smu_table->metrics_table);
174 smu_table->metrics_table = NULL;
175
176 kfree(smu_table->watermarks_table);
177 smu_table->watermarks_table = NULL;
178
179 kfree(smu_table->gpu_metrics_table);
180 smu_table->gpu_metrics_table = NULL;
181
182 return 0;
183 }
184
smu_v13_0_5_system_features_control(struct smu_context * smu,bool en)185 static int smu_v13_0_5_system_features_control(struct smu_context *smu, bool en)
186 {
187 struct amdgpu_device *adev = smu->adev;
188 int ret = 0;
189
190 if (!en && !adev->in_s0ix)
191 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_PrepareMp1ForUnload, NULL);
192
193 return ret;
194 }
195
smu_v13_0_5_dpm_set_vcn_enable(struct smu_context * smu,bool enable)196 static int smu_v13_0_5_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
197 {
198 int ret = 0;
199
200 /* vcn dpm on is a prerequisite for vcn power gate messages */
201 if (enable)
202 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn,
203 0, NULL);
204 else
205 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownVcn,
206 0, NULL);
207
208 return ret;
209 }
210
smu_v13_0_5_dpm_set_jpeg_enable(struct smu_context * smu,bool enable)211 static int smu_v13_0_5_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)
212 {
213 int ret = 0;
214
215 if (enable)
216 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpJpeg,
217 0, NULL);
218 else
219 ret = smu_cmn_send_smc_msg_with_param(smu,
220 SMU_MSG_PowerDownJpeg, 0,
221 NULL);
222
223 return ret;
224 }
225
226
smu_v13_0_5_is_dpm_running(struct smu_context * smu)227 static bool smu_v13_0_5_is_dpm_running(struct smu_context *smu)
228 {
229 int ret = 0;
230 uint64_t feature_enabled;
231
232 ret = smu_cmn_get_enabled_mask(smu, &feature_enabled);
233
234 if (ret)
235 return false;
236
237 return !!(feature_enabled & SMC_DPM_FEATURE);
238 }
239
smu_v13_0_5_mode_reset(struct smu_context * smu,int type)240 static int smu_v13_0_5_mode_reset(struct smu_context *smu, int type)
241 {
242 int ret = 0;
243
244 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GfxDeviceDriverReset, type, NULL);
245 if (ret)
246 dev_err(smu->adev->dev, "Failed to mode reset!\n");
247
248 return ret;
249 }
250
smu_v13_0_5_mode2_reset(struct smu_context * smu)251 static int smu_v13_0_5_mode2_reset(struct smu_context *smu)
252 {
253 return smu_v13_0_5_mode_reset(smu, SMU_RESET_MODE_2);
254 }
255
smu_v13_0_5_get_smu_metrics_data(struct smu_context * smu,MetricsMember_t member,uint32_t * value)256 static int smu_v13_0_5_get_smu_metrics_data(struct smu_context *smu,
257 MetricsMember_t member,
258 uint32_t *value)
259 {
260 struct smu_table_context *smu_table = &smu->smu_table;
261
262 SmuMetrics_t *metrics = (SmuMetrics_t *)smu_table->metrics_table;
263 int ret = 0;
264
265 ret = smu_cmn_get_metrics_table(smu, NULL, false);
266 if (ret)
267 return ret;
268
269 switch (member) {
270 case METRICS_AVERAGE_GFXCLK:
271 *value = metrics->GfxclkFrequency;
272 break;
273 case METRICS_AVERAGE_SOCCLK:
274 *value = metrics->SocclkFrequency;
275 break;
276 case METRICS_AVERAGE_VCLK:
277 *value = metrics->VclkFrequency;
278 break;
279 case METRICS_AVERAGE_DCLK:
280 *value = metrics->DclkFrequency;
281 break;
282 case METRICS_AVERAGE_UCLK:
283 *value = metrics->MemclkFrequency;
284 break;
285 case METRICS_AVERAGE_GFXACTIVITY:
286 *value = metrics->GfxActivity / 100;
287 break;
288 case METRICS_AVERAGE_VCNACTIVITY:
289 *value = metrics->UvdActivity / 100;
290 break;
291 case METRICS_CURR_SOCKETPOWER:
292 *value = (metrics->CurrentSocketPower << 8) / 1000;
293 break;
294 case METRICS_TEMPERATURE_EDGE:
295 *value = metrics->GfxTemperature / 100 *
296 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
297 break;
298 case METRICS_TEMPERATURE_HOTSPOT:
299 *value = metrics->SocTemperature / 100 *
300 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
301 break;
302 case METRICS_THROTTLER_STATUS:
303 *value = metrics->ThrottlerStatus;
304 break;
305 case METRICS_VOLTAGE_VDDGFX:
306 *value = metrics->Voltage[0];
307 break;
308 case METRICS_VOLTAGE_VDDSOC:
309 *value = metrics->Voltage[1];
310 break;
311 default:
312 *value = UINT_MAX;
313 break;
314 }
315
316 return ret;
317 }
318
smu_v13_0_5_read_sensor(struct smu_context * smu,enum amd_pp_sensors sensor,void * data,uint32_t * size)319 static int smu_v13_0_5_read_sensor(struct smu_context *smu,
320 enum amd_pp_sensors sensor,
321 void *data, uint32_t *size)
322 {
323 int ret = 0;
324
325 if (!data || !size)
326 return -EINVAL;
327
328 switch (sensor) {
329 case AMDGPU_PP_SENSOR_GPU_LOAD:
330 ret = smu_v13_0_5_get_smu_metrics_data(smu,
331 METRICS_AVERAGE_GFXACTIVITY,
332 (uint32_t *)data);
333 *size = 4;
334 break;
335 case AMDGPU_PP_SENSOR_VCN_LOAD:
336 ret = smu_v13_0_5_get_smu_metrics_data(smu,
337 METRICS_AVERAGE_VCNACTIVITY,
338 (uint32_t *)data);
339 *size = 4;
340 break;
341 case AMDGPU_PP_SENSOR_GPU_INPUT_POWER:
342 ret = smu_v13_0_5_get_smu_metrics_data(smu,
343 METRICS_CURR_SOCKETPOWER,
344 (uint32_t *)data);
345 *size = 4;
346 break;
347 case AMDGPU_PP_SENSOR_EDGE_TEMP:
348 ret = smu_v13_0_5_get_smu_metrics_data(smu,
349 METRICS_TEMPERATURE_EDGE,
350 (uint32_t *)data);
351 *size = 4;
352 break;
353 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
354 ret = smu_v13_0_5_get_smu_metrics_data(smu,
355 METRICS_TEMPERATURE_HOTSPOT,
356 (uint32_t *)data);
357 *size = 4;
358 break;
359 case AMDGPU_PP_SENSOR_GFX_MCLK:
360 ret = smu_v13_0_5_get_smu_metrics_data(smu,
361 METRICS_AVERAGE_UCLK,
362 (uint32_t *)data);
363 *(uint32_t *)data *= 100;
364 *size = 4;
365 break;
366 case AMDGPU_PP_SENSOR_GFX_SCLK:
367 ret = smu_v13_0_5_get_smu_metrics_data(smu,
368 METRICS_AVERAGE_GFXCLK,
369 (uint32_t *)data);
370 *(uint32_t *)data *= 100;
371 *size = 4;
372 break;
373 case AMDGPU_PP_SENSOR_VDDGFX:
374 ret = smu_v13_0_5_get_smu_metrics_data(smu,
375 METRICS_VOLTAGE_VDDGFX,
376 (uint32_t *)data);
377 *size = 4;
378 break;
379 case AMDGPU_PP_SENSOR_VDDNB:
380 ret = smu_v13_0_5_get_smu_metrics_data(smu,
381 METRICS_VOLTAGE_VDDSOC,
382 (uint32_t *)data);
383 *size = 4;
384 break;
385 case AMDGPU_PP_SENSOR_SS_APU_SHARE:
386 ret = smu_v13_0_5_get_smu_metrics_data(smu,
387 METRICS_SS_APU_SHARE,
388 (uint32_t *)data);
389 *size = 4;
390 break;
391 case AMDGPU_PP_SENSOR_SS_DGPU_SHARE:
392 ret = smu_v13_0_5_get_smu_metrics_data(smu,
393 METRICS_SS_DGPU_SHARE,
394 (uint32_t *)data);
395 *size = 4;
396 break;
397 case AMDGPU_PP_SENSOR_GPU_AVG_POWER:
398 default:
399 ret = -EOPNOTSUPP;
400 break;
401 }
402
403 return ret;
404 }
405
smu_v13_0_5_set_watermarks_table(struct smu_context * smu,struct pp_smu_wm_range_sets * clock_ranges)406 static int smu_v13_0_5_set_watermarks_table(struct smu_context *smu,
407 struct pp_smu_wm_range_sets *clock_ranges)
408 {
409 int i;
410 int ret = 0;
411 Watermarks_t *table = smu->smu_table.watermarks_table;
412
413 if (!table || !clock_ranges)
414 return -EINVAL;
415
416 if (clock_ranges) {
417 if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES ||
418 clock_ranges->num_writer_wm_sets > NUM_WM_RANGES)
419 return -EINVAL;
420
421 for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) {
422 table->WatermarkRow[WM_DCFCLK][i].MinClock =
423 clock_ranges->reader_wm_sets[i].min_drain_clk_mhz;
424 table->WatermarkRow[WM_DCFCLK][i].MaxClock =
425 clock_ranges->reader_wm_sets[i].max_drain_clk_mhz;
426 table->WatermarkRow[WM_DCFCLK][i].MinMclk =
427 clock_ranges->reader_wm_sets[i].min_fill_clk_mhz;
428 table->WatermarkRow[WM_DCFCLK][i].MaxMclk =
429 clock_ranges->reader_wm_sets[i].max_fill_clk_mhz;
430
431 table->WatermarkRow[WM_DCFCLK][i].WmSetting =
432 clock_ranges->reader_wm_sets[i].wm_inst;
433 }
434
435 for (i = 0; i < clock_ranges->num_writer_wm_sets; i++) {
436 table->WatermarkRow[WM_SOCCLK][i].MinClock =
437 clock_ranges->writer_wm_sets[i].min_fill_clk_mhz;
438 table->WatermarkRow[WM_SOCCLK][i].MaxClock =
439 clock_ranges->writer_wm_sets[i].max_fill_clk_mhz;
440 table->WatermarkRow[WM_SOCCLK][i].MinMclk =
441 clock_ranges->writer_wm_sets[i].min_drain_clk_mhz;
442 table->WatermarkRow[WM_SOCCLK][i].MaxMclk =
443 clock_ranges->writer_wm_sets[i].max_drain_clk_mhz;
444
445 table->WatermarkRow[WM_SOCCLK][i].WmSetting =
446 clock_ranges->writer_wm_sets[i].wm_inst;
447 }
448
449 smu->watermarks_bitmap |= WATERMARKS_EXIST;
450 }
451
452 /* pass data to smu controller */
453 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
454 !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
455 ret = smu_cmn_write_watermarks_table(smu);
456 if (ret) {
457 dev_err(smu->adev->dev, "Failed to update WMTABLE!");
458 return ret;
459 }
460 smu->watermarks_bitmap |= WATERMARKS_LOADED;
461 }
462
463 return 0;
464 }
465
smu_v13_0_5_get_gpu_metrics(struct smu_context * smu,void ** table)466 static ssize_t smu_v13_0_5_get_gpu_metrics(struct smu_context *smu,
467 void **table)
468 {
469 struct smu_table_context *smu_table = &smu->smu_table;
470 struct gpu_metrics_v2_1 *gpu_metrics =
471 (struct gpu_metrics_v2_1 *)smu_table->gpu_metrics_table;
472 SmuMetrics_t metrics;
473 int ret = 0;
474
475 ret = smu_cmn_get_metrics_table(smu, &metrics, true);
476 if (ret)
477 return ret;
478
479 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 1);
480
481 gpu_metrics->temperature_gfx = metrics.GfxTemperature;
482 gpu_metrics->temperature_soc = metrics.SocTemperature;
483
484 gpu_metrics->average_gfx_activity = metrics.GfxActivity;
485 gpu_metrics->average_mm_activity = metrics.UvdActivity;
486
487 gpu_metrics->average_socket_power = metrics.CurrentSocketPower;
488 gpu_metrics->average_gfx_power = metrics.Power[0];
489 gpu_metrics->average_soc_power = metrics.Power[1];
490 gpu_metrics->average_gfxclk_frequency = metrics.GfxclkFrequency;
491 gpu_metrics->average_socclk_frequency = metrics.SocclkFrequency;
492 gpu_metrics->average_uclk_frequency = metrics.MemclkFrequency;
493 gpu_metrics->average_fclk_frequency = metrics.MemclkFrequency;
494 gpu_metrics->average_vclk_frequency = metrics.VclkFrequency;
495 gpu_metrics->average_dclk_frequency = metrics.DclkFrequency;
496 gpu_metrics->throttle_status = metrics.ThrottlerStatus;
497 gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
498
499 *table = (void *)gpu_metrics;
500
501 return sizeof(struct gpu_metrics_v2_1);
502 }
503
smu_v13_0_5_set_default_dpm_tables(struct smu_context * smu)504 static int smu_v13_0_5_set_default_dpm_tables(struct smu_context *smu)
505 {
506 struct smu_table_context *smu_table = &smu->smu_table;
507
508 return smu_cmn_update_table(smu, SMU_TABLE_DPMCLOCKS, 0, smu_table->clocks_table, false);
509 }
510
smu_v13_0_5_od_edit_dpm_table(struct smu_context * smu,enum PP_OD_DPM_TABLE_COMMAND type,long input[],uint32_t size)511 static int smu_v13_0_5_od_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TABLE_COMMAND type,
512 long input[], uint32_t size)
513 {
514 struct smu_dpm_context *smu_dpm = &(smu->smu_dpm);
515 int ret = 0;
516
517 /* Only allowed in manual mode */
518 if (smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
519 return -EINVAL;
520
521 switch (type) {
522 case PP_OD_EDIT_SCLK_VDDC_TABLE:
523 if (size != 2) {
524 dev_err(smu->adev->dev, "Input parameter number not correct\n");
525 return -EINVAL;
526 }
527
528 if (input[0] == 0) {
529 if (input[1] < smu->gfx_default_hard_min_freq) {
530 dev_warn(smu->adev->dev,
531 "Fine grain setting minimum sclk (%ld) MHz is less than the minimum allowed (%d) MHz\n",
532 input[1], smu->gfx_default_hard_min_freq);
533 return -EINVAL;
534 }
535 smu->gfx_actual_hard_min_freq = input[1];
536 } else if (input[0] == 1) {
537 if (input[1] > smu->gfx_default_soft_max_freq) {
538 dev_warn(smu->adev->dev,
539 "Fine grain setting maximum sclk (%ld) MHz is greater than the maximum allowed (%d) MHz\n",
540 input[1], smu->gfx_default_soft_max_freq);
541 return -EINVAL;
542 }
543 smu->gfx_actual_soft_max_freq = input[1];
544 } else {
545 return -EINVAL;
546 }
547 break;
548 case PP_OD_RESTORE_DEFAULT_TABLE:
549 if (size != 0) {
550 dev_err(smu->adev->dev, "Input parameter number not correct\n");
551 return -EINVAL;
552 } else {
553 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
554 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
555 }
556 break;
557 case PP_OD_COMMIT_DPM_TABLE:
558 if (size != 0) {
559 dev_err(smu->adev->dev, "Input parameter number not correct\n");
560 return -EINVAL;
561 } else {
562 if (smu->gfx_actual_hard_min_freq > smu->gfx_actual_soft_max_freq) {
563 dev_err(smu->adev->dev,
564 "The setting minimum sclk (%d) MHz is greater than the setting maximum sclk (%d) MHz\n",
565 smu->gfx_actual_hard_min_freq,
566 smu->gfx_actual_soft_max_freq);
567 return -EINVAL;
568 }
569
570 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk,
571 smu->gfx_actual_hard_min_freq, NULL);
572 if (ret) {
573 dev_err(smu->adev->dev, "Set hard min sclk failed!");
574 return ret;
575 }
576
577 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk,
578 smu->gfx_actual_soft_max_freq, NULL);
579 if (ret) {
580 dev_err(smu->adev->dev, "Set soft max sclk failed!");
581 return ret;
582 }
583 }
584 break;
585 default:
586 return -ENOSYS;
587 }
588
589 return ret;
590 }
591
smu_v13_0_5_get_current_clk_freq(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * value)592 static int smu_v13_0_5_get_current_clk_freq(struct smu_context *smu,
593 enum smu_clk_type clk_type,
594 uint32_t *value)
595 {
596 MetricsMember_t member_type;
597
598 switch (clk_type) {
599 case SMU_SOCCLK:
600 member_type = METRICS_AVERAGE_SOCCLK;
601 break;
602 case SMU_VCLK:
603 member_type = METRICS_AVERAGE_VCLK;
604 break;
605 case SMU_DCLK:
606 member_type = METRICS_AVERAGE_DCLK;
607 break;
608 case SMU_MCLK:
609 member_type = METRICS_AVERAGE_UCLK;
610 break;
611 case SMU_GFXCLK:
612 case SMU_SCLK:
613 return smu_cmn_send_smc_msg_with_param(smu,
614 SMU_MSG_GetGfxclkFrequency, 0, value);
615 break;
616 default:
617 return -EINVAL;
618 }
619
620 return smu_v13_0_5_get_smu_metrics_data(smu, member_type, value);
621 }
622
smu_v13_0_5_get_dpm_level_count(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * count)623 static int smu_v13_0_5_get_dpm_level_count(struct smu_context *smu,
624 enum smu_clk_type clk_type,
625 uint32_t *count)
626 {
627 DpmClocks_t *clk_table = smu->smu_table.clocks_table;
628
629 switch (clk_type) {
630 case SMU_SOCCLK:
631 *count = clk_table->NumSocClkLevelsEnabled;
632 break;
633 case SMU_VCLK:
634 *count = clk_table->VcnClkLevelsEnabled;
635 break;
636 case SMU_DCLK:
637 *count = clk_table->VcnClkLevelsEnabled;
638 break;
639 case SMU_MCLK:
640 *count = clk_table->NumDfPstatesEnabled;
641 break;
642 case SMU_FCLK:
643 *count = clk_table->NumDfPstatesEnabled;
644 break;
645 default:
646 return -EINVAL;
647 }
648
649 return 0;
650 }
651
smu_v13_0_5_get_dpm_freq_by_index(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t dpm_level,uint32_t * freq)652 static int smu_v13_0_5_get_dpm_freq_by_index(struct smu_context *smu,
653 enum smu_clk_type clk_type,
654 uint32_t dpm_level,
655 uint32_t *freq)
656 {
657 DpmClocks_t *clk_table = smu->smu_table.clocks_table;
658
659 if (!clk_table || clk_type >= SMU_CLK_COUNT)
660 return -EINVAL;
661
662 switch (clk_type) {
663 case SMU_SOCCLK:
664 if (dpm_level >= clk_table->NumSocClkLevelsEnabled)
665 return -EINVAL;
666 *freq = clk_table->SocClocks[dpm_level];
667 break;
668 case SMU_VCLK:
669 if (dpm_level >= clk_table->VcnClkLevelsEnabled)
670 return -EINVAL;
671 *freq = clk_table->VClocks[dpm_level];
672 break;
673 case SMU_DCLK:
674 if (dpm_level >= clk_table->VcnClkLevelsEnabled)
675 return -EINVAL;
676 *freq = clk_table->DClocks[dpm_level];
677 break;
678 case SMU_UCLK:
679 case SMU_MCLK:
680 if (dpm_level >= clk_table->NumDfPstatesEnabled)
681 return -EINVAL;
682 *freq = clk_table->DfPstateTable[dpm_level].MemClk;
683 break;
684 case SMU_FCLK:
685 if (dpm_level >= clk_table->NumDfPstatesEnabled)
686 return -EINVAL;
687 *freq = clk_table->DfPstateTable[dpm_level].FClk;
688 break;
689 default:
690 return -EINVAL;
691 }
692
693 return 0;
694 }
695
smu_v13_0_5_clk_dpm_is_enabled(struct smu_context * smu,enum smu_clk_type clk_type)696 static bool smu_v13_0_5_clk_dpm_is_enabled(struct smu_context *smu,
697 enum smu_clk_type clk_type)
698 {
699 enum smu_feature_mask feature_id = 0;
700
701 switch (clk_type) {
702 case SMU_MCLK:
703 case SMU_UCLK:
704 case SMU_FCLK:
705 feature_id = SMU_FEATURE_DPM_FCLK_BIT;
706 break;
707 case SMU_GFXCLK:
708 case SMU_SCLK:
709 feature_id = SMU_FEATURE_DPM_GFXCLK_BIT;
710 break;
711 case SMU_SOCCLK:
712 feature_id = SMU_FEATURE_DPM_SOCCLK_BIT;
713 break;
714 case SMU_VCLK:
715 case SMU_DCLK:
716 feature_id = SMU_FEATURE_VCN_DPM_BIT;
717 break;
718 default:
719 return true;
720 }
721
722 return smu_cmn_feature_is_enabled(smu, feature_id);
723 }
724
smu_v13_0_5_get_dpm_ultimate_freq(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * min,uint32_t * max)725 static int smu_v13_0_5_get_dpm_ultimate_freq(struct smu_context *smu,
726 enum smu_clk_type clk_type,
727 uint32_t *min,
728 uint32_t *max)
729 {
730 DpmClocks_t *clk_table = smu->smu_table.clocks_table;
731 uint32_t clock_limit;
732 uint32_t max_dpm_level, min_dpm_level;
733 int ret = 0;
734
735 if (!smu_v13_0_5_clk_dpm_is_enabled(smu, clk_type)) {
736 ret = smu_v13_0_get_boot_freq_by_index(smu, clk_type, &clock_limit);
737 if (ret)
738 return ret;
739
740 /* clock in Mhz unit */
741 if (min)
742 *min = clock_limit / 100;
743 if (max)
744 *max = clock_limit / 100;
745
746 return 0;
747 }
748
749 if (max) {
750 switch (clk_type) {
751 case SMU_GFXCLK:
752 case SMU_SCLK:
753 *max = clk_table->MaxGfxClk;
754 break;
755 case SMU_MCLK:
756 case SMU_UCLK:
757 case SMU_FCLK:
758 max_dpm_level = 0;
759 break;
760 case SMU_SOCCLK:
761 max_dpm_level = clk_table->NumSocClkLevelsEnabled - 1;
762 break;
763 case SMU_VCLK:
764 case SMU_DCLK:
765 max_dpm_level = clk_table->VcnClkLevelsEnabled - 1;
766 break;
767 default:
768 ret = -EINVAL;
769 goto failed;
770 }
771
772 if (clk_type != SMU_GFXCLK && clk_type != SMU_SCLK) {
773 ret = smu_v13_0_5_get_dpm_freq_by_index(smu, clk_type, max_dpm_level, max);
774 if (ret)
775 goto failed;
776 }
777 }
778
779 if (min) {
780 switch (clk_type) {
781 case SMU_GFXCLK:
782 case SMU_SCLK:
783 *min = clk_table->MinGfxClk;
784 break;
785 case SMU_MCLK:
786 case SMU_UCLK:
787 case SMU_FCLK:
788 min_dpm_level = clk_table->NumDfPstatesEnabled - 1;
789 break;
790 case SMU_SOCCLK:
791 min_dpm_level = 0;
792 break;
793 case SMU_VCLK:
794 case SMU_DCLK:
795 min_dpm_level = 0;
796 break;
797 default:
798 ret = -EINVAL;
799 goto failed;
800 }
801
802 if (clk_type != SMU_GFXCLK && clk_type != SMU_SCLK) {
803 ret = smu_v13_0_5_get_dpm_freq_by_index(smu, clk_type, min_dpm_level, min);
804 if (ret)
805 goto failed;
806 }
807 }
808
809 failed:
810 return ret;
811 }
812
smu_v13_0_5_set_soft_freq_limited_range(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t min,uint32_t max)813 static int smu_v13_0_5_set_soft_freq_limited_range(struct smu_context *smu,
814 enum smu_clk_type clk_type,
815 uint32_t min,
816 uint32_t max)
817 {
818 enum smu_message_type msg_set_min, msg_set_max;
819 uint32_t min_clk = min;
820 uint32_t max_clk = max;
821 int ret = 0;
822
823 if (!smu_v13_0_5_clk_dpm_is_enabled(smu, clk_type))
824 return -EINVAL;
825
826 switch (clk_type) {
827 case SMU_GFXCLK:
828 case SMU_SCLK:
829 msg_set_min = SMU_MSG_SetHardMinGfxClk;
830 msg_set_max = SMU_MSG_SetSoftMaxGfxClk;
831 break;
832 case SMU_VCLK:
833 case SMU_DCLK:
834 msg_set_min = SMU_MSG_SetHardMinVcn;
835 msg_set_max = SMU_MSG_SetSoftMaxVcn;
836 break;
837 default:
838 return -EINVAL;
839 }
840
841 if (clk_type == SMU_VCLK) {
842 min_clk = min << SMU_13_VCLK_SHIFT;
843 max_clk = max << SMU_13_VCLK_SHIFT;
844 }
845
846 ret = smu_cmn_send_smc_msg_with_param(smu, msg_set_min, min_clk, NULL);
847 if (ret)
848 goto out;
849
850 ret = smu_cmn_send_smc_msg_with_param(smu, msg_set_max, max_clk, NULL);
851 if (ret)
852 goto out;
853
854 out:
855 return ret;
856 }
857
smu_v13_0_5_print_clk_levels(struct smu_context * smu,enum smu_clk_type clk_type,char * buf)858 static int smu_v13_0_5_print_clk_levels(struct smu_context *smu,
859 enum smu_clk_type clk_type, char *buf)
860 {
861 int i, idx, size = 0, ret = 0;
862 uint32_t cur_value = 0, value = 0, count = 0;
863 uint32_t min = 0, max = 0;
864
865 smu_cmn_get_sysfs_buf(&buf, &size);
866
867 switch (clk_type) {
868 case SMU_OD_SCLK:
869 size += sysfs_emit_at(buf, size, "%s:\n", "OD_SCLK");
870 size += sysfs_emit_at(buf, size, "0: %10uMhz\n",
871 (smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq);
872 size += sysfs_emit_at(buf, size, "1: %10uMhz\n",
873 (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq);
874 break;
875 case SMU_OD_RANGE:
876 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
877 size += sysfs_emit_at(buf, size, "SCLK: %7uMhz %10uMhz\n",
878 smu->gfx_default_hard_min_freq, smu->gfx_default_soft_max_freq);
879 break;
880 case SMU_SOCCLK:
881 case SMU_VCLK:
882 case SMU_DCLK:
883 case SMU_MCLK:
884 ret = smu_v13_0_5_get_current_clk_freq(smu, clk_type, &cur_value);
885 if (ret)
886 goto print_clk_out;
887
888 ret = smu_v13_0_5_get_dpm_level_count(smu, clk_type, &count);
889 if (ret)
890 goto print_clk_out;
891
892 for (i = 0; i < count; i++) {
893 idx = (clk_type == SMU_MCLK) ? (count - i - 1) : i;
894 ret = smu_v13_0_5_get_dpm_freq_by_index(smu, clk_type, idx, &value);
895 if (ret)
896 goto print_clk_out;
897
898 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, value,
899 cur_value == value ? "*" : "");
900 }
901 break;
902 case SMU_GFXCLK:
903 case SMU_SCLK:
904 ret = smu_v13_0_5_get_current_clk_freq(smu, clk_type, &cur_value);
905 if (ret)
906 goto print_clk_out;
907 min = (smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq;
908 max = (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq;
909 if (cur_value == max)
910 i = 2;
911 else if (cur_value == min)
912 i = 0;
913 else
914 i = 1;
915 size += sysfs_emit_at(buf, size, "0: %uMhz %s\n", min,
916 i == 0 ? "*" : "");
917 size += sysfs_emit_at(buf, size, "1: %uMhz %s\n",
918 i == 1 ? cur_value : SMU_13_0_5_UMD_PSTATE_GFXCLK,
919 i == 1 ? "*" : "");
920 size += sysfs_emit_at(buf, size, "2: %uMhz %s\n", max,
921 i == 2 ? "*" : "");
922 break;
923 default:
924 break;
925 }
926
927 print_clk_out:
928 return size;
929 }
930
931
smu_v13_0_5_force_clk_levels(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t mask)932 static int smu_v13_0_5_force_clk_levels(struct smu_context *smu,
933 enum smu_clk_type clk_type, uint32_t mask)
934 {
935 uint32_t soft_min_level = 0, soft_max_level = 0;
936 uint32_t min_freq = 0, max_freq = 0;
937 int ret = 0;
938
939 soft_min_level = mask ? (ffs(mask) - 1) : 0;
940 soft_max_level = mask ? (fls(mask) - 1) : 0;
941
942 switch (clk_type) {
943 case SMU_VCLK:
944 case SMU_DCLK:
945 ret = smu_v13_0_5_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq);
946 if (ret)
947 goto force_level_out;
948
949 ret = smu_v13_0_5_get_dpm_freq_by_index(smu, clk_type, soft_max_level, &max_freq);
950 if (ret)
951 goto force_level_out;
952
953 ret = smu_v13_0_5_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq);
954 if (ret)
955 goto force_level_out;
956 break;
957 default:
958 ret = -EINVAL;
959 break;
960 }
961
962 force_level_out:
963 return ret;
964 }
965
smu_v13_0_5_get_dpm_profile_freq(struct smu_context * smu,enum amd_dpm_forced_level level,enum smu_clk_type clk_type,uint32_t * min_clk,uint32_t * max_clk)966 static int smu_v13_0_5_get_dpm_profile_freq(struct smu_context *smu,
967 enum amd_dpm_forced_level level,
968 enum smu_clk_type clk_type,
969 uint32_t *min_clk,
970 uint32_t *max_clk)
971 {
972 int ret = 0;
973 uint32_t clk_limit = 0;
974
975 switch (clk_type) {
976 case SMU_GFXCLK:
977 case SMU_SCLK:
978 clk_limit = SMU_13_0_5_UMD_PSTATE_GFXCLK;
979 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
980 smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_SCLK, NULL, &clk_limit);
981 else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK)
982 smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_SCLK, &clk_limit, NULL);
983 break;
984 case SMU_VCLK:
985 smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_VCLK, NULL, &clk_limit);
986 break;
987 case SMU_DCLK:
988 smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_DCLK, NULL, &clk_limit);
989 break;
990 default:
991 ret = -EINVAL;
992 break;
993 }
994 *min_clk = *max_clk = clk_limit;
995 return ret;
996 }
997
smu_v13_0_5_set_performance_level(struct smu_context * smu,enum amd_dpm_forced_level level)998 static int smu_v13_0_5_set_performance_level(struct smu_context *smu,
999 enum amd_dpm_forced_level level)
1000 {
1001 struct amdgpu_device *adev = smu->adev;
1002 uint32_t sclk_min = 0, sclk_max = 0;
1003 uint32_t vclk_min = 0, vclk_max = 0;
1004 uint32_t dclk_min = 0, dclk_max = 0;
1005 int ret = 0;
1006
1007 switch (level) {
1008 case AMD_DPM_FORCED_LEVEL_HIGH:
1009 smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_SCLK, NULL, &sclk_max);
1010 smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_VCLK, NULL, &vclk_max);
1011 smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_DCLK, NULL, &dclk_max);
1012 sclk_min = sclk_max;
1013 vclk_min = vclk_max;
1014 dclk_min = dclk_max;
1015 break;
1016 case AMD_DPM_FORCED_LEVEL_LOW:
1017 smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_SCLK, &sclk_min, NULL);
1018 smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_VCLK, &vclk_min, NULL);
1019 smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_DCLK, &dclk_min, NULL);
1020 sclk_max = sclk_min;
1021 vclk_max = vclk_min;
1022 dclk_max = dclk_min;
1023 break;
1024 case AMD_DPM_FORCED_LEVEL_AUTO:
1025 smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_SCLK, &sclk_min, &sclk_max);
1026 smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_VCLK, &vclk_min, &vclk_max);
1027 smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_DCLK, &dclk_min, &dclk_max);
1028 break;
1029 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1030 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1031 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1032 smu_v13_0_5_get_dpm_profile_freq(smu, level, SMU_SCLK, &sclk_min, &sclk_max);
1033 smu_v13_0_5_get_dpm_profile_freq(smu, level, SMU_VCLK, &vclk_min, &vclk_max);
1034 smu_v13_0_5_get_dpm_profile_freq(smu, level, SMU_DCLK, &dclk_min, &dclk_max);
1035 break;
1036 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1037 dev_err(adev->dev, "The performance level profile_min_mclk is not supported.");
1038 return -EOPNOTSUPP;
1039 case AMD_DPM_FORCED_LEVEL_MANUAL:
1040 case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
1041 return 0;
1042 default:
1043 dev_err(adev->dev, "Invalid performance level %d\n", level);
1044 return -EINVAL;
1045 }
1046
1047 if (sclk_min && sclk_max) {
1048 ret = smu_v13_0_5_set_soft_freq_limited_range(smu,
1049 SMU_SCLK,
1050 sclk_min,
1051 sclk_max);
1052 if (ret)
1053 return ret;
1054
1055 smu->gfx_actual_hard_min_freq = sclk_min;
1056 smu->gfx_actual_soft_max_freq = sclk_max;
1057 }
1058
1059 if (vclk_min && vclk_max) {
1060 ret = smu_v13_0_5_set_soft_freq_limited_range(smu,
1061 SMU_VCLK,
1062 vclk_min,
1063 vclk_max);
1064 if (ret)
1065 return ret;
1066 }
1067
1068 if (dclk_min && dclk_max) {
1069 ret = smu_v13_0_5_set_soft_freq_limited_range(smu,
1070 SMU_DCLK,
1071 dclk_min,
1072 dclk_max);
1073 if (ret)
1074 return ret;
1075 }
1076 return ret;
1077 }
1078
smu_v13_0_5_set_fine_grain_gfx_freq_parameters(struct smu_context * smu)1079 static int smu_v13_0_5_set_fine_grain_gfx_freq_parameters(struct smu_context *smu)
1080 {
1081 DpmClocks_t *clk_table = smu->smu_table.clocks_table;
1082
1083 smu->gfx_default_hard_min_freq = clk_table->MinGfxClk;
1084 smu->gfx_default_soft_max_freq = clk_table->MaxGfxClk;
1085 smu->gfx_actual_hard_min_freq = 0;
1086 smu->gfx_actual_soft_max_freq = 0;
1087
1088 return 0;
1089 }
1090
1091 static const struct pptable_funcs smu_v13_0_5_ppt_funcs = {
1092 .check_fw_status = smu_v13_0_check_fw_status,
1093 .check_fw_version = smu_v13_0_check_fw_version,
1094 .init_smc_tables = smu_v13_0_5_init_smc_tables,
1095 .fini_smc_tables = smu_v13_0_5_fini_smc_tables,
1096 .get_vbios_bootup_values = smu_v13_0_get_vbios_bootup_values,
1097 .system_features_control = smu_v13_0_5_system_features_control,
1098 .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param,
1099 .send_smc_msg = smu_cmn_send_smc_msg,
1100 .dpm_set_vcn_enable = smu_v13_0_5_dpm_set_vcn_enable,
1101 .dpm_set_jpeg_enable = smu_v13_0_5_dpm_set_jpeg_enable,
1102 .set_default_dpm_table = smu_v13_0_5_set_default_dpm_tables,
1103 .read_sensor = smu_v13_0_5_read_sensor,
1104 .is_dpm_running = smu_v13_0_5_is_dpm_running,
1105 .set_watermarks_table = smu_v13_0_5_set_watermarks_table,
1106 .get_gpu_metrics = smu_v13_0_5_get_gpu_metrics,
1107 .get_enabled_mask = smu_cmn_get_enabled_mask,
1108 .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
1109 .set_driver_table_location = smu_v13_0_set_driver_table_location,
1110 .gfx_off_control = smu_v13_0_gfx_off_control,
1111 .mode2_reset = smu_v13_0_5_mode2_reset,
1112 .get_dpm_ultimate_freq = smu_v13_0_5_get_dpm_ultimate_freq,
1113 .od_edit_dpm_table = smu_v13_0_5_od_edit_dpm_table,
1114 .print_clk_levels = smu_v13_0_5_print_clk_levels,
1115 .force_clk_levels = smu_v13_0_5_force_clk_levels,
1116 .set_performance_level = smu_v13_0_5_set_performance_level,
1117 .set_fine_grain_gfx_freq_parameters = smu_v13_0_5_set_fine_grain_gfx_freq_parameters,
1118 };
1119
smu_v13_0_5_set_ppt_funcs(struct smu_context * smu)1120 void smu_v13_0_5_set_ppt_funcs(struct smu_context *smu)
1121 {
1122 struct amdgpu_device *adev = smu->adev;
1123
1124 smu->ppt_funcs = &smu_v13_0_5_ppt_funcs;
1125 smu->message_map = smu_v13_0_5_message_map;
1126 smu->feature_map = smu_v13_0_5_feature_mask_map;
1127 smu->table_map = smu_v13_0_5_table_map;
1128 smu->is_apu = true;
1129 smu->smc_driver_if_version = SMU13_0_5_DRIVER_IF_VERSION;
1130 smu->param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_C2PMSG_34);
1131 smu->msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_C2PMSG_2);
1132 smu->resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_C2PMSG_33);
1133 }
1134