1 // SPDX-License-Identifier: MIT
2 /*
3 * Copyright © 2020 Intel Corporation
4 */
5
6 #include "i915_reg.h"
7 #include "intel_de.h"
8 #include "intel_display_types.h"
9 #include "intel_fb.h"
10 #include "skl_scaler.h"
11 #include "skl_universal_plane.h"
12
13 /*
14 * The hardware phase 0.0 refers to the center of the pixel.
15 * We want to start from the top/left edge which is phase
16 * -0.5. That matches how the hardware calculates the scaling
17 * factors (from top-left of the first pixel to bottom-right
18 * of the last pixel, as opposed to the pixel centers).
19 *
20 * For 4:2:0 subsampled chroma planes we obviously have to
21 * adjust that so that the chroma sample position lands in
22 * the right spot.
23 *
24 * Note that for packed YCbCr 4:2:2 formats there is no way to
25 * control chroma siting. The hardware simply replicates the
26 * chroma samples for both of the luma samples, and thus we don't
27 * actually get the expected MPEG2 chroma siting convention :(
28 * The same behaviour is observed on pre-SKL platforms as well.
29 *
30 * Theory behind the formula (note that we ignore sub-pixel
31 * source coordinates):
32 * s = source sample position
33 * d = destination sample position
34 *
35 * Downscaling 4:1:
36 * -0.5
37 * | 0.0
38 * | | 1.5 (initial phase)
39 * | | |
40 * v v v
41 * | s | s | s | s |
42 * | d |
43 *
44 * Upscaling 1:4:
45 * -0.5
46 * | -0.375 (initial phase)
47 * | | 0.0
48 * | | |
49 * v v v
50 * | s |
51 * | d | d | d | d |
52 */
skl_scaler_calc_phase(int sub,int scale,bool chroma_cosited)53 static u16 skl_scaler_calc_phase(int sub, int scale, bool chroma_cosited)
54 {
55 int phase = -0x8000;
56 u16 trip = 0;
57
58 if (chroma_cosited)
59 phase += (sub - 1) * 0x8000 / sub;
60
61 phase += scale / (2 * sub);
62
63 /*
64 * Hardware initial phase limited to [-0.5:1.5].
65 * Since the max hardware scale factor is 3.0, we
66 * should never actually excdeed 1.0 here.
67 */
68 WARN_ON(phase < -0x8000 || phase > 0x18000);
69
70 if (phase < 0)
71 phase = 0x10000 + phase;
72 else
73 trip = PS_PHASE_TRIP;
74
75 return ((phase >> 2) & PS_PHASE_MASK) | trip;
76 }
77
78 #define SKL_MIN_SRC_W 8
79 #define SKL_MAX_SRC_W 4096
80 #define SKL_MIN_SRC_H 8
81 #define SKL_MAX_SRC_H 4096
82 #define SKL_MIN_DST_W 8
83 #define SKL_MAX_DST_W 4096
84 #define SKL_MIN_DST_H 8
85 #define SKL_MAX_DST_H 4096
86 #define ICL_MAX_SRC_W 5120
87 #define ICL_MAX_SRC_H 4096
88 #define ICL_MAX_DST_W 5120
89 #define ICL_MAX_DST_H 4096
90 #define TGL_MAX_SRC_W 5120
91 #define TGL_MAX_SRC_H 8192
92 #define TGL_MAX_DST_W 8192
93 #define TGL_MAX_DST_H 8192
94 #define MTL_MAX_SRC_W 4096
95 #define MTL_MAX_SRC_H 8192
96 #define MTL_MAX_DST_W 8192
97 #define MTL_MAX_DST_H 8192
98 #define SKL_MIN_YUV_420_SRC_W 16
99 #define SKL_MIN_YUV_420_SRC_H 16
100
101 static int
skl_update_scaler(struct intel_crtc_state * crtc_state,bool force_detach,unsigned int scaler_user,int * scaler_id,int src_w,int src_h,int dst_w,int dst_h,const struct drm_format_info * format,u64 modifier,bool need_scaler)102 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
103 unsigned int scaler_user, int *scaler_id,
104 int src_w, int src_h, int dst_w, int dst_h,
105 const struct drm_format_info *format,
106 u64 modifier, bool need_scaler)
107 {
108 struct intel_crtc_scaler_state *scaler_state =
109 &crtc_state->scaler_state;
110 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
111 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
112 const struct drm_display_mode *adjusted_mode =
113 &crtc_state->hw.adjusted_mode;
114 int pipe_src_w = drm_rect_width(&crtc_state->pipe_src);
115 int pipe_src_h = drm_rect_height(&crtc_state->pipe_src);
116 int min_src_w, min_src_h, min_dst_w, min_dst_h;
117 int max_src_w, max_src_h, max_dst_w, max_dst_h;
118
119 /*
120 * Src coordinates are already rotated by 270 degrees for
121 * the 90/270 degree plane rotation cases (to match the
122 * GTT mapping), hence no need to account for rotation here.
123 */
124 if (src_w != dst_w || src_h != dst_h)
125 need_scaler = true;
126
127 /*
128 * Scaling/fitting not supported in IF-ID mode in GEN9+
129 * TODO: Interlace fetch mode doesn't support YUV420 planar formats.
130 * Once NV12 is enabled, handle it here while allocating scaler
131 * for NV12.
132 */
133 if (DISPLAY_VER(dev_priv) >= 9 && crtc_state->hw.enable &&
134 need_scaler && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
135 drm_dbg_kms(&dev_priv->drm,
136 "Pipe/Plane scaling not supported with IF-ID mode\n");
137 return -EINVAL;
138 }
139
140 /*
141 * if plane is being disabled or scaler is no more required or force detach
142 * - free scaler binded to this plane/crtc
143 * - in order to do this, update crtc->scaler_usage
144 *
145 * Here scaler state in crtc_state is set free so that
146 * scaler can be assigned to other user. Actual register
147 * update to free the scaler is done in plane/panel-fit programming.
148 * For this purpose crtc/plane_state->scaler_id isn't reset here.
149 */
150 if (force_detach || !need_scaler) {
151 if (*scaler_id >= 0) {
152 scaler_state->scaler_users &= ~(1 << scaler_user);
153 scaler_state->scalers[*scaler_id].in_use = 0;
154
155 drm_dbg_kms(&dev_priv->drm,
156 "scaler_user index %u.%u: "
157 "Staged freeing scaler id %d scaler_users = 0x%x\n",
158 crtc->pipe, scaler_user, *scaler_id,
159 scaler_state->scaler_users);
160 *scaler_id = -1;
161 }
162 return 0;
163 }
164
165 if (format && intel_format_info_is_yuv_semiplanar(format, modifier) &&
166 (src_h < SKL_MIN_YUV_420_SRC_H || src_w < SKL_MIN_YUV_420_SRC_W)) {
167 drm_dbg_kms(&dev_priv->drm,
168 "Planar YUV: src dimensions not met\n");
169 return -EINVAL;
170 }
171
172 min_src_w = SKL_MIN_SRC_W;
173 min_src_h = SKL_MIN_SRC_H;
174 min_dst_w = SKL_MIN_DST_W;
175 min_dst_h = SKL_MIN_DST_H;
176
177 if (DISPLAY_VER(dev_priv) < 11) {
178 max_src_w = SKL_MAX_SRC_W;
179 max_src_h = SKL_MAX_SRC_H;
180 max_dst_w = SKL_MAX_DST_W;
181 max_dst_h = SKL_MAX_DST_H;
182 } else if (DISPLAY_VER(dev_priv) < 12) {
183 max_src_w = ICL_MAX_SRC_W;
184 max_src_h = ICL_MAX_SRC_H;
185 max_dst_w = ICL_MAX_DST_W;
186 max_dst_h = ICL_MAX_DST_H;
187 } else if (DISPLAY_VER(dev_priv) < 14) {
188 max_src_w = TGL_MAX_SRC_W;
189 max_src_h = TGL_MAX_SRC_H;
190 max_dst_w = TGL_MAX_DST_W;
191 max_dst_h = TGL_MAX_DST_H;
192 } else {
193 max_src_w = MTL_MAX_SRC_W;
194 max_src_h = MTL_MAX_SRC_H;
195 max_dst_w = MTL_MAX_DST_W;
196 max_dst_h = MTL_MAX_DST_H;
197 }
198
199 /* range checks */
200 if (src_w < min_src_w || src_h < min_src_h ||
201 dst_w < min_dst_w || dst_h < min_dst_h ||
202 src_w > max_src_w || src_h > max_src_h ||
203 dst_w > max_dst_w || dst_h > max_dst_h) {
204 drm_dbg_kms(&dev_priv->drm,
205 "scaler_user index %u.%u: src %ux%u dst %ux%u "
206 "size is out of scaler range\n",
207 crtc->pipe, scaler_user, src_w, src_h,
208 dst_w, dst_h);
209 return -EINVAL;
210 }
211
212 /*
213 * The pipe scaler does not use all the bits of PIPESRC, at least
214 * on the earlier platforms. So even when we're scaling a plane
215 * the *pipe* source size must not be too large. For simplicity
216 * we assume the limits match the scaler destination size limits.
217 * Might not be 100% accurate on all platforms, but good enough for
218 * now.
219 */
220 if (pipe_src_w > max_dst_w || pipe_src_h > max_dst_h) {
221 drm_dbg_kms(&dev_priv->drm,
222 "scaler_user index %u.%u: pipe src size %ux%u "
223 "is out of scaler range\n",
224 crtc->pipe, scaler_user, pipe_src_w, pipe_src_h);
225 return -EINVAL;
226 }
227
228 /* mark this plane as a scaler user in crtc_state */
229 scaler_state->scaler_users |= (1 << scaler_user);
230 drm_dbg_kms(&dev_priv->drm, "scaler_user index %u.%u: "
231 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
232 crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
233 scaler_state->scaler_users);
234
235 return 0;
236 }
237
skl_update_scaler_crtc(struct intel_crtc_state * crtc_state)238 int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state)
239 {
240 const struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode;
241 int width, height;
242
243 if (crtc_state->pch_pfit.enabled) {
244 width = drm_rect_width(&crtc_state->pch_pfit.dst);
245 height = drm_rect_height(&crtc_state->pch_pfit.dst);
246 } else {
247 width = pipe_mode->crtc_hdisplay;
248 height = pipe_mode->crtc_vdisplay;
249 }
250 return skl_update_scaler(crtc_state, !crtc_state->hw.active,
251 SKL_CRTC_INDEX,
252 &crtc_state->scaler_state.scaler_id,
253 drm_rect_width(&crtc_state->pipe_src),
254 drm_rect_height(&crtc_state->pipe_src),
255 width, height, NULL, 0,
256 crtc_state->pch_pfit.enabled);
257 }
258
259 /**
260 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
261 * @crtc_state: crtc's scaler state
262 * @plane_state: atomic plane state to update
263 *
264 * Return
265 * 0 - scaler_usage updated successfully
266 * error - requested scaling cannot be supported or other error condition
267 */
skl_update_scaler_plane(struct intel_crtc_state * crtc_state,struct intel_plane_state * plane_state)268 int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
269 struct intel_plane_state *plane_state)
270 {
271 struct intel_plane *intel_plane =
272 to_intel_plane(plane_state->uapi.plane);
273 struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev);
274 struct drm_framebuffer *fb = plane_state->hw.fb;
275 int ret;
276 bool force_detach = !fb || !plane_state->uapi.visible;
277 bool need_scaler = false;
278
279 /* Pre-gen11 and SDR planes always need a scaler for planar formats. */
280 if (!icl_is_hdr_plane(dev_priv, intel_plane->id) &&
281 fb && intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier))
282 need_scaler = true;
283
284 ret = skl_update_scaler(crtc_state, force_detach,
285 drm_plane_index(&intel_plane->base),
286 &plane_state->scaler_id,
287 drm_rect_width(&plane_state->uapi.src) >> 16,
288 drm_rect_height(&plane_state->uapi.src) >> 16,
289 drm_rect_width(&plane_state->uapi.dst),
290 drm_rect_height(&plane_state->uapi.dst),
291 fb ? fb->format : NULL,
292 fb ? fb->modifier : 0,
293 need_scaler);
294
295 if (ret || plane_state->scaler_id < 0)
296 return ret;
297
298 /* check colorkey */
299 if (plane_state->ckey.flags) {
300 drm_dbg_kms(&dev_priv->drm,
301 "[PLANE:%d:%s] scaling with color key not allowed",
302 intel_plane->base.base.id,
303 intel_plane->base.name);
304 return -EINVAL;
305 }
306
307 /* Check src format */
308 switch (fb->format->format) {
309 case DRM_FORMAT_RGB565:
310 case DRM_FORMAT_XBGR8888:
311 case DRM_FORMAT_XRGB8888:
312 case DRM_FORMAT_ABGR8888:
313 case DRM_FORMAT_ARGB8888:
314 case DRM_FORMAT_XRGB2101010:
315 case DRM_FORMAT_XBGR2101010:
316 case DRM_FORMAT_ARGB2101010:
317 case DRM_FORMAT_ABGR2101010:
318 case DRM_FORMAT_YUYV:
319 case DRM_FORMAT_YVYU:
320 case DRM_FORMAT_UYVY:
321 case DRM_FORMAT_VYUY:
322 case DRM_FORMAT_NV12:
323 case DRM_FORMAT_XYUV8888:
324 case DRM_FORMAT_P010:
325 case DRM_FORMAT_P012:
326 case DRM_FORMAT_P016:
327 case DRM_FORMAT_Y210:
328 case DRM_FORMAT_Y212:
329 case DRM_FORMAT_Y216:
330 case DRM_FORMAT_XVYU2101010:
331 case DRM_FORMAT_XVYU12_16161616:
332 case DRM_FORMAT_XVYU16161616:
333 break;
334 case DRM_FORMAT_XBGR16161616F:
335 case DRM_FORMAT_ABGR16161616F:
336 case DRM_FORMAT_XRGB16161616F:
337 case DRM_FORMAT_ARGB16161616F:
338 if (DISPLAY_VER(dev_priv) >= 11)
339 break;
340 fallthrough;
341 default:
342 drm_dbg_kms(&dev_priv->drm,
343 "[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
344 intel_plane->base.base.id, intel_plane->base.name,
345 fb->base.id, fb->format->format);
346 return -EINVAL;
347 }
348
349 return 0;
350 }
351
intel_atomic_setup_scaler(struct intel_crtc_scaler_state * scaler_state,int num_scalers_need,struct intel_crtc * intel_crtc,const char * name,int idx,struct intel_plane_state * plane_state,int * scaler_id)352 static int intel_atomic_setup_scaler(struct intel_crtc_scaler_state *scaler_state,
353 int num_scalers_need, struct intel_crtc *intel_crtc,
354 const char *name, int idx,
355 struct intel_plane_state *plane_state,
356 int *scaler_id)
357 {
358 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
359 int j;
360 u32 mode;
361
362 if (*scaler_id < 0) {
363 /* find a free scaler */
364 for (j = 0; j < intel_crtc->num_scalers; j++) {
365 if (scaler_state->scalers[j].in_use)
366 continue;
367
368 *scaler_id = j;
369 scaler_state->scalers[*scaler_id].in_use = 1;
370 break;
371 }
372 }
373
374 if (drm_WARN(&dev_priv->drm, *scaler_id < 0,
375 "Cannot find scaler for %s:%d\n", name, idx))
376 return -EINVAL;
377
378 /* set scaler mode */
379 if (plane_state && plane_state->hw.fb &&
380 plane_state->hw.fb->format->is_yuv &&
381 plane_state->hw.fb->format->num_planes > 1) {
382 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
383
384 if (DISPLAY_VER(dev_priv) == 9) {
385 mode = SKL_PS_SCALER_MODE_NV12;
386 } else if (icl_is_hdr_plane(dev_priv, plane->id)) {
387 /*
388 * On gen11+'s HDR planes we only use the scaler for
389 * scaling. They have a dedicated chroma upsampler, so
390 * we don't need the scaler to upsample the UV plane.
391 */
392 mode = PS_SCALER_MODE_NORMAL;
393 } else {
394 struct intel_plane *linked =
395 plane_state->planar_linked_plane;
396
397 mode = PS_SCALER_MODE_PLANAR;
398
399 if (linked)
400 mode |= PS_BINDING_Y_PLANE(linked->id);
401 }
402 } else if (DISPLAY_VER(dev_priv) >= 10) {
403 mode = PS_SCALER_MODE_NORMAL;
404 } else if (num_scalers_need == 1 && intel_crtc->num_scalers > 1) {
405 /*
406 * when only 1 scaler is in use on a pipe with 2 scalers
407 * scaler 0 operates in high quality (HQ) mode.
408 * In this case use scaler 0 to take advantage of HQ mode
409 */
410 scaler_state->scalers[*scaler_id].in_use = 0;
411 *scaler_id = 0;
412 scaler_state->scalers[0].in_use = 1;
413 mode = SKL_PS_SCALER_MODE_HQ;
414 } else {
415 mode = SKL_PS_SCALER_MODE_DYN;
416 }
417
418 /*
419 * FIXME: we should also check the scaler factors for pfit, so
420 * this shouldn't be tied directly to planes.
421 */
422 if (plane_state && plane_state->hw.fb) {
423 const struct drm_framebuffer *fb = plane_state->hw.fb;
424 const struct drm_rect *src = &plane_state->uapi.src;
425 const struct drm_rect *dst = &plane_state->uapi.dst;
426 int hscale, vscale, max_vscale, max_hscale;
427
428 /*
429 * FIXME: When two scalers are needed, but only one of
430 * them needs to downscale, we should make sure that
431 * the one that needs downscaling support is assigned
432 * as the first scaler, so we don't reject downscaling
433 * unnecessarily.
434 */
435
436 if (DISPLAY_VER(dev_priv) >= 14) {
437 /*
438 * On versions 14 and up, only the first
439 * scaler supports a vertical scaling factor
440 * of more than 1.0, while a horizontal
441 * scaling factor of 3.0 is supported.
442 */
443 max_hscale = 0x30000 - 1;
444 if (*scaler_id == 0)
445 max_vscale = 0x30000 - 1;
446 else
447 max_vscale = 0x10000;
448
449 } else if (DISPLAY_VER(dev_priv) >= 10 ||
450 !intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier)) {
451 max_hscale = 0x30000 - 1;
452 max_vscale = 0x30000 - 1;
453 } else {
454 max_hscale = 0x20000 - 1;
455 max_vscale = 0x20000 - 1;
456 }
457
458 /*
459 * FIXME: We should change the if-else block above to
460 * support HQ vs dynamic scaler properly.
461 */
462
463 /* Check if required scaling is within limits */
464 hscale = drm_rect_calc_hscale(src, dst, 1, max_hscale);
465 vscale = drm_rect_calc_vscale(src, dst, 1, max_vscale);
466
467 if (hscale < 0 || vscale < 0) {
468 drm_dbg_kms(&dev_priv->drm,
469 "Scaler %d doesn't support required plane scaling\n",
470 *scaler_id);
471 drm_rect_debug_print("src: ", src, true);
472 drm_rect_debug_print("dst: ", dst, false);
473
474 return -EINVAL;
475 }
476 }
477
478 drm_dbg_kms(&dev_priv->drm, "Attached scaler id %u.%u to %s:%d\n",
479 intel_crtc->pipe, *scaler_id, name, idx);
480 scaler_state->scalers[*scaler_id].mode = mode;
481
482 return 0;
483 }
484
485 /**
486 * intel_atomic_setup_scalers() - setup scalers for crtc per staged requests
487 * @dev_priv: i915 device
488 * @intel_crtc: intel crtc
489 * @crtc_state: incoming crtc_state to validate and setup scalers
490 *
491 * This function sets up scalers based on staged scaling requests for
492 * a @crtc and its planes. It is called from crtc level check path. If request
493 * is a supportable request, it attaches scalers to requested planes and crtc.
494 *
495 * This function takes into account the current scaler(s) in use by any planes
496 * not being part of this atomic state
497 *
498 * Returns:
499 * 0 - scalers were setup successfully
500 * error code - otherwise
501 */
intel_atomic_setup_scalers(struct drm_i915_private * dev_priv,struct intel_crtc * intel_crtc,struct intel_crtc_state * crtc_state)502 int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
503 struct intel_crtc *intel_crtc,
504 struct intel_crtc_state *crtc_state)
505 {
506 struct drm_plane *plane = NULL;
507 struct intel_plane *intel_plane;
508 struct intel_crtc_scaler_state *scaler_state =
509 &crtc_state->scaler_state;
510 struct drm_atomic_state *drm_state = crtc_state->uapi.state;
511 struct intel_atomic_state *intel_state = to_intel_atomic_state(drm_state);
512 int num_scalers_need;
513 int i;
514
515 num_scalers_need = hweight32(scaler_state->scaler_users);
516
517 /*
518 * High level flow:
519 * - staged scaler requests are already in scaler_state->scaler_users
520 * - check whether staged scaling requests can be supported
521 * - add planes using scalers that aren't in current transaction
522 * - assign scalers to requested users
523 * - as part of plane commit, scalers will be committed
524 * (i.e., either attached or detached) to respective planes in hw
525 * - as part of crtc_commit, scaler will be either attached or detached
526 * to crtc in hw
527 */
528
529 /* fail if required scalers > available scalers */
530 if (num_scalers_need > intel_crtc->num_scalers) {
531 drm_dbg_kms(&dev_priv->drm,
532 "Too many scaling requests %d > %d\n",
533 num_scalers_need, intel_crtc->num_scalers);
534 return -EINVAL;
535 }
536
537 /* walkthrough scaler_users bits and start assigning scalers */
538 for (i = 0; i < sizeof(scaler_state->scaler_users) * 8; i++) {
539 struct intel_plane_state *plane_state = NULL;
540 int *scaler_id;
541 const char *name;
542 int idx, ret;
543
544 /* skip if scaler not required */
545 if (!(scaler_state->scaler_users & (1 << i)))
546 continue;
547
548 if (i == SKL_CRTC_INDEX) {
549 name = "CRTC";
550 idx = intel_crtc->base.base.id;
551
552 /* panel fitter case: assign as a crtc scaler */
553 scaler_id = &scaler_state->scaler_id;
554 } else {
555 name = "PLANE";
556
557 /* plane scaler case: assign as a plane scaler */
558 /* find the plane that set the bit as scaler_user */
559 plane = drm_state->planes[i].ptr;
560
561 /*
562 * to enable/disable hq mode, add planes that are using scaler
563 * into this transaction
564 */
565 if (!plane) {
566 struct drm_plane_state *state;
567
568 /*
569 * GLK+ scalers don't have a HQ mode so it
570 * isn't necessary to change between HQ and dyn mode
571 * on those platforms.
572 */
573 if (DISPLAY_VER(dev_priv) >= 10)
574 continue;
575
576 plane = drm_plane_from_index(&dev_priv->drm, i);
577 state = drm_atomic_get_plane_state(drm_state, plane);
578 if (IS_ERR(state)) {
579 drm_dbg_kms(&dev_priv->drm,
580 "Failed to add [PLANE:%d] to drm_state\n",
581 plane->base.id);
582 return PTR_ERR(state);
583 }
584 }
585
586 intel_plane = to_intel_plane(plane);
587 idx = plane->base.id;
588
589 /* plane on different crtc cannot be a scaler user of this crtc */
590 if (drm_WARN_ON(&dev_priv->drm,
591 intel_plane->pipe != intel_crtc->pipe))
592 continue;
593
594 plane_state = intel_atomic_get_new_plane_state(intel_state,
595 intel_plane);
596 scaler_id = &plane_state->scaler_id;
597 }
598
599 ret = intel_atomic_setup_scaler(scaler_state, num_scalers_need,
600 intel_crtc, name, idx,
601 plane_state, scaler_id);
602 if (ret < 0)
603 return ret;
604 }
605
606 return 0;
607 }
608
glk_coef_tap(int i)609 static int glk_coef_tap(int i)
610 {
611 return i % 7;
612 }
613
glk_nearest_filter_coef(int t)614 static u16 glk_nearest_filter_coef(int t)
615 {
616 return t == 3 ? 0x0800 : 0x3000;
617 }
618
619 /*
620 * Theory behind setting nearest-neighbor integer scaling:
621 *
622 * 17 phase of 7 taps requires 119 coefficients in 60 dwords per set.
623 * The letter represents the filter tap (D is the center tap) and the number
624 * represents the coefficient set for a phase (0-16).
625 *
626 * +------------+------------------------+------------------------+
627 * |Index value | Data value coeffient 1 | Data value coeffient 2 |
628 * +------------+------------------------+------------------------+
629 * | 00h | B0 | A0 |
630 * +------------+------------------------+------------------------+
631 * | 01h | D0 | C0 |
632 * +------------+------------------------+------------------------+
633 * | 02h | F0 | E0 |
634 * +------------+------------------------+------------------------+
635 * | 03h | A1 | G0 |
636 * +------------+------------------------+------------------------+
637 * | 04h | C1 | B1 |
638 * +------------+------------------------+------------------------+
639 * | ... | ... | ... |
640 * +------------+------------------------+------------------------+
641 * | 38h | B16 | A16 |
642 * +------------+------------------------+------------------------+
643 * | 39h | D16 | C16 |
644 * +------------+------------------------+------------------------+
645 * | 3Ah | F16 | C16 |
646 * +------------+------------------------+------------------------+
647 * | 3Bh | Reserved | G16 |
648 * +------------+------------------------+------------------------+
649 *
650 * To enable nearest-neighbor scaling: program scaler coefficents with
651 * the center tap (Dxx) values set to 1 and all other values set to 0 as per
652 * SCALER_COEFFICIENT_FORMAT
653 *
654 */
655
glk_program_nearest_filter_coefs(struct drm_i915_private * dev_priv,enum pipe pipe,int id,int set)656 static void glk_program_nearest_filter_coefs(struct drm_i915_private *dev_priv,
657 enum pipe pipe, int id, int set)
658 {
659 int i;
660
661 intel_de_write_fw(dev_priv, GLK_PS_COEF_INDEX_SET(pipe, id, set),
662 PS_COEF_INDEX_AUTO_INC);
663
664 for (i = 0; i < 17 * 7; i += 2) {
665 u32 tmp;
666 int t;
667
668 t = glk_coef_tap(i);
669 tmp = glk_nearest_filter_coef(t);
670
671 t = glk_coef_tap(i + 1);
672 tmp |= glk_nearest_filter_coef(t) << 16;
673
674 intel_de_write_fw(dev_priv, GLK_PS_COEF_DATA_SET(pipe, id, set),
675 tmp);
676 }
677
678 intel_de_write_fw(dev_priv, GLK_PS_COEF_INDEX_SET(pipe, id, set), 0);
679 }
680
skl_scaler_get_filter_select(enum drm_scaling_filter filter,int set)681 static u32 skl_scaler_get_filter_select(enum drm_scaling_filter filter, int set)
682 {
683 if (filter == DRM_SCALING_FILTER_NEAREST_NEIGHBOR) {
684 return (PS_FILTER_PROGRAMMED |
685 PS_Y_VERT_FILTER_SELECT(set) |
686 PS_Y_HORZ_FILTER_SELECT(set) |
687 PS_UV_VERT_FILTER_SELECT(set) |
688 PS_UV_HORZ_FILTER_SELECT(set));
689 }
690
691 return PS_FILTER_MEDIUM;
692 }
693
skl_scaler_setup_filter(struct drm_i915_private * dev_priv,enum pipe pipe,int id,int set,enum drm_scaling_filter filter)694 static void skl_scaler_setup_filter(struct drm_i915_private *dev_priv, enum pipe pipe,
695 int id, int set, enum drm_scaling_filter filter)
696 {
697 switch (filter) {
698 case DRM_SCALING_FILTER_DEFAULT:
699 break;
700 case DRM_SCALING_FILTER_NEAREST_NEIGHBOR:
701 glk_program_nearest_filter_coefs(dev_priv, pipe, id, set);
702 break;
703 default:
704 MISSING_CASE(filter);
705 }
706 }
707
skl_pfit_enable(const struct intel_crtc_state * crtc_state)708 void skl_pfit_enable(const struct intel_crtc_state *crtc_state)
709 {
710 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
711 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
712 const struct intel_crtc_scaler_state *scaler_state =
713 &crtc_state->scaler_state;
714 const struct drm_rect *dst = &crtc_state->pch_pfit.dst;
715 u16 uv_rgb_hphase, uv_rgb_vphase;
716 enum pipe pipe = crtc->pipe;
717 int width = drm_rect_width(dst);
718 int height = drm_rect_height(dst);
719 int x = dst->x1;
720 int y = dst->y1;
721 int hscale, vscale;
722 struct drm_rect src;
723 int id;
724 u32 ps_ctrl;
725
726 if (!crtc_state->pch_pfit.enabled)
727 return;
728
729 if (drm_WARN_ON(&dev_priv->drm,
730 crtc_state->scaler_state.scaler_id < 0))
731 return;
732
733 drm_rect_init(&src, 0, 0,
734 drm_rect_width(&crtc_state->pipe_src) << 16,
735 drm_rect_height(&crtc_state->pipe_src) << 16);
736
737 hscale = drm_rect_calc_hscale(&src, dst, 0, INT_MAX);
738 vscale = drm_rect_calc_vscale(&src, dst, 0, INT_MAX);
739
740 uv_rgb_hphase = skl_scaler_calc_phase(1, hscale, false);
741 uv_rgb_vphase = skl_scaler_calc_phase(1, vscale, false);
742
743 id = scaler_state->scaler_id;
744
745 ps_ctrl = PS_SCALER_EN | PS_BINDING_PIPE | scaler_state->scalers[id].mode |
746 skl_scaler_get_filter_select(crtc_state->hw.scaling_filter, 0);
747
748 skl_scaler_setup_filter(dev_priv, pipe, id, 0,
749 crtc_state->hw.scaling_filter);
750
751 intel_de_write_fw(dev_priv, SKL_PS_CTRL(pipe, id), ps_ctrl);
752
753 intel_de_write_fw(dev_priv, SKL_PS_VPHASE(pipe, id),
754 PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_vphase));
755 intel_de_write_fw(dev_priv, SKL_PS_HPHASE(pipe, id),
756 PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_hphase));
757 intel_de_write_fw(dev_priv, SKL_PS_WIN_POS(pipe, id),
758 PS_WIN_XPOS(x) | PS_WIN_YPOS(y));
759 intel_de_write_fw(dev_priv, SKL_PS_WIN_SZ(pipe, id),
760 PS_WIN_XSIZE(width) | PS_WIN_YSIZE(height));
761 }
762
763 void
skl_program_plane_scaler(struct intel_plane * plane,const struct intel_crtc_state * crtc_state,const struct intel_plane_state * plane_state)764 skl_program_plane_scaler(struct intel_plane *plane,
765 const struct intel_crtc_state *crtc_state,
766 const struct intel_plane_state *plane_state)
767 {
768 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
769 const struct drm_framebuffer *fb = plane_state->hw.fb;
770 enum pipe pipe = plane->pipe;
771 int scaler_id = plane_state->scaler_id;
772 const struct intel_scaler *scaler =
773 &crtc_state->scaler_state.scalers[scaler_id];
774 int crtc_x = plane_state->uapi.dst.x1;
775 int crtc_y = plane_state->uapi.dst.y1;
776 u32 crtc_w = drm_rect_width(&plane_state->uapi.dst);
777 u32 crtc_h = drm_rect_height(&plane_state->uapi.dst);
778 u16 y_hphase, uv_rgb_hphase;
779 u16 y_vphase, uv_rgb_vphase;
780 int hscale, vscale;
781 u32 ps_ctrl;
782
783 hscale = drm_rect_calc_hscale(&plane_state->uapi.src,
784 &plane_state->uapi.dst,
785 0, INT_MAX);
786 vscale = drm_rect_calc_vscale(&plane_state->uapi.src,
787 &plane_state->uapi.dst,
788 0, INT_MAX);
789
790 /* TODO: handle sub-pixel coordinates */
791 if (intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier) &&
792 !icl_is_hdr_plane(dev_priv, plane->id)) {
793 y_hphase = skl_scaler_calc_phase(1, hscale, false);
794 y_vphase = skl_scaler_calc_phase(1, vscale, false);
795
796 /* MPEG2 chroma siting convention */
797 uv_rgb_hphase = skl_scaler_calc_phase(2, hscale, true);
798 uv_rgb_vphase = skl_scaler_calc_phase(2, vscale, false);
799 } else {
800 /* not used */
801 y_hphase = 0;
802 y_vphase = 0;
803
804 uv_rgb_hphase = skl_scaler_calc_phase(1, hscale, false);
805 uv_rgb_vphase = skl_scaler_calc_phase(1, vscale, false);
806 }
807
808 ps_ctrl = PS_SCALER_EN | PS_BINDING_PLANE(plane->id) | scaler->mode |
809 skl_scaler_get_filter_select(plane_state->hw.scaling_filter, 0);
810
811 skl_scaler_setup_filter(dev_priv, pipe, scaler_id, 0,
812 plane_state->hw.scaling_filter);
813
814 intel_de_write_fw(dev_priv, SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
815 intel_de_write_fw(dev_priv, SKL_PS_VPHASE(pipe, scaler_id),
816 PS_Y_PHASE(y_vphase) | PS_UV_RGB_PHASE(uv_rgb_vphase));
817 intel_de_write_fw(dev_priv, SKL_PS_HPHASE(pipe, scaler_id),
818 PS_Y_PHASE(y_hphase) | PS_UV_RGB_PHASE(uv_rgb_hphase));
819 intel_de_write_fw(dev_priv, SKL_PS_WIN_POS(pipe, scaler_id),
820 PS_WIN_XPOS(crtc_x) | PS_WIN_YPOS(crtc_y));
821 intel_de_write_fw(dev_priv, SKL_PS_WIN_SZ(pipe, scaler_id),
822 PS_WIN_XSIZE(crtc_w) | PS_WIN_YSIZE(crtc_h));
823 }
824
skl_detach_scaler(struct intel_crtc * crtc,int id)825 static void skl_detach_scaler(struct intel_crtc *crtc, int id)
826 {
827 struct drm_device *dev = crtc->base.dev;
828 struct drm_i915_private *dev_priv = to_i915(dev);
829
830 intel_de_write_fw(dev_priv, SKL_PS_CTRL(crtc->pipe, id), 0);
831 intel_de_write_fw(dev_priv, SKL_PS_WIN_POS(crtc->pipe, id), 0);
832 intel_de_write_fw(dev_priv, SKL_PS_WIN_SZ(crtc->pipe, id), 0);
833 }
834
835 /*
836 * This function detaches (aka. unbinds) unused scalers in hardware
837 */
skl_detach_scalers(const struct intel_crtc_state * crtc_state)838 void skl_detach_scalers(const struct intel_crtc_state *crtc_state)
839 {
840 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
841 const struct intel_crtc_scaler_state *scaler_state =
842 &crtc_state->scaler_state;
843 int i;
844
845 /* loop through and disable scalers that aren't in use */
846 for (i = 0; i < crtc->num_scalers; i++) {
847 if (!scaler_state->scalers[i].in_use)
848 skl_detach_scaler(crtc, i);
849 }
850 }
851
skl_scaler_disable(const struct intel_crtc_state * old_crtc_state)852 void skl_scaler_disable(const struct intel_crtc_state *old_crtc_state)
853 {
854 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
855 int i;
856
857 for (i = 0; i < crtc->num_scalers; i++)
858 skl_detach_scaler(crtc, i);
859 }
860
skl_scaler_get_config(struct intel_crtc_state * crtc_state)861 void skl_scaler_get_config(struct intel_crtc_state *crtc_state)
862 {
863 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
864 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
865 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
866 int id = -1;
867 int i;
868
869 /* find scaler attached to this pipe */
870 for (i = 0; i < crtc->num_scalers; i++) {
871 u32 ctl, pos, size;
872
873 ctl = intel_de_read(dev_priv, SKL_PS_CTRL(crtc->pipe, i));
874 if ((ctl & (PS_SCALER_EN | PS_BINDING_MASK)) != (PS_SCALER_EN | PS_BINDING_PIPE))
875 continue;
876
877 id = i;
878 crtc_state->pch_pfit.enabled = true;
879
880 pos = intel_de_read(dev_priv, SKL_PS_WIN_POS(crtc->pipe, i));
881 size = intel_de_read(dev_priv, SKL_PS_WIN_SZ(crtc->pipe, i));
882
883 drm_rect_init(&crtc_state->pch_pfit.dst,
884 REG_FIELD_GET(PS_WIN_XPOS_MASK, pos),
885 REG_FIELD_GET(PS_WIN_YPOS_MASK, pos),
886 REG_FIELD_GET(PS_WIN_XSIZE_MASK, size),
887 REG_FIELD_GET(PS_WIN_YSIZE_MASK, size));
888
889 scaler_state->scalers[i].in_use = true;
890 break;
891 }
892
893 scaler_state->scaler_id = id;
894 if (id >= 0)
895 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
896 else
897 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
898 }
899