1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (C) 2012-2019 ARM Limited (or its affiliates). */ 3 4 #ifndef __CC_HW_QUEUE_DEFS_H__ 5 #define __CC_HW_QUEUE_DEFS_H__ 6 7 #include <linux/types.h> 8 9 #include "cc_kernel_regs.h" 10 #include <linux/bitfield.h> 11 12 /****************************************************************************** 13 * DEFINITIONS 14 ******************************************************************************/ 15 16 #define HW_DESC_SIZE_WORDS 6 17 /* Define max. available slots in HW queue */ 18 #define HW_QUEUE_SLOTS_MAX 15 19 20 #define CC_REG_LOW(name) (name ## _BIT_SHIFT) 21 #define CC_REG_HIGH(name) (CC_REG_LOW(name) + name ## _BIT_SIZE - 1) 22 #define CC_GENMASK(name) GENMASK(CC_REG_HIGH(name), CC_REG_LOW(name)) 23 24 #define CC_HWQ_GENMASK(word, field) \ 25 CC_GENMASK(CC_DSCRPTR_QUEUE_WORD ## word ## _ ## field) 26 27 #define WORD0_VALUE CC_HWQ_GENMASK(0, VALUE) 28 #define WORD0_CPP_CIPHER_MODE CC_HWQ_GENMASK(0, CPP_CIPHER_MODE) 29 #define WORD1_DIN_CONST_VALUE CC_HWQ_GENMASK(1, DIN_CONST_VALUE) 30 #define WORD1_DIN_DMA_MODE CC_HWQ_GENMASK(1, DIN_DMA_MODE) 31 #define WORD1_DIN_SIZE CC_HWQ_GENMASK(1, DIN_SIZE) 32 #define WORD1_NOT_LAST CC_HWQ_GENMASK(1, NOT_LAST) 33 #define WORD1_NS_BIT CC_HWQ_GENMASK(1, NS_BIT) 34 #define WORD1_LOCK_QUEUE CC_HWQ_GENMASK(1, LOCK_QUEUE) 35 #define WORD2_VALUE CC_HWQ_GENMASK(2, VALUE) 36 #define WORD3_DOUT_DMA_MODE CC_HWQ_GENMASK(3, DOUT_DMA_MODE) 37 #define WORD3_DOUT_LAST_IND CC_HWQ_GENMASK(3, DOUT_LAST_IND) 38 #define WORD3_DOUT_SIZE CC_HWQ_GENMASK(3, DOUT_SIZE) 39 #define WORD3_HASH_XOR_BIT CC_HWQ_GENMASK(3, HASH_XOR_BIT) 40 #define WORD3_NS_BIT CC_HWQ_GENMASK(3, NS_BIT) 41 #define WORD3_QUEUE_LAST_IND CC_HWQ_GENMASK(3, QUEUE_LAST_IND) 42 #define WORD4_ACK_NEEDED CC_HWQ_GENMASK(4, ACK_NEEDED) 43 #define WORD4_AES_SEL_N_HASH CC_HWQ_GENMASK(4, AES_SEL_N_HASH) 44 #define WORD4_AES_XOR_CRYPTO_KEY CC_HWQ_GENMASK(4, AES_XOR_CRYPTO_KEY) 45 #define WORD4_BYTES_SWAP CC_HWQ_GENMASK(4, BYTES_SWAP) 46 #define WORD4_CIPHER_CONF0 CC_HWQ_GENMASK(4, CIPHER_CONF0) 47 #define WORD4_CIPHER_CONF1 CC_HWQ_GENMASK(4, CIPHER_CONF1) 48 #define WORD4_CIPHER_CONF2 CC_HWQ_GENMASK(4, CIPHER_CONF2) 49 #define WORD4_CIPHER_DO CC_HWQ_GENMASK(4, CIPHER_DO) 50 #define WORD4_CIPHER_MODE CC_HWQ_GENMASK(4, CIPHER_MODE) 51 #define WORD4_CMAC_SIZE0 CC_HWQ_GENMASK(4, CMAC_SIZE0) 52 #define WORD4_DATA_FLOW_MODE CC_HWQ_GENMASK(4, DATA_FLOW_MODE) 53 #define WORD4_KEY_SIZE CC_HWQ_GENMASK(4, KEY_SIZE) 54 #define WORD4_SETUP_OPERATION CC_HWQ_GENMASK(4, SETUP_OPERATION) 55 #define WORD5_DIN_ADDR_HIGH CC_HWQ_GENMASK(5, DIN_ADDR_HIGH) 56 #define WORD5_DOUT_ADDR_HIGH CC_HWQ_GENMASK(5, DOUT_ADDR_HIGH) 57 58 /****************************************************************************** 59 * TYPE DEFINITIONS 60 ******************************************************************************/ 61 62 struct cc_hw_desc { 63 union { 64 u32 word[HW_DESC_SIZE_WORDS]; 65 u16 hword[HW_DESC_SIZE_WORDS * 2]; 66 }; 67 }; 68 69 enum cc_axi_sec { 70 AXI_SECURE = 0, 71 AXI_NOT_SECURE = 1 72 }; 73 74 enum cc_desc_direction { 75 DESC_DIRECTION_ILLEGAL = -1, 76 DESC_DIRECTION_ENCRYPT_ENCRYPT = 0, 77 DESC_DIRECTION_DECRYPT_DECRYPT = 1, 78 DESC_DIRECTION_DECRYPT_ENCRYPT = 3, 79 DESC_DIRECTION_END = S32_MAX, 80 }; 81 82 enum cc_dma_mode { 83 DMA_MODE_NULL = -1, 84 NO_DMA = 0, 85 DMA_SRAM = 1, 86 DMA_DLLI = 2, 87 DMA_MLLI = 3, 88 DMA_MODE_END = S32_MAX, 89 }; 90 91 enum cc_flow_mode { 92 FLOW_MODE_NULL = -1, 93 /* data flows */ 94 BYPASS = 0, 95 DIN_AES_DOUT = 1, 96 AES_to_HASH = 2, 97 AES_and_HASH = 3, 98 DIN_DES_DOUT = 4, 99 DES_to_HASH = 5, 100 DES_and_HASH = 6, 101 DIN_HASH = 7, 102 DIN_HASH_and_BYPASS = 8, 103 AESMAC_and_BYPASS = 9, 104 AES_to_HASH_and_DOUT = 10, 105 DIN_RC4_DOUT = 11, 106 DES_to_HASH_and_DOUT = 12, 107 AES_to_AES_to_HASH_and_DOUT = 13, 108 AES_to_AES_to_HASH = 14, 109 AES_to_HASH_and_AES = 15, 110 DIN_SM4_DOUT = 16, 111 DIN_AES_AESMAC = 17, 112 HASH_to_DOUT = 18, 113 /* setup flows */ 114 S_DIN_to_AES = 32, 115 S_DIN_to_AES2 = 33, 116 S_DIN_to_DES = 34, 117 S_DIN_to_RC4 = 35, 118 S_DIN_to_SM4 = 36, 119 S_DIN_to_HASH = 37, 120 S_AES_to_DOUT = 38, 121 S_AES2_to_DOUT = 39, 122 S_SM4_to_DOUT = 40, 123 S_RC4_to_DOUT = 41, 124 S_DES_to_DOUT = 42, 125 S_HASH_to_DOUT = 43, 126 SET_FLOW_ID = 44, 127 FLOW_MODE_END = S32_MAX, 128 }; 129 130 enum cc_setup_op { 131 SETUP_LOAD_NOP = 0, 132 SETUP_LOAD_STATE0 = 1, 133 SETUP_LOAD_STATE1 = 2, 134 SETUP_LOAD_STATE2 = 3, 135 SETUP_LOAD_KEY0 = 4, 136 SETUP_LOAD_XEX_KEY = 5, 137 SETUP_WRITE_STATE0 = 8, 138 SETUP_WRITE_STATE1 = 9, 139 SETUP_WRITE_STATE2 = 10, 140 SETUP_WRITE_STATE3 = 11, 141 SETUP_OP_END = S32_MAX, 142 }; 143 144 enum cc_hash_conf_pad { 145 HASH_PADDING_DISABLED = 0, 146 HASH_PADDING_ENABLED = 1, 147 HASH_DIGEST_RESULT_LITTLE_ENDIAN = 2, 148 HASH_CONFIG1_PADDING_RESERVE32 = S32_MAX, 149 }; 150 151 enum cc_aes_mac_selector { 152 AES_SK = 1, 153 AES_CMAC_INIT = 2, 154 AES_CMAC_SIZE0 = 3, 155 AES_MAC_END = S32_MAX, 156 }; 157 158 #define HW_KEY_MASK_CIPHER_DO 0x3 159 #define HW_KEY_SHIFT_CIPHER_CFG2 2 160 161 /* HwCryptoKey[1:0] is mapped to cipher_do[1:0] */ 162 /* HwCryptoKey[2:3] is mapped to cipher_config2[1:0] */ 163 enum cc_hw_crypto_key { 164 USER_KEY = 0, /* 0x0000 */ 165 ROOT_KEY = 1, /* 0x0001 */ 166 PROVISIONING_KEY = 2, /* 0x0010 */ /* ==KCP */ 167 SESSION_KEY = 3, /* 0x0011 */ 168 RESERVED_KEY = 4, /* NA */ 169 PLATFORM_KEY = 5, /* 0x0101 */ 170 CUSTOMER_KEY = 6, /* 0x0110 */ 171 KFDE0_KEY = 7, /* 0x0111 */ 172 KFDE1_KEY = 9, /* 0x1001 */ 173 KFDE2_KEY = 10, /* 0x1010 */ 174 KFDE3_KEY = 11, /* 0x1011 */ 175 END_OF_KEYS = S32_MAX, 176 }; 177 178 #define CC_NUM_HW_KEY_SLOTS 4 179 #define CC_FIRST_HW_KEY_SLOT 0 180 #define CC_LAST_HW_KEY_SLOT (CC_FIRST_HW_KEY_SLOT + CC_NUM_HW_KEY_SLOTS - 1) 181 182 #define CC_NUM_CPP_KEY_SLOTS 8 183 #define CC_FIRST_CPP_KEY_SLOT 16 184 #define CC_LAST_CPP_KEY_SLOT (CC_FIRST_CPP_KEY_SLOT + \ 185 CC_NUM_CPP_KEY_SLOTS - 1) 186 187 enum cc_hw_aes_key_size { 188 AES_128_KEY = 0, 189 AES_192_KEY = 1, 190 AES_256_KEY = 2, 191 END_OF_AES_KEYS = S32_MAX, 192 }; 193 194 enum cc_hash_cipher_pad { 195 DO_NOT_PAD = 0, 196 DO_PAD = 1, 197 HASH_CIPHER_DO_PADDING_RESERVE32 = S32_MAX, 198 }; 199 200 #define CC_CPP_DIN_ADDR 0xFF00FF00UL 201 #define CC_CPP_DIN_SIZE 0xFF00FFUL 202 203 /*****************************/ 204 /* Descriptor packing macros */ 205 /*****************************/ 206 207 /** 208 * hw_desc_init() - Init a HW descriptor struct 209 * @pdesc: pointer to HW descriptor struct 210 */ hw_desc_init(struct cc_hw_desc * pdesc)211 static inline void hw_desc_init(struct cc_hw_desc *pdesc) 212 { 213 memset(pdesc, 0, sizeof(struct cc_hw_desc)); 214 } 215 216 /** 217 * set_queue_last_ind_bit() - Indicate the end of current HW descriptors flow 218 * and release the HW engines. 219 * 220 * @pdesc: Pointer to HW descriptor struct 221 */ set_queue_last_ind_bit(struct cc_hw_desc * pdesc)222 static inline void set_queue_last_ind_bit(struct cc_hw_desc *pdesc) 223 { 224 pdesc->word[3] |= FIELD_PREP(WORD3_QUEUE_LAST_IND, 1); 225 } 226 227 /** 228 * set_din_type() - Set the DIN field of a HW descriptor 229 * 230 * @pdesc: Pointer to HW descriptor struct 231 * @dma_mode: The DMA mode: NO_DMA, SRAM, DLLI, MLLI, CONSTANT 232 * @addr: DIN address 233 * @size: Data size in bytes 234 * @axi_sec: AXI secure bit 235 */ set_din_type(struct cc_hw_desc * pdesc,enum cc_dma_mode dma_mode,dma_addr_t addr,u32 size,enum cc_axi_sec axi_sec)236 static inline void set_din_type(struct cc_hw_desc *pdesc, 237 enum cc_dma_mode dma_mode, dma_addr_t addr, 238 u32 size, enum cc_axi_sec axi_sec) 239 { 240 pdesc->word[0] = lower_32_bits(addr); 241 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT 242 pdesc->word[5] |= FIELD_PREP(WORD5_DIN_ADDR_HIGH, upper_32_bits(addr)); 243 #endif 244 pdesc->word[1] |= FIELD_PREP(WORD1_DIN_DMA_MODE, dma_mode) | 245 FIELD_PREP(WORD1_DIN_SIZE, size) | 246 FIELD_PREP(WORD1_NS_BIT, axi_sec); 247 } 248 249 /** 250 * set_din_no_dma() - Set the DIN field of a HW descriptor to NO DMA mode. 251 * Used for NOP descriptor, register patches and other special modes. 252 * 253 * @pdesc: Pointer to HW descriptor struct 254 * @addr: DIN address 255 * @size: Data size in bytes 256 */ set_din_no_dma(struct cc_hw_desc * pdesc,u32 addr,u32 size)257 static inline void set_din_no_dma(struct cc_hw_desc *pdesc, u32 addr, u32 size) 258 { 259 pdesc->word[0] = addr; 260 pdesc->word[1] |= FIELD_PREP(WORD1_DIN_SIZE, size); 261 } 262 263 /** 264 * set_cpp_crypto_key() - Setup the special CPP descriptor 265 * 266 * @pdesc: Pointer to HW descriptor struct 267 * @slot: Slot number 268 */ set_cpp_crypto_key(struct cc_hw_desc * pdesc,u8 slot)269 static inline void set_cpp_crypto_key(struct cc_hw_desc *pdesc, u8 slot) 270 { 271 pdesc->word[0] |= CC_CPP_DIN_ADDR; 272 273 pdesc->word[1] |= FIELD_PREP(WORD1_DIN_SIZE, CC_CPP_DIN_SIZE); 274 pdesc->word[1] |= FIELD_PREP(WORD1_LOCK_QUEUE, 1); 275 276 pdesc->word[4] |= FIELD_PREP(WORD4_SETUP_OPERATION, slot); 277 } 278 279 /** 280 * set_din_sram() - Set the DIN field of a HW descriptor to SRAM mode. 281 * Note: No need to check SRAM alignment since host requests do not use SRAM and 282 * the adaptor will enforce alignment checks. 283 * 284 * @pdesc: Pointer to HW descriptor struct 285 * @addr: DIN address 286 * @size: Data size in bytes 287 */ set_din_sram(struct cc_hw_desc * pdesc,u32 addr,u32 size)288 static inline void set_din_sram(struct cc_hw_desc *pdesc, u32 addr, u32 size) 289 { 290 pdesc->word[0] = addr; 291 pdesc->word[1] |= FIELD_PREP(WORD1_DIN_SIZE, size) | 292 FIELD_PREP(WORD1_DIN_DMA_MODE, DMA_SRAM); 293 } 294 295 /** 296 * set_din_const() - Set the DIN field of a HW descriptor to CONST mode 297 * 298 * @pdesc: Pointer to HW descriptor struct 299 * @val: DIN const value 300 * @size: Data size in bytes 301 */ set_din_const(struct cc_hw_desc * pdesc,u32 val,u32 size)302 static inline void set_din_const(struct cc_hw_desc *pdesc, u32 val, u32 size) 303 { 304 pdesc->word[0] = val; 305 pdesc->word[1] |= FIELD_PREP(WORD1_DIN_CONST_VALUE, 1) | 306 FIELD_PREP(WORD1_DIN_DMA_MODE, DMA_SRAM) | 307 FIELD_PREP(WORD1_DIN_SIZE, size); 308 } 309 310 /** 311 * set_din_not_last_indication() - Set the DIN not last input data indicator 312 * 313 * @pdesc: Pointer to HW descriptor struct 314 */ set_din_not_last_indication(struct cc_hw_desc * pdesc)315 static inline void set_din_not_last_indication(struct cc_hw_desc *pdesc) 316 { 317 pdesc->word[1] |= FIELD_PREP(WORD1_NOT_LAST, 1); 318 } 319 320 /** 321 * set_dout_type() - Set the DOUT field of a HW descriptor 322 * 323 * @pdesc: Pointer to HW descriptor struct 324 * @dma_mode: The DMA mode: NO_DMA, SRAM, DLLI, MLLI, CONSTANT 325 * @addr: DOUT address 326 * @size: Data size in bytes 327 * @axi_sec: AXI secure bit 328 */ set_dout_type(struct cc_hw_desc * pdesc,enum cc_dma_mode dma_mode,dma_addr_t addr,u32 size,enum cc_axi_sec axi_sec)329 static inline void set_dout_type(struct cc_hw_desc *pdesc, 330 enum cc_dma_mode dma_mode, dma_addr_t addr, 331 u32 size, enum cc_axi_sec axi_sec) 332 { 333 pdesc->word[2] = lower_32_bits(addr); 334 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT 335 pdesc->word[5] |= FIELD_PREP(WORD5_DOUT_ADDR_HIGH, upper_32_bits(addr)); 336 #endif 337 pdesc->word[3] |= FIELD_PREP(WORD3_DOUT_DMA_MODE, dma_mode) | 338 FIELD_PREP(WORD3_DOUT_SIZE, size) | 339 FIELD_PREP(WORD3_NS_BIT, axi_sec); 340 } 341 342 /** 343 * set_dout_dlli() - Set the DOUT field of a HW descriptor to DLLI type 344 * The LAST INDICATION is provided by the user 345 * 346 * @pdesc: Pointer to HW descriptor struct 347 * @addr: DOUT address 348 * @size: Data size in bytes 349 * @axi_sec: AXI secure bit 350 * @last_ind: The last indication bit 351 */ set_dout_dlli(struct cc_hw_desc * pdesc,dma_addr_t addr,u32 size,enum cc_axi_sec axi_sec,u32 last_ind)352 static inline void set_dout_dlli(struct cc_hw_desc *pdesc, dma_addr_t addr, 353 u32 size, enum cc_axi_sec axi_sec, 354 u32 last_ind) 355 { 356 set_dout_type(pdesc, DMA_DLLI, addr, size, axi_sec); 357 pdesc->word[3] |= FIELD_PREP(WORD3_DOUT_LAST_IND, last_ind); 358 } 359 360 /** 361 * set_dout_mlli() - Set the DOUT field of a HW descriptor to MLLI type 362 * The LAST INDICATION is provided by the user 363 * 364 * @pdesc: Pointer to HW descriptor struct 365 * @addr: DOUT address 366 * @size: Data size in bytes 367 * @axi_sec: AXI secure bit 368 * @last_ind: The last indication bit 369 */ set_dout_mlli(struct cc_hw_desc * pdesc,u32 addr,u32 size,enum cc_axi_sec axi_sec,bool last_ind)370 static inline void set_dout_mlli(struct cc_hw_desc *pdesc, u32 addr, u32 size, 371 enum cc_axi_sec axi_sec, bool last_ind) 372 { 373 set_dout_type(pdesc, DMA_MLLI, addr, size, axi_sec); 374 pdesc->word[3] |= FIELD_PREP(WORD3_DOUT_LAST_IND, last_ind); 375 } 376 377 /** 378 * set_dout_no_dma() - Set the DOUT field of a HW descriptor to NO DMA mode. 379 * Used for NOP descriptor, register patches and other special modes. 380 * 381 * @pdesc: pointer to HW descriptor struct 382 * @addr: DOUT address 383 * @size: Data size in bytes 384 * @write_enable: Enables a write operation to a register 385 */ set_dout_no_dma(struct cc_hw_desc * pdesc,u32 addr,u32 size,bool write_enable)386 static inline void set_dout_no_dma(struct cc_hw_desc *pdesc, u32 addr, 387 u32 size, bool write_enable) 388 { 389 pdesc->word[2] = addr; 390 pdesc->word[3] |= FIELD_PREP(WORD3_DOUT_SIZE, size) | 391 FIELD_PREP(WORD3_DOUT_LAST_IND, write_enable); 392 } 393 394 /** 395 * set_xor_val() - Set the word for the XOR operation. 396 * 397 * @pdesc: Pointer to HW descriptor struct 398 * @val: XOR data value 399 */ set_xor_val(struct cc_hw_desc * pdesc,u32 val)400 static inline void set_xor_val(struct cc_hw_desc *pdesc, u32 val) 401 { 402 pdesc->word[2] = val; 403 } 404 405 /** 406 * set_xor_active() - Set the XOR indicator bit in the descriptor 407 * 408 * @pdesc: Pointer to HW descriptor struct 409 */ set_xor_active(struct cc_hw_desc * pdesc)410 static inline void set_xor_active(struct cc_hw_desc *pdesc) 411 { 412 pdesc->word[3] |= FIELD_PREP(WORD3_HASH_XOR_BIT, 1); 413 } 414 415 /** 416 * set_aes_not_hash_mode() - Select the AES engine instead of HASH engine when 417 * setting up combined mode with AES XCBC MAC 418 * 419 * @pdesc: Pointer to HW descriptor struct 420 */ set_aes_not_hash_mode(struct cc_hw_desc * pdesc)421 static inline void set_aes_not_hash_mode(struct cc_hw_desc *pdesc) 422 { 423 pdesc->word[4] |= FIELD_PREP(WORD4_AES_SEL_N_HASH, 1); 424 } 425 426 /** 427 * set_aes_xor_crypto_key() - Set aes xor crypto key, which in some scenarios 428 * selects the SM3 engine 429 * 430 * @pdesc: Pointer to HW descriptor struct 431 */ set_aes_xor_crypto_key(struct cc_hw_desc * pdesc)432 static inline void set_aes_xor_crypto_key(struct cc_hw_desc *pdesc) 433 { 434 pdesc->word[4] |= FIELD_PREP(WORD4_AES_XOR_CRYPTO_KEY, 1); 435 } 436 437 /** 438 * set_dout_sram() - Set the DOUT field of a HW descriptor to SRAM mode 439 * Note: No need to check SRAM alignment since host requests do not use SRAM and 440 * the adaptor will enforce alignment checks. 441 * 442 * @pdesc: Pointer to HW descriptor struct 443 * @addr: DOUT address 444 * @size: Data size in bytes 445 */ set_dout_sram(struct cc_hw_desc * pdesc,u32 addr,u32 size)446 static inline void set_dout_sram(struct cc_hw_desc *pdesc, u32 addr, u32 size) 447 { 448 pdesc->word[2] = addr; 449 pdesc->word[3] |= FIELD_PREP(WORD3_DOUT_DMA_MODE, DMA_SRAM) | 450 FIELD_PREP(WORD3_DOUT_SIZE, size); 451 } 452 453 /** 454 * set_xex_data_unit_size() - Set the data unit size for XEX mode in 455 * data_out_addr[15:0] 456 * 457 * @pdesc: Pointer to HW descriptor struct 458 * @size: Data unit size for XEX mode 459 */ set_xex_data_unit_size(struct cc_hw_desc * pdesc,u32 size)460 static inline void set_xex_data_unit_size(struct cc_hw_desc *pdesc, u32 size) 461 { 462 pdesc->word[2] = size; 463 } 464 465 /** 466 * set_multi2_num_rounds() - Set the number of rounds for Multi2 in 467 * data_out_addr[15:0] 468 * 469 * @pdesc: Pointer to HW descriptor struct 470 * @num: Number of rounds for Multi2 471 */ set_multi2_num_rounds(struct cc_hw_desc * pdesc,u32 num)472 static inline void set_multi2_num_rounds(struct cc_hw_desc *pdesc, u32 num) 473 { 474 pdesc->word[2] = num; 475 } 476 477 /** 478 * set_flow_mode() - Set the flow mode. 479 * 480 * @pdesc: Pointer to HW descriptor struct 481 * @mode: Any one of the modes defined in [CC7x-DESC] 482 */ set_flow_mode(struct cc_hw_desc * pdesc,enum cc_flow_mode mode)483 static inline void set_flow_mode(struct cc_hw_desc *pdesc, 484 enum cc_flow_mode mode) 485 { 486 pdesc->word[4] |= FIELD_PREP(WORD4_DATA_FLOW_MODE, mode); 487 } 488 489 /** 490 * set_cipher_mode() - Set the cipher mode. 491 * 492 * @pdesc: Pointer to HW descriptor struct 493 * @mode: Any one of the modes defined in [CC7x-DESC] 494 */ set_cipher_mode(struct cc_hw_desc * pdesc,int mode)495 static inline void set_cipher_mode(struct cc_hw_desc *pdesc, int mode) 496 { 497 pdesc->word[4] |= FIELD_PREP(WORD4_CIPHER_MODE, mode); 498 } 499 500 /** 501 * set_hash_cipher_mode() - Set the cipher mode for hash algorithms. 502 * 503 * @pdesc: Pointer to HW descriptor struct 504 * @cipher_mode: Any one of the modes defined in [CC7x-DESC] 505 * @hash_mode: specifies which hash is being handled 506 */ set_hash_cipher_mode(struct cc_hw_desc * pdesc,enum drv_cipher_mode cipher_mode,enum drv_hash_mode hash_mode)507 static inline void set_hash_cipher_mode(struct cc_hw_desc *pdesc, 508 enum drv_cipher_mode cipher_mode, 509 enum drv_hash_mode hash_mode) 510 { 511 set_cipher_mode(pdesc, cipher_mode); 512 if (hash_mode == DRV_HASH_SM3) 513 set_aes_xor_crypto_key(pdesc); 514 } 515 516 /** 517 * set_cipher_config0() - Set the cipher configuration fields. 518 * 519 * @pdesc: Pointer to HW descriptor struct 520 * @mode: Any one of the modes defined in [CC7x-DESC] 521 */ set_cipher_config0(struct cc_hw_desc * pdesc,int mode)522 static inline void set_cipher_config0(struct cc_hw_desc *pdesc, int mode) 523 { 524 pdesc->word[4] |= FIELD_PREP(WORD4_CIPHER_CONF0, mode); 525 } 526 527 /** 528 * set_cipher_config1() - Set the cipher configuration fields. 529 * 530 * @pdesc: Pointer to HW descriptor struct 531 * @config: Padding mode 532 */ set_cipher_config1(struct cc_hw_desc * pdesc,enum cc_hash_conf_pad config)533 static inline void set_cipher_config1(struct cc_hw_desc *pdesc, 534 enum cc_hash_conf_pad config) 535 { 536 pdesc->word[4] |= FIELD_PREP(WORD4_CIPHER_CONF1, config); 537 } 538 539 /** 540 * set_hw_crypto_key() - Set HW key configuration fields. 541 * 542 * @pdesc: Pointer to HW descriptor struct 543 * @hw_key: The HW key slot asdefined in enum cc_hw_crypto_key 544 */ set_hw_crypto_key(struct cc_hw_desc * pdesc,enum cc_hw_crypto_key hw_key)545 static inline void set_hw_crypto_key(struct cc_hw_desc *pdesc, 546 enum cc_hw_crypto_key hw_key) 547 { 548 pdesc->word[4] |= FIELD_PREP(WORD4_CIPHER_DO, 549 (hw_key & HW_KEY_MASK_CIPHER_DO)) | 550 FIELD_PREP(WORD4_CIPHER_CONF2, 551 (hw_key >> HW_KEY_SHIFT_CIPHER_CFG2)); 552 } 553 554 /** 555 * set_bytes_swap() - Set byte order of all setup-finalize descriptors. 556 * 557 * @pdesc: Pointer to HW descriptor struct 558 * @config: True to enable byte swapping 559 */ set_bytes_swap(struct cc_hw_desc * pdesc,bool config)560 static inline void set_bytes_swap(struct cc_hw_desc *pdesc, bool config) 561 { 562 pdesc->word[4] |= FIELD_PREP(WORD4_BYTES_SWAP, config); 563 } 564 565 /** 566 * set_cmac_size0_mode() - Set CMAC_SIZE0 mode. 567 * 568 * @pdesc: Pointer to HW descriptor struct 569 */ set_cmac_size0_mode(struct cc_hw_desc * pdesc)570 static inline void set_cmac_size0_mode(struct cc_hw_desc *pdesc) 571 { 572 pdesc->word[4] |= FIELD_PREP(WORD4_CMAC_SIZE0, 1); 573 } 574 575 /** 576 * set_key_size() - Set key size descriptor field. 577 * 578 * @pdesc: Pointer to HW descriptor struct 579 * @size: Key size in bytes (NOT size code) 580 */ set_key_size(struct cc_hw_desc * pdesc,u32 size)581 static inline void set_key_size(struct cc_hw_desc *pdesc, u32 size) 582 { 583 pdesc->word[4] |= FIELD_PREP(WORD4_KEY_SIZE, size); 584 } 585 586 /** 587 * set_key_size_aes() - Set AES key size. 588 * 589 * @pdesc: Pointer to HW descriptor struct 590 * @size: Key size in bytes (NOT size code) 591 */ set_key_size_aes(struct cc_hw_desc * pdesc,u32 size)592 static inline void set_key_size_aes(struct cc_hw_desc *pdesc, u32 size) 593 { 594 set_key_size(pdesc, ((size >> 3) - 2)); 595 } 596 597 /** 598 * set_key_size_des() - Set DES key size. 599 * 600 * @pdesc: Pointer to HW descriptor struct 601 * @size: Key size in bytes (NOT size code) 602 */ set_key_size_des(struct cc_hw_desc * pdesc,u32 size)603 static inline void set_key_size_des(struct cc_hw_desc *pdesc, u32 size) 604 { 605 set_key_size(pdesc, ((size >> 3) - 1)); 606 } 607 608 /** 609 * set_setup_mode() - Set the descriptor setup mode 610 * 611 * @pdesc: Pointer to HW descriptor struct 612 * @mode: Any one of the setup modes defined in [CC7x-DESC] 613 */ set_setup_mode(struct cc_hw_desc * pdesc,enum cc_setup_op mode)614 static inline void set_setup_mode(struct cc_hw_desc *pdesc, 615 enum cc_setup_op mode) 616 { 617 pdesc->word[4] |= FIELD_PREP(WORD4_SETUP_OPERATION, mode); 618 } 619 620 /** 621 * set_cipher_do() - Set the descriptor cipher DO 622 * 623 * @pdesc: Pointer to HW descriptor struct 624 * @config: Any one of the cipher do defined in [CC7x-DESC] 625 */ set_cipher_do(struct cc_hw_desc * pdesc,enum cc_hash_cipher_pad config)626 static inline void set_cipher_do(struct cc_hw_desc *pdesc, 627 enum cc_hash_cipher_pad config) 628 { 629 pdesc->word[4] |= FIELD_PREP(WORD4_CIPHER_DO, 630 (config & HW_KEY_MASK_CIPHER_DO)); 631 } 632 633 #endif /*__CC_HW_QUEUE_DEFS_H__*/ 634