1 /*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #include <linux/delay.h>
25 #include <linux/firmware.h>
26 #include <linux/module.h>
27 #include <linux/pci.h>
28
29 #include "amdgpu.h"
30 #include "amdgpu_ucode.h"
31 #include "amdgpu_trace.h"
32
33 #include "gc/gc_10_1_0_offset.h"
34 #include "gc/gc_10_1_0_sh_mask.h"
35 #include "ivsrcid/sdma0/irqsrcs_sdma0_5_0.h"
36 #include "ivsrcid/sdma1/irqsrcs_sdma1_5_0.h"
37
38 #include "soc15_common.h"
39 #include "soc15.h"
40 #include "navi10_sdma_pkt_open.h"
41 #include "nbio_v2_3.h"
42 #include "sdma_common.h"
43 #include "sdma_v5_0.h"
44
45 MODULE_FIRMWARE("amdgpu/navi10_sdma.bin");
46 MODULE_FIRMWARE("amdgpu/navi10_sdma1.bin");
47
48 MODULE_FIRMWARE("amdgpu/navi14_sdma.bin");
49 MODULE_FIRMWARE("amdgpu/navi14_sdma1.bin");
50
51 MODULE_FIRMWARE("amdgpu/navi12_sdma.bin");
52 MODULE_FIRMWARE("amdgpu/navi12_sdma1.bin");
53
54 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_sdma.bin");
55 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_sdma1.bin");
56
57 #define SDMA1_REG_OFFSET 0x600
58 #define SDMA0_HYP_DEC_REG_START 0x5880
59 #define SDMA0_HYP_DEC_REG_END 0x5893
60 #define SDMA1_HYP_DEC_REG_OFFSET 0x20
61
62 static const struct amdgpu_hwip_reg_entry sdma_reg_list_5_0[] = {
63 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_STATUS_REG),
64 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_STATUS1_REG),
65 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_STATUS2_REG),
66 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_STATUS3_REG),
67 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UCODE_CHECKSUM),
68 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RB_RPTR_FETCH_HI),
69 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RB_RPTR_FETCH),
70 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UTCL1_RD_STATUS),
71 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UTCL1_WR_STATUS),
72 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UTCL1_RD_XNACK0),
73 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UTCL1_RD_XNACK1),
74 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UTCL1_WR_XNACK0),
75 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UTCL1_WR_XNACK1),
76 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_RB_CNTL),
77 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_RB_RPTR),
78 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_RB_RPTR_HI),
79 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_RB_WPTR),
80 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_RB_WPTR_HI),
81 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_IB_OFFSET),
82 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_IB_BASE_LO),
83 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_IB_BASE_HI),
84 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_IB_CNTL),
85 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_IB_RPTR),
86 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_IB_SUB_REMAIN),
87 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_DUMMY_REG),
88 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_RB_CNTL),
89 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_RB_RPTR),
90 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_RB_RPTR_HI),
91 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_RB_WPTR),
92 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_RB_WPTR_HI),
93 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_IB_OFFSET),
94 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_IB_BASE_LO),
95 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_IB_BASE_HI),
96 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_DUMMY_REG),
97 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_RB_CNTL),
98 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_RB_RPTR),
99 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_RB_RPTR_HI),
100 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_RB_WPTR),
101 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_RB_WPTR_HI),
102 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_IB_OFFSET),
103 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_IB_BASE_LO),
104 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_IB_BASE_HI),
105 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_DUMMY_REG),
106 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_INT_STATUS),
107 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_VM_CNTL),
108 SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS2)
109 };
110
111 static void sdma_v5_0_set_ring_funcs(struct amdgpu_device *adev);
112 static void sdma_v5_0_set_buffer_funcs(struct amdgpu_device *adev);
113 static void sdma_v5_0_set_vm_pte_funcs(struct amdgpu_device *adev);
114 static void sdma_v5_0_set_irq_funcs(struct amdgpu_device *adev);
115
116 static const struct soc15_reg_golden golden_settings_sdma_5[] = {
117 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_CHICKEN_BITS, 0xffbf1f0f, 0x03ab0107),
118 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
119 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
120 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
121 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
122 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
123 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
124 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
125 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
126 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
127 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
128 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_UTCL1_PAGE, 0x00ffffff, 0x000c5c00),
129 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_CHICKEN_BITS, 0xffbf1f0f, 0x03ab0107),
130 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
131 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
132 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
133 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
134 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
135 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
136 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
137 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
138 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
139 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
140 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_UTCL1_PAGE, 0x00ffffff, 0x000c5c00)
141 };
142
143 static const struct soc15_reg_golden golden_settings_sdma_5_sriov[] = {
144 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
145 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
146 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
147 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
148 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
149 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
150 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
151 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
152 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
153 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
154 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
155 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
156 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
157 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
158 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
159 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
160 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
161 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
162 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
163 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
164 };
165
166 static const struct soc15_reg_golden golden_settings_sdma_nv10[] = {
167 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
168 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
169 };
170
171 static const struct soc15_reg_golden golden_settings_sdma_nv14[] = {
172 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
173 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
174 };
175
176 static const struct soc15_reg_golden golden_settings_sdma_nv12[] = {
177 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
178 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GB_ADDR_CONFIG, 0x001877ff, 0x00000044),
179 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x001877ff, 0x00000044),
180 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GB_ADDR_CONFIG, 0x001877ff, 0x00000044),
181 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x001877ff, 0x00000044),
182 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
183 };
184
185 static const struct soc15_reg_golden golden_settings_sdma_cyan_skillfish[] = {
186 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_CHICKEN_BITS, 0xffbf1f0f, 0x03ab0107),
187 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GB_ADDR_CONFIG, 0x001877ff, 0x00000044),
188 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x001877ff, 0x00000044),
189 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
190 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
191 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
192 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
193 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
194 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
195 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
196 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
197 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
198 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
199 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_UTCL1_PAGE, 0x007fffff, 0x004c5c00),
200 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_CHICKEN_BITS, 0xffbf1f0f, 0x03ab0107),
201 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GB_ADDR_CONFIG, 0x001877ff, 0x00000044),
202 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x001877ff, 0x00000044),
203 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
204 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
205 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
206 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
207 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
208 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
209 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
210 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
211 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
212 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
213 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_UTCL1_PAGE, 0x007fffff, 0x004c5c00)
214 };
215
sdma_v5_0_get_reg_offset(struct amdgpu_device * adev,u32 instance,u32 internal_offset)216 static u32 sdma_v5_0_get_reg_offset(struct amdgpu_device *adev, u32 instance, u32 internal_offset)
217 {
218 u32 base;
219
220 if (internal_offset >= SDMA0_HYP_DEC_REG_START &&
221 internal_offset <= SDMA0_HYP_DEC_REG_END) {
222 base = adev->reg_offset[GC_HWIP][0][1];
223 if (instance == 1)
224 internal_offset += SDMA1_HYP_DEC_REG_OFFSET;
225 } else {
226 base = adev->reg_offset[GC_HWIP][0][0];
227 if (instance == 1)
228 internal_offset += SDMA1_REG_OFFSET;
229 }
230
231 return base + internal_offset;
232 }
233
sdma_v5_0_init_golden_registers(struct amdgpu_device * adev)234 static void sdma_v5_0_init_golden_registers(struct amdgpu_device *adev)
235 {
236 switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) {
237 case IP_VERSION(5, 0, 0):
238 soc15_program_register_sequence(adev,
239 golden_settings_sdma_5,
240 (const u32)ARRAY_SIZE(golden_settings_sdma_5));
241 soc15_program_register_sequence(adev,
242 golden_settings_sdma_nv10,
243 (const u32)ARRAY_SIZE(golden_settings_sdma_nv10));
244 break;
245 case IP_VERSION(5, 0, 2):
246 soc15_program_register_sequence(adev,
247 golden_settings_sdma_5,
248 (const u32)ARRAY_SIZE(golden_settings_sdma_5));
249 soc15_program_register_sequence(adev,
250 golden_settings_sdma_nv14,
251 (const u32)ARRAY_SIZE(golden_settings_sdma_nv14));
252 break;
253 case IP_VERSION(5, 0, 5):
254 if (amdgpu_sriov_vf(adev))
255 soc15_program_register_sequence(adev,
256 golden_settings_sdma_5_sriov,
257 (const u32)ARRAY_SIZE(golden_settings_sdma_5_sriov));
258 else
259 soc15_program_register_sequence(adev,
260 golden_settings_sdma_5,
261 (const u32)ARRAY_SIZE(golden_settings_sdma_5));
262 soc15_program_register_sequence(adev,
263 golden_settings_sdma_nv12,
264 (const u32)ARRAY_SIZE(golden_settings_sdma_nv12));
265 break;
266 case IP_VERSION(5, 0, 1):
267 soc15_program_register_sequence(adev,
268 golden_settings_sdma_cyan_skillfish,
269 (const u32)ARRAY_SIZE(golden_settings_sdma_cyan_skillfish));
270 break;
271 default:
272 break;
273 }
274 }
275
276 /**
277 * sdma_v5_0_init_microcode - load ucode images from disk
278 *
279 * @adev: amdgpu_device pointer
280 *
281 * Use the firmware interface to load the ucode images into
282 * the driver (not loaded into hw).
283 * Returns 0 on success, error on failure.
284 */
285
286 // emulation only, won't work on real chip
287 // navi10 real chip need to use PSP to load firmware
sdma_v5_0_init_microcode(struct amdgpu_device * adev)288 static int sdma_v5_0_init_microcode(struct amdgpu_device *adev)
289 {
290 int ret, i;
291
292 for (i = 0; i < adev->sdma.num_instances; i++) {
293 ret = amdgpu_sdma_init_microcode(adev, i, false);
294 if (ret)
295 return ret;
296 }
297
298 return ret;
299 }
300
sdma_v5_0_ring_init_cond_exec(struct amdgpu_ring * ring,uint64_t addr)301 static unsigned sdma_v5_0_ring_init_cond_exec(struct amdgpu_ring *ring,
302 uint64_t addr)
303 {
304 unsigned ret;
305
306 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_COND_EXE));
307 amdgpu_ring_write(ring, lower_32_bits(addr));
308 amdgpu_ring_write(ring, upper_32_bits(addr));
309 amdgpu_ring_write(ring, 1);
310 /* this is the offset we need patch later */
311 ret = ring->wptr & ring->buf_mask;
312 /* insert dummy here and patch it later */
313 amdgpu_ring_write(ring, 0);
314
315 return ret;
316 }
317
318 /**
319 * sdma_v5_0_ring_get_rptr - get the current read pointer
320 *
321 * @ring: amdgpu ring pointer
322 *
323 * Get the current rptr from the hardware (NAVI10+).
324 */
sdma_v5_0_ring_get_rptr(struct amdgpu_ring * ring)325 static uint64_t sdma_v5_0_ring_get_rptr(struct amdgpu_ring *ring)
326 {
327 u64 *rptr;
328
329 /* XXX check if swapping is necessary on BE */
330 rptr = (u64 *)ring->rptr_cpu_addr;
331
332 DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr);
333 return ((*rptr) >> 2);
334 }
335
336 /**
337 * sdma_v5_0_ring_get_wptr - get the current write pointer
338 *
339 * @ring: amdgpu ring pointer
340 *
341 * Get the current wptr from the hardware (NAVI10+).
342 */
sdma_v5_0_ring_get_wptr(struct amdgpu_ring * ring)343 static uint64_t sdma_v5_0_ring_get_wptr(struct amdgpu_ring *ring)
344 {
345 struct amdgpu_device *adev = ring->adev;
346 u64 wptr;
347
348 if (ring->use_doorbell) {
349 /* XXX check if swapping is necessary on BE */
350 wptr = READ_ONCE(*((u64 *)ring->wptr_cpu_addr));
351 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr);
352 } else {
353 wptr = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI));
354 wptr = wptr << 32;
355 wptr |= RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR));
356 DRM_DEBUG("wptr before shift [%i] wptr == 0x%016llx\n", ring->me, wptr);
357 }
358
359 return wptr >> 2;
360 }
361
362 /**
363 * sdma_v5_0_ring_set_wptr - commit the write pointer
364 *
365 * @ring: amdgpu ring pointer
366 *
367 * Write the wptr back to the hardware (NAVI10+).
368 */
sdma_v5_0_ring_set_wptr(struct amdgpu_ring * ring)369 static void sdma_v5_0_ring_set_wptr(struct amdgpu_ring *ring)
370 {
371 struct amdgpu_device *adev = ring->adev;
372 uint32_t *wptr_saved;
373 uint32_t *is_queue_unmap;
374 uint64_t aggregated_db_index;
375 uint32_t mqd_size = adev->mqds[AMDGPU_HW_IP_DMA].mqd_size;
376
377 DRM_DEBUG("Setting write pointer\n");
378 if (ring->is_mes_queue) {
379 wptr_saved = (uint32_t *)(ring->mqd_ptr + mqd_size);
380 is_queue_unmap = (uint32_t *)(ring->mqd_ptr + mqd_size +
381 sizeof(uint32_t));
382 aggregated_db_index =
383 amdgpu_mes_get_aggregated_doorbell_index(adev,
384 AMDGPU_MES_PRIORITY_LEVEL_NORMAL);
385
386 atomic64_set((atomic64_t *)ring->wptr_cpu_addr,
387 ring->wptr << 2);
388 *wptr_saved = ring->wptr << 2;
389 if (*is_queue_unmap) {
390 WDOORBELL64(aggregated_db_index, ring->wptr << 2);
391 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",
392 ring->doorbell_index, ring->wptr << 2);
393 WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
394 } else {
395 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",
396 ring->doorbell_index, ring->wptr << 2);
397 WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
398
399 if (*is_queue_unmap)
400 WDOORBELL64(aggregated_db_index,
401 ring->wptr << 2);
402 }
403 } else {
404 if (ring->use_doorbell) {
405 DRM_DEBUG("Using doorbell -- "
406 "wptr_offs == 0x%08x "
407 "lower_32_bits(ring->wptr) << 2 == 0x%08x "
408 "upper_32_bits(ring->wptr) << 2 == 0x%08x\n",
409 ring->wptr_offs,
410 lower_32_bits(ring->wptr << 2),
411 upper_32_bits(ring->wptr << 2));
412 /* XXX check if swapping is necessary on BE */
413 atomic64_set((atomic64_t *)ring->wptr_cpu_addr,
414 ring->wptr << 2);
415 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",
416 ring->doorbell_index, ring->wptr << 2);
417 WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
418 } else {
419 DRM_DEBUG("Not using doorbell -- "
420 "mmSDMA%i_GFX_RB_WPTR == 0x%08x "
421 "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n",
422 ring->me,
423 lower_32_bits(ring->wptr << 2),
424 ring->me,
425 upper_32_bits(ring->wptr << 2));
426 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev,
427 ring->me, mmSDMA0_GFX_RB_WPTR),
428 lower_32_bits(ring->wptr << 2));
429 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev,
430 ring->me, mmSDMA0_GFX_RB_WPTR_HI),
431 upper_32_bits(ring->wptr << 2));
432 }
433 }
434 }
435
sdma_v5_0_ring_insert_nop(struct amdgpu_ring * ring,uint32_t count)436 static void sdma_v5_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
437 {
438 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
439 int i;
440
441 for (i = 0; i < count; i++)
442 if (sdma && sdma->burst_nop && (i == 0))
443 amdgpu_ring_write(ring, ring->funcs->nop |
444 SDMA_PKT_NOP_HEADER_COUNT(count - 1));
445 else
446 amdgpu_ring_write(ring, ring->funcs->nop);
447 }
448
449 /**
450 * sdma_v5_0_ring_emit_ib - Schedule an IB on the DMA engine
451 *
452 * @ring: amdgpu ring pointer
453 * @job: job to retrieve vmid from
454 * @ib: IB object to schedule
455 * @flags: unused
456 *
457 * Schedule an IB in the DMA ring (NAVI10).
458 */
sdma_v5_0_ring_emit_ib(struct amdgpu_ring * ring,struct amdgpu_job * job,struct amdgpu_ib * ib,uint32_t flags)459 static void sdma_v5_0_ring_emit_ib(struct amdgpu_ring *ring,
460 struct amdgpu_job *job,
461 struct amdgpu_ib *ib,
462 uint32_t flags)
463 {
464 unsigned vmid = AMDGPU_JOB_GET_VMID(job);
465 uint64_t csa_mc_addr = amdgpu_sdma_get_csa_mc_addr(ring, vmid);
466
467 /* An IB packet must end on a 8 DW boundary--the next dword
468 * must be on a 8-dword boundary. Our IB packet below is 6
469 * dwords long, thus add x number of NOPs, such that, in
470 * modular arithmetic,
471 * wptr + 6 + x = 8k, k >= 0, which in C is,
472 * (wptr + 6 + x) % 8 = 0.
473 * The expression below, is a solution of x.
474 */
475 sdma_v5_0_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7);
476
477 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
478 SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf));
479 /* base must be 32 byte aligned */
480 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
481 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
482 amdgpu_ring_write(ring, ib->length_dw);
483 amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr));
484 amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr));
485 }
486
487 /**
488 * sdma_v5_0_ring_emit_mem_sync - flush the IB by graphics cache rinse
489 *
490 * @ring: amdgpu ring pointer
491 *
492 * flush the IB by graphics cache rinse.
493 */
sdma_v5_0_ring_emit_mem_sync(struct amdgpu_ring * ring)494 static void sdma_v5_0_ring_emit_mem_sync(struct amdgpu_ring *ring)
495 {
496 uint32_t gcr_cntl = SDMA_GCR_GL2_INV | SDMA_GCR_GL2_WB | SDMA_GCR_GLM_INV |
497 SDMA_GCR_GL1_INV | SDMA_GCR_GLV_INV | SDMA_GCR_GLK_INV |
498 SDMA_GCR_GLI_INV(1);
499
500 /* flush entire cache L0/L1/L2, this can be optimized by performance requirement */
501 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_GCR_REQ));
502 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD1_BASE_VA_31_7(0));
503 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD2_GCR_CONTROL_15_0(gcr_cntl) |
504 SDMA_PKT_GCR_REQ_PAYLOAD2_BASE_VA_47_32(0));
505 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD3_LIMIT_VA_31_7(0) |
506 SDMA_PKT_GCR_REQ_PAYLOAD3_GCR_CONTROL_18_16(gcr_cntl >> 16));
507 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD4_LIMIT_VA_47_32(0) |
508 SDMA_PKT_GCR_REQ_PAYLOAD4_VMID(0));
509 }
510
511 /**
512 * sdma_v5_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
513 *
514 * @ring: amdgpu ring pointer
515 *
516 * Emit an hdp flush packet on the requested DMA ring.
517 */
sdma_v5_0_ring_emit_hdp_flush(struct amdgpu_ring * ring)518 static void sdma_v5_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
519 {
520 struct amdgpu_device *adev = ring->adev;
521 u32 ref_and_mask = 0;
522 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
523
524 if (ring->me == 0)
525 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0;
526 else
527 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma1;
528
529 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
530 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |
531 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
532 amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_done_offset(adev)) << 2);
533 amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_req_offset(adev)) << 2);
534 amdgpu_ring_write(ring, ref_and_mask); /* reference */
535 amdgpu_ring_write(ring, ref_and_mask); /* mask */
536 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
537 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
538 }
539
540 /**
541 * sdma_v5_0_ring_emit_fence - emit a fence on the DMA ring
542 *
543 * @ring: amdgpu ring pointer
544 * @addr: address
545 * @seq: sequence number
546 * @flags: fence related flags
547 *
548 * Add a DMA fence packet to the ring to write
549 * the fence seq number and DMA trap packet to generate
550 * an interrupt if needed (NAVI10).
551 */
sdma_v5_0_ring_emit_fence(struct amdgpu_ring * ring,u64 addr,u64 seq,unsigned flags)552 static void sdma_v5_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
553 unsigned flags)
554 {
555 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
556 /* write the fence */
557 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) |
558 SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); /* Ucached(UC) */
559 /* zero in first two bits */
560 BUG_ON(addr & 0x3);
561 amdgpu_ring_write(ring, lower_32_bits(addr));
562 amdgpu_ring_write(ring, upper_32_bits(addr));
563 amdgpu_ring_write(ring, lower_32_bits(seq));
564
565 /* optionally write high bits as well */
566 if (write64bit) {
567 addr += 4;
568 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) |
569 SDMA_PKT_FENCE_HEADER_MTYPE(0x3));
570 /* zero in first two bits */
571 BUG_ON(addr & 0x3);
572 amdgpu_ring_write(ring, lower_32_bits(addr));
573 amdgpu_ring_write(ring, upper_32_bits(addr));
574 amdgpu_ring_write(ring, upper_32_bits(seq));
575 }
576
577 if (flags & AMDGPU_FENCE_FLAG_INT) {
578 uint32_t ctx = ring->is_mes_queue ?
579 (ring->hw_queue_id | AMDGPU_FENCE_MES_QUEUE_FLAG) : 0;
580 /* generate an interrupt */
581 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
582 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(ctx));
583 }
584 }
585
586
587 /**
588 * sdma_v5_0_gfx_stop - stop the gfx async dma engines
589 *
590 * @adev: amdgpu_device pointer
591 *
592 * Stop the gfx async dma ring buffers (NAVI10).
593 */
sdma_v5_0_gfx_stop(struct amdgpu_device * adev)594 static void sdma_v5_0_gfx_stop(struct amdgpu_device *adev)
595 {
596 u32 rb_cntl, ib_cntl;
597 int i;
598
599 for (i = 0; i < adev->sdma.num_instances; i++) {
600 rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));
601 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
602 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
603 ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));
604 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
605 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
606 }
607 }
608
609 /**
610 * sdma_v5_0_rlc_stop - stop the compute async dma engines
611 *
612 * @adev: amdgpu_device pointer
613 *
614 * Stop the compute async dma queues (NAVI10).
615 */
sdma_v5_0_rlc_stop(struct amdgpu_device * adev)616 static void sdma_v5_0_rlc_stop(struct amdgpu_device *adev)
617 {
618 /* XXX todo */
619 }
620
621 /**
622 * sdma_v5_0_ctx_switch_enable - stop the async dma engines context switch
623 *
624 * @adev: amdgpu_device pointer
625 * @enable: enable/disable the DMA MEs context switch.
626 *
627 * Halt or unhalt the async dma engines context switch (NAVI10).
628 */
sdma_v5_0_ctx_switch_enable(struct amdgpu_device * adev,bool enable)629 static void sdma_v5_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
630 {
631 u32 f32_cntl = 0, phase_quantum = 0;
632 int i;
633
634 if (amdgpu_sdma_phase_quantum) {
635 unsigned value = amdgpu_sdma_phase_quantum;
636 unsigned unit = 0;
637
638 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
639 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) {
640 value = (value + 1) >> 1;
641 unit++;
642 }
643 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
644 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) {
645 value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
646 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT);
647 unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
648 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT);
649 WARN_ONCE(1,
650 "clamping sdma_phase_quantum to %uK clock cycles\n",
651 value << unit);
652 }
653 phase_quantum =
654 value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT |
655 unit << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT;
656 }
657
658 for (i = 0; i < adev->sdma.num_instances; i++) {
659 if (!amdgpu_sriov_vf(adev)) {
660 f32_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL));
661 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
662 AUTO_CTXSW_ENABLE, enable ? 1 : 0);
663 }
664
665 if (enable && amdgpu_sdma_phase_quantum) {
666 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE0_QUANTUM),
667 phase_quantum);
668 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE1_QUANTUM),
669 phase_quantum);
670 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE2_QUANTUM),
671 phase_quantum);
672 }
673 if (!amdgpu_sriov_vf(adev))
674 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL), f32_cntl);
675 }
676
677 }
678
679 /**
680 * sdma_v5_0_enable - stop the async dma engines
681 *
682 * @adev: amdgpu_device pointer
683 * @enable: enable/disable the DMA MEs.
684 *
685 * Halt or unhalt the async dma engines (NAVI10).
686 */
sdma_v5_0_enable(struct amdgpu_device * adev,bool enable)687 static void sdma_v5_0_enable(struct amdgpu_device *adev, bool enable)
688 {
689 u32 f32_cntl;
690 int i;
691
692 if (!enable) {
693 sdma_v5_0_gfx_stop(adev);
694 sdma_v5_0_rlc_stop(adev);
695 }
696
697 if (amdgpu_sriov_vf(adev))
698 return;
699
700 for (i = 0; i < adev->sdma.num_instances; i++) {
701 f32_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));
702 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1);
703 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl);
704 }
705 }
706
707 /**
708 * sdma_v5_0_gfx_resume - setup and start the async dma engines
709 *
710 * @adev: amdgpu_device pointer
711 *
712 * Set up the gfx DMA ring buffers and enable them (NAVI10).
713 * Returns 0 for success, error for failure.
714 */
sdma_v5_0_gfx_resume(struct amdgpu_device * adev)715 static int sdma_v5_0_gfx_resume(struct amdgpu_device *adev)
716 {
717 struct amdgpu_ring *ring;
718 u32 rb_cntl, ib_cntl;
719 u32 rb_bufsz;
720 u32 doorbell;
721 u32 doorbell_offset;
722 u32 temp;
723 u32 wptr_poll_cntl;
724 u64 wptr_gpu_addr;
725 int i, r;
726
727 for (i = 0; i < adev->sdma.num_instances; i++) {
728 ring = &adev->sdma.instance[i].ring;
729
730 if (!amdgpu_sriov_vf(adev))
731 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0);
732
733 /* Set ring buffer size in dwords */
734 rb_bufsz = order_base_2(ring->ring_size / 4);
735 rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));
736 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
737 #ifdef __BIG_ENDIAN
738 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
739 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
740 RPTR_WRITEBACK_SWAP_ENABLE, 1);
741 #endif
742 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
743
744 /* Initialize the ring buffer's read and write pointers */
745 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0);
746 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0);
747 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0);
748 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0);
749
750 /* setup the wptr shadow polling */
751 wptr_gpu_addr = ring->wptr_gpu_addr;
752 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO),
753 lower_32_bits(wptr_gpu_addr));
754 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI),
755 upper_32_bits(wptr_gpu_addr));
756 wptr_poll_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i,
757 mmSDMA0_GFX_RB_WPTR_POLL_CNTL));
758 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
759 SDMA0_GFX_RB_WPTR_POLL_CNTL,
760 F32_POLL_ENABLE, 1);
761 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL),
762 wptr_poll_cntl);
763
764 /* set the wb address whether it's enabled or not */
765 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_HI),
766 upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF);
767 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_LO),
768 lower_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFC);
769
770 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
771
772 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE),
773 ring->gpu_addr >> 8);
774 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE_HI),
775 ring->gpu_addr >> 40);
776
777 ring->wptr = 0;
778
779 /* before programing wptr to a less value, need set minor_ptr_update first */
780 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1);
781
782 if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */
783 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR),
784 lower_32_bits(ring->wptr << 2));
785 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI),
786 upper_32_bits(ring->wptr << 2));
787 }
788
789 doorbell = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL));
790 doorbell_offset = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i,
791 mmSDMA0_GFX_DOORBELL_OFFSET));
792
793 if (ring->use_doorbell) {
794 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1);
795 doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_GFX_DOORBELL_OFFSET,
796 OFFSET, ring->doorbell_index);
797 } else {
798 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0);
799 }
800 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL), doorbell);
801 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET),
802 doorbell_offset);
803
804 adev->nbio.funcs->sdma_doorbell_range(adev, i, ring->use_doorbell,
805 ring->doorbell_index, 20);
806
807 if (amdgpu_sriov_vf(adev))
808 sdma_v5_0_ring_set_wptr(ring);
809
810 /* set minor_ptr_update to 0 after wptr programed */
811 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0);
812
813 if (!amdgpu_sriov_vf(adev)) {
814 /* set utc l1 enable flag always to 1 */
815 temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL));
816 temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1);
817
818 /* enable MCBP */
819 temp = REG_SET_FIELD(temp, SDMA0_CNTL, MIDCMD_PREEMPT_ENABLE, 1);
820 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL), temp);
821
822 /* Set up RESP_MODE to non-copy addresses */
823 temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL));
824 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, RESP_MODE, 3);
825 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9);
826 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL), temp);
827
828 /* program default cache read and write policy */
829 temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE));
830 /* clean read policy and write policy bits */
831 temp &= 0xFF0FFF;
832 temp |= ((CACHE_READ_POLICY_L2__DEFAULT << 12) | (CACHE_WRITE_POLICY_L2__DEFAULT << 14));
833 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE), temp);
834 }
835
836 if (!amdgpu_sriov_vf(adev)) {
837 /* unhalt engine */
838 temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));
839 temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0);
840 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), temp);
841 }
842
843 /* enable DMA RB */
844 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
845 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
846
847 ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));
848 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
849 #ifdef __BIG_ENDIAN
850 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
851 #endif
852 /* enable DMA IBs */
853 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
854
855 if (amdgpu_sriov_vf(adev)) { /* bare-metal sequence doesn't need below to lines */
856 sdma_v5_0_ctx_switch_enable(adev, true);
857 sdma_v5_0_enable(adev, true);
858 }
859
860 r = amdgpu_ring_test_helper(ring);
861 if (r)
862 return r;
863 }
864
865 return 0;
866 }
867
868 /**
869 * sdma_v5_0_rlc_resume - setup and start the async dma engines
870 *
871 * @adev: amdgpu_device pointer
872 *
873 * Set up the compute DMA queues and enable them (NAVI10).
874 * Returns 0 for success, error for failure.
875 */
sdma_v5_0_rlc_resume(struct amdgpu_device * adev)876 static int sdma_v5_0_rlc_resume(struct amdgpu_device *adev)
877 {
878 return 0;
879 }
880
881 /**
882 * sdma_v5_0_load_microcode - load the sDMA ME ucode
883 *
884 * @adev: amdgpu_device pointer
885 *
886 * Loads the sDMA0/1 ucode.
887 * Returns 0 for success, -EINVAL if the ucode is not available.
888 */
sdma_v5_0_load_microcode(struct amdgpu_device * adev)889 static int sdma_v5_0_load_microcode(struct amdgpu_device *adev)
890 {
891 const struct sdma_firmware_header_v1_0 *hdr;
892 const __le32 *fw_data;
893 u32 fw_size;
894 int i, j;
895
896 /* halt the MEs */
897 sdma_v5_0_enable(adev, false);
898
899 for (i = 0; i < adev->sdma.num_instances; i++) {
900 if (!adev->sdma.instance[i].fw)
901 return -EINVAL;
902
903 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
904 amdgpu_ucode_print_sdma_hdr(&hdr->header);
905 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
906
907 fw_data = (const __le32 *)
908 (adev->sdma.instance[i].fw->data +
909 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
910
911 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), 0);
912
913 for (j = 0; j < fw_size; j++) {
914 if (amdgpu_emu_mode == 1 && j % 500 == 0)
915 msleep(1);
916 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UCODE_DATA), le32_to_cpup(fw_data++));
917 }
918
919 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), adev->sdma.instance[i].fw_version);
920 }
921
922 return 0;
923 }
924
925 /**
926 * sdma_v5_0_start - setup and start the async dma engines
927 *
928 * @adev: amdgpu_device pointer
929 *
930 * Set up the DMA engines and enable them (NAVI10).
931 * Returns 0 for success, error for failure.
932 */
sdma_v5_0_start(struct amdgpu_device * adev)933 static int sdma_v5_0_start(struct amdgpu_device *adev)
934 {
935 int r = 0;
936
937 if (amdgpu_sriov_vf(adev)) {
938 sdma_v5_0_ctx_switch_enable(adev, false);
939 sdma_v5_0_enable(adev, false);
940
941 /* set RB registers */
942 r = sdma_v5_0_gfx_resume(adev);
943 return r;
944 }
945
946 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
947 r = sdma_v5_0_load_microcode(adev);
948 if (r)
949 return r;
950 }
951
952 /* unhalt the MEs */
953 sdma_v5_0_enable(adev, true);
954 /* enable sdma ring preemption */
955 sdma_v5_0_ctx_switch_enable(adev, true);
956
957 /* start the gfx rings and rlc compute queues */
958 r = sdma_v5_0_gfx_resume(adev);
959 if (r)
960 return r;
961 r = sdma_v5_0_rlc_resume(adev);
962
963 return r;
964 }
965
sdma_v5_0_mqd_init(struct amdgpu_device * adev,void * mqd,struct amdgpu_mqd_prop * prop)966 static int sdma_v5_0_mqd_init(struct amdgpu_device *adev, void *mqd,
967 struct amdgpu_mqd_prop *prop)
968 {
969 struct v10_sdma_mqd *m = mqd;
970 uint64_t wb_gpu_addr;
971
972 m->sdmax_rlcx_rb_cntl =
973 order_base_2(prop->queue_size / 4) << SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT |
974 1 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT |
975 6 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT |
976 1 << SDMA0_RLC0_RB_CNTL__RB_PRIV__SHIFT;
977
978 m->sdmax_rlcx_rb_base = lower_32_bits(prop->hqd_base_gpu_addr >> 8);
979 m->sdmax_rlcx_rb_base_hi = upper_32_bits(prop->hqd_base_gpu_addr >> 8);
980
981 m->sdmax_rlcx_rb_wptr_poll_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, 0,
982 mmSDMA0_GFX_RB_WPTR_POLL_CNTL));
983
984 wb_gpu_addr = prop->wptr_gpu_addr;
985 m->sdmax_rlcx_rb_wptr_poll_addr_lo = lower_32_bits(wb_gpu_addr);
986 m->sdmax_rlcx_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr);
987
988 wb_gpu_addr = prop->rptr_gpu_addr;
989 m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits(wb_gpu_addr);
990 m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits(wb_gpu_addr);
991
992 m->sdmax_rlcx_ib_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, 0,
993 mmSDMA0_GFX_IB_CNTL));
994
995 m->sdmax_rlcx_doorbell_offset =
996 prop->doorbell_index << SDMA0_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT;
997
998 m->sdmax_rlcx_doorbell = REG_SET_FIELD(0, SDMA0_RLC0_DOORBELL, ENABLE, 1);
999
1000 return 0;
1001 }
1002
sdma_v5_0_set_mqd_funcs(struct amdgpu_device * adev)1003 static void sdma_v5_0_set_mqd_funcs(struct amdgpu_device *adev)
1004 {
1005 adev->mqds[AMDGPU_HW_IP_DMA].mqd_size = sizeof(struct v10_sdma_mqd);
1006 adev->mqds[AMDGPU_HW_IP_DMA].init_mqd = sdma_v5_0_mqd_init;
1007 }
1008
1009 /**
1010 * sdma_v5_0_ring_test_ring - simple async dma engine test
1011 *
1012 * @ring: amdgpu_ring structure holding ring information
1013 *
1014 * Test the DMA engine by writing using it to write an
1015 * value to memory. (NAVI10).
1016 * Returns 0 for success, error for failure.
1017 */
sdma_v5_0_ring_test_ring(struct amdgpu_ring * ring)1018 static int sdma_v5_0_ring_test_ring(struct amdgpu_ring *ring)
1019 {
1020 struct amdgpu_device *adev = ring->adev;
1021 unsigned i;
1022 unsigned index;
1023 int r;
1024 u32 tmp;
1025 u64 gpu_addr;
1026 volatile uint32_t *cpu_ptr = NULL;
1027
1028 tmp = 0xCAFEDEAD;
1029
1030 if (ring->is_mes_queue) {
1031 uint32_t offset = 0;
1032 offset = amdgpu_mes_ctx_get_offs(ring,
1033 AMDGPU_MES_CTX_PADDING_OFFS);
1034 gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
1035 cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
1036 *cpu_ptr = tmp;
1037 } else {
1038 r = amdgpu_device_wb_get(adev, &index);
1039 if (r) {
1040 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
1041 return r;
1042 }
1043
1044 gpu_addr = adev->wb.gpu_addr + (index * 4);
1045 adev->wb.wb[index] = cpu_to_le32(tmp);
1046 }
1047
1048 r = amdgpu_ring_alloc(ring, 20);
1049 if (r) {
1050 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r);
1051 if (!ring->is_mes_queue)
1052 amdgpu_device_wb_free(adev, index);
1053 return r;
1054 }
1055
1056 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1057 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
1058 amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
1059 amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
1060 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0));
1061 amdgpu_ring_write(ring, 0xDEADBEEF);
1062 amdgpu_ring_commit(ring);
1063
1064 for (i = 0; i < adev->usec_timeout; i++) {
1065 if (ring->is_mes_queue)
1066 tmp = le32_to_cpu(*cpu_ptr);
1067 else
1068 tmp = le32_to_cpu(adev->wb.wb[index]);
1069 if (tmp == 0xDEADBEEF)
1070 break;
1071 if (amdgpu_emu_mode == 1)
1072 msleep(1);
1073 else
1074 udelay(1);
1075 }
1076
1077 if (i >= adev->usec_timeout)
1078 r = -ETIMEDOUT;
1079
1080 if (!ring->is_mes_queue)
1081 amdgpu_device_wb_free(adev, index);
1082
1083 return r;
1084 }
1085
1086 /**
1087 * sdma_v5_0_ring_test_ib - test an IB on the DMA engine
1088 *
1089 * @ring: amdgpu_ring structure holding ring information
1090 * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT
1091 *
1092 * Test a simple IB in the DMA ring (NAVI10).
1093 * Returns 0 on success, error on failure.
1094 */
sdma_v5_0_ring_test_ib(struct amdgpu_ring * ring,long timeout)1095 static int sdma_v5_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
1096 {
1097 struct amdgpu_device *adev = ring->adev;
1098 struct amdgpu_ib ib;
1099 struct dma_fence *f = NULL;
1100 unsigned index;
1101 long r;
1102 u32 tmp = 0;
1103 u64 gpu_addr;
1104 volatile uint32_t *cpu_ptr = NULL;
1105
1106 tmp = 0xCAFEDEAD;
1107 memset(&ib, 0, sizeof(ib));
1108
1109 if (ring->is_mes_queue) {
1110 uint32_t offset = 0;
1111 offset = amdgpu_mes_ctx_get_offs(ring, AMDGPU_MES_CTX_IB_OFFS);
1112 ib.gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
1113 ib.ptr = (void *)amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
1114
1115 offset = amdgpu_mes_ctx_get_offs(ring,
1116 AMDGPU_MES_CTX_PADDING_OFFS);
1117 gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
1118 cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
1119 *cpu_ptr = tmp;
1120 } else {
1121 r = amdgpu_device_wb_get(adev, &index);
1122 if (r) {
1123 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r);
1124 return r;
1125 }
1126
1127 gpu_addr = adev->wb.gpu_addr + (index * 4);
1128 adev->wb.wb[index] = cpu_to_le32(tmp);
1129
1130 r = amdgpu_ib_get(adev, NULL, 256,
1131 AMDGPU_IB_POOL_DIRECT, &ib);
1132 if (r) {
1133 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
1134 goto err0;
1135 }
1136 }
1137
1138 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1139 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1140 ib.ptr[1] = lower_32_bits(gpu_addr);
1141 ib.ptr[2] = upper_32_bits(gpu_addr);
1142 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0);
1143 ib.ptr[4] = 0xDEADBEEF;
1144 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1145 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1146 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1147 ib.length_dw = 8;
1148
1149 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
1150 if (r)
1151 goto err1;
1152
1153 r = dma_fence_wait_timeout(f, false, timeout);
1154 if (r == 0) {
1155 DRM_ERROR("amdgpu: IB test timed out\n");
1156 r = -ETIMEDOUT;
1157 goto err1;
1158 } else if (r < 0) {
1159 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
1160 goto err1;
1161 }
1162
1163 if (ring->is_mes_queue)
1164 tmp = le32_to_cpu(*cpu_ptr);
1165 else
1166 tmp = le32_to_cpu(adev->wb.wb[index]);
1167
1168 if (tmp == 0xDEADBEEF)
1169 r = 0;
1170 else
1171 r = -EINVAL;
1172
1173 err1:
1174 amdgpu_ib_free(adev, &ib, NULL);
1175 dma_fence_put(f);
1176 err0:
1177 if (!ring->is_mes_queue)
1178 amdgpu_device_wb_free(adev, index);
1179 return r;
1180 }
1181
1182
1183 /**
1184 * sdma_v5_0_vm_copy_pte - update PTEs by copying them from the GART
1185 *
1186 * @ib: indirect buffer to fill with commands
1187 * @pe: addr of the page entry
1188 * @src: src addr to copy from
1189 * @count: number of page entries to update
1190 *
1191 * Update PTEs by copying them from the GART using sDMA (NAVI10).
1192 */
sdma_v5_0_vm_copy_pte(struct amdgpu_ib * ib,uint64_t pe,uint64_t src,unsigned count)1193 static void sdma_v5_0_vm_copy_pte(struct amdgpu_ib *ib,
1194 uint64_t pe, uint64_t src,
1195 unsigned count)
1196 {
1197 unsigned bytes = count * 8;
1198
1199 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1200 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1201 ib->ptr[ib->length_dw++] = bytes - 1;
1202 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1203 ib->ptr[ib->length_dw++] = lower_32_bits(src);
1204 ib->ptr[ib->length_dw++] = upper_32_bits(src);
1205 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1206 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1207
1208 }
1209
1210 /**
1211 * sdma_v5_0_vm_write_pte - update PTEs by writing them manually
1212 *
1213 * @ib: indirect buffer to fill with commands
1214 * @pe: addr of the page entry
1215 * @value: dst addr to write into pe
1216 * @count: number of page entries to update
1217 * @incr: increase next addr by incr bytes
1218 *
1219 * Update PTEs by writing them manually using sDMA (NAVI10).
1220 */
sdma_v5_0_vm_write_pte(struct amdgpu_ib * ib,uint64_t pe,uint64_t value,unsigned count,uint32_t incr)1221 static void sdma_v5_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
1222 uint64_t value, unsigned count,
1223 uint32_t incr)
1224 {
1225 unsigned ndw = count * 2;
1226
1227 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1228 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1229 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1230 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1231 ib->ptr[ib->length_dw++] = ndw - 1;
1232 for (; ndw > 0; ndw -= 2) {
1233 ib->ptr[ib->length_dw++] = lower_32_bits(value);
1234 ib->ptr[ib->length_dw++] = upper_32_bits(value);
1235 value += incr;
1236 }
1237 }
1238
1239 /**
1240 * sdma_v5_0_vm_set_pte_pde - update the page tables using sDMA
1241 *
1242 * @ib: indirect buffer to fill with commands
1243 * @pe: addr of the page entry
1244 * @addr: dst addr to write into pe
1245 * @count: number of page entries to update
1246 * @incr: increase next addr by incr bytes
1247 * @flags: access flags
1248 *
1249 * Update the page tables using sDMA (NAVI10).
1250 */
sdma_v5_0_vm_set_pte_pde(struct amdgpu_ib * ib,uint64_t pe,uint64_t addr,unsigned count,uint32_t incr,uint64_t flags)1251 static void sdma_v5_0_vm_set_pte_pde(struct amdgpu_ib *ib,
1252 uint64_t pe,
1253 uint64_t addr, unsigned count,
1254 uint32_t incr, uint64_t flags)
1255 {
1256 /* for physically contiguous pages (vram) */
1257 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE);
1258 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
1259 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1260 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
1261 ib->ptr[ib->length_dw++] = upper_32_bits(flags);
1262 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
1263 ib->ptr[ib->length_dw++] = upper_32_bits(addr);
1264 ib->ptr[ib->length_dw++] = incr; /* increment size */
1265 ib->ptr[ib->length_dw++] = 0;
1266 ib->ptr[ib->length_dw++] = count - 1; /* number of entries */
1267 }
1268
1269 /**
1270 * sdma_v5_0_ring_pad_ib - pad the IB
1271 * @ring: amdgpu_ring structure holding ring information
1272 * @ib: indirect buffer to fill with padding
1273 *
1274 * Pad the IB with NOPs to a boundary multiple of 8.
1275 */
sdma_v5_0_ring_pad_ib(struct amdgpu_ring * ring,struct amdgpu_ib * ib)1276 static void sdma_v5_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
1277 {
1278 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
1279 u32 pad_count;
1280 int i;
1281
1282 pad_count = (-ib->length_dw) & 0x7;
1283 for (i = 0; i < pad_count; i++)
1284 if (sdma && sdma->burst_nop && (i == 0))
1285 ib->ptr[ib->length_dw++] =
1286 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) |
1287 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
1288 else
1289 ib->ptr[ib->length_dw++] =
1290 SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
1291 }
1292
1293
1294 /**
1295 * sdma_v5_0_ring_emit_pipeline_sync - sync the pipeline
1296 *
1297 * @ring: amdgpu_ring pointer
1298 *
1299 * Make sure all previous operations are completed (CIK).
1300 */
sdma_v5_0_ring_emit_pipeline_sync(struct amdgpu_ring * ring)1301 static void sdma_v5_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1302 {
1303 uint32_t seq = ring->fence_drv.sync_seq;
1304 uint64_t addr = ring->fence_drv.gpu_addr;
1305
1306 /* wait for idle */
1307 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1308 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1309 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */
1310 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1));
1311 amdgpu_ring_write(ring, addr & 0xfffffffc);
1312 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
1313 amdgpu_ring_write(ring, seq); /* reference */
1314 amdgpu_ring_write(ring, 0xffffffff); /* mask */
1315 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1316 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */
1317 }
1318
1319
1320 /**
1321 * sdma_v5_0_ring_emit_vm_flush - vm flush using sDMA
1322 *
1323 * @ring: amdgpu_ring pointer
1324 * @vmid: vmid number to use
1325 * @pd_addr: address
1326 *
1327 * Update the page table base and flush the VM TLB
1328 * using sDMA (NAVI10).
1329 */
sdma_v5_0_ring_emit_vm_flush(struct amdgpu_ring * ring,unsigned vmid,uint64_t pd_addr)1330 static void sdma_v5_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
1331 unsigned vmid, uint64_t pd_addr)
1332 {
1333 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1334 }
1335
sdma_v5_0_ring_emit_wreg(struct amdgpu_ring * ring,uint32_t reg,uint32_t val)1336 static void sdma_v5_0_ring_emit_wreg(struct amdgpu_ring *ring,
1337 uint32_t reg, uint32_t val)
1338 {
1339 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1340 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1341 amdgpu_ring_write(ring, reg);
1342 amdgpu_ring_write(ring, val);
1343 }
1344
sdma_v5_0_ring_emit_reg_wait(struct amdgpu_ring * ring,uint32_t reg,uint32_t val,uint32_t mask)1345 static void sdma_v5_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
1346 uint32_t val, uint32_t mask)
1347 {
1348 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1349 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1350 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* equal */
1351 amdgpu_ring_write(ring, reg << 2);
1352 amdgpu_ring_write(ring, 0);
1353 amdgpu_ring_write(ring, val); /* reference */
1354 amdgpu_ring_write(ring, mask); /* mask */
1355 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1356 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10));
1357 }
1358
sdma_v5_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring * ring,uint32_t reg0,uint32_t reg1,uint32_t ref,uint32_t mask)1359 static void sdma_v5_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
1360 uint32_t reg0, uint32_t reg1,
1361 uint32_t ref, uint32_t mask)
1362 {
1363 amdgpu_ring_emit_wreg(ring, reg0, ref);
1364 /* wait for a cycle to reset vm_inv_eng*_ack */
1365 amdgpu_ring_emit_reg_wait(ring, reg0, 0, 0);
1366 amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask);
1367 }
1368
sdma_v5_0_early_init(void * handle)1369 static int sdma_v5_0_early_init(void *handle)
1370 {
1371 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1372 int r;
1373
1374 r = sdma_v5_0_init_microcode(adev);
1375 if (r)
1376 return r;
1377
1378 sdma_v5_0_set_ring_funcs(adev);
1379 sdma_v5_0_set_buffer_funcs(adev);
1380 sdma_v5_0_set_vm_pte_funcs(adev);
1381 sdma_v5_0_set_irq_funcs(adev);
1382 sdma_v5_0_set_mqd_funcs(adev);
1383
1384 return 0;
1385 }
1386
1387
sdma_v5_0_sw_init(void * handle)1388 static int sdma_v5_0_sw_init(void *handle)
1389 {
1390 struct amdgpu_ring *ring;
1391 int r, i;
1392 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1393 uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_5_0);
1394 uint32_t *ptr;
1395
1396 /* SDMA trap event */
1397 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA0,
1398 SDMA0_5_0__SRCID__SDMA_TRAP,
1399 &adev->sdma.trap_irq);
1400 if (r)
1401 return r;
1402
1403 /* SDMA trap event */
1404 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA1,
1405 SDMA1_5_0__SRCID__SDMA_TRAP,
1406 &adev->sdma.trap_irq);
1407 if (r)
1408 return r;
1409
1410 for (i = 0; i < adev->sdma.num_instances; i++) {
1411 ring = &adev->sdma.instance[i].ring;
1412 ring->ring_obj = NULL;
1413 ring->use_doorbell = true;
1414
1415 DRM_DEBUG("SDMA %d use_doorbell being set to: [%s]\n", i,
1416 ring->use_doorbell?"true":"false");
1417
1418 ring->doorbell_index = (i == 0) ?
1419 (adev->doorbell_index.sdma_engine[0] << 1) //get DWORD offset
1420 : (adev->doorbell_index.sdma_engine[1] << 1); // get DWORD offset
1421
1422 ring->vm_hub = AMDGPU_GFXHUB(0);
1423 sprintf(ring->name, "sdma%d", i);
1424 r = amdgpu_ring_init(adev, ring, 1024, &adev->sdma.trap_irq,
1425 (i == 0) ? AMDGPU_SDMA_IRQ_INSTANCE0 :
1426 AMDGPU_SDMA_IRQ_INSTANCE1,
1427 AMDGPU_RING_PRIO_DEFAULT, NULL);
1428 if (r)
1429 return r;
1430 }
1431
1432 /* Allocate memory for SDMA IP Dump buffer */
1433 ptr = kcalloc(adev->sdma.num_instances * reg_count, sizeof(uint32_t), GFP_KERNEL);
1434 if (ptr)
1435 adev->sdma.ip_dump = ptr;
1436 else
1437 DRM_ERROR("Failed to allocated memory for SDMA IP Dump\n");
1438
1439 return r;
1440 }
1441
sdma_v5_0_sw_fini(void * handle)1442 static int sdma_v5_0_sw_fini(void *handle)
1443 {
1444 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1445 int i;
1446
1447 for (i = 0; i < adev->sdma.num_instances; i++)
1448 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
1449
1450 amdgpu_sdma_destroy_inst_ctx(adev, false);
1451
1452 kfree(adev->sdma.ip_dump);
1453
1454 return 0;
1455 }
1456
sdma_v5_0_hw_init(void * handle)1457 static int sdma_v5_0_hw_init(void *handle)
1458 {
1459 int r;
1460 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1461
1462 sdma_v5_0_init_golden_registers(adev);
1463
1464 r = sdma_v5_0_start(adev);
1465
1466 return r;
1467 }
1468
sdma_v5_0_hw_fini(void * handle)1469 static int sdma_v5_0_hw_fini(void *handle)
1470 {
1471 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1472
1473 if (amdgpu_sriov_vf(adev))
1474 return 0;
1475
1476 sdma_v5_0_ctx_switch_enable(adev, false);
1477 sdma_v5_0_enable(adev, false);
1478
1479 return 0;
1480 }
1481
sdma_v5_0_suspend(void * handle)1482 static int sdma_v5_0_suspend(void *handle)
1483 {
1484 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1485
1486 return sdma_v5_0_hw_fini(adev);
1487 }
1488
sdma_v5_0_resume(void * handle)1489 static int sdma_v5_0_resume(void *handle)
1490 {
1491 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1492
1493 return sdma_v5_0_hw_init(adev);
1494 }
1495
sdma_v5_0_is_idle(void * handle)1496 static bool sdma_v5_0_is_idle(void *handle)
1497 {
1498 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1499 u32 i;
1500
1501 for (i = 0; i < adev->sdma.num_instances; i++) {
1502 u32 tmp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_STATUS_REG));
1503
1504 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK))
1505 return false;
1506 }
1507
1508 return true;
1509 }
1510
sdma_v5_0_wait_for_idle(void * handle)1511 static int sdma_v5_0_wait_for_idle(void *handle)
1512 {
1513 unsigned i;
1514 u32 sdma0, sdma1;
1515 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1516
1517 for (i = 0; i < adev->usec_timeout; i++) {
1518 sdma0 = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_STATUS_REG));
1519 sdma1 = RREG32(sdma_v5_0_get_reg_offset(adev, 1, mmSDMA0_STATUS_REG));
1520
1521 if (sdma0 & sdma1 & SDMA0_STATUS_REG__IDLE_MASK)
1522 return 0;
1523 udelay(1);
1524 }
1525 return -ETIMEDOUT;
1526 }
1527
sdma_v5_0_soft_reset(void * handle)1528 static int sdma_v5_0_soft_reset(void *handle)
1529 {
1530 /* todo */
1531
1532 return 0;
1533 }
1534
sdma_v5_0_ring_preempt_ib(struct amdgpu_ring * ring)1535 static int sdma_v5_0_ring_preempt_ib(struct amdgpu_ring *ring)
1536 {
1537 int i, r = 0;
1538 struct amdgpu_device *adev = ring->adev;
1539 u32 index = 0;
1540 u64 sdma_gfx_preempt;
1541
1542 amdgpu_sdma_get_index_from_ring(ring, &index);
1543 if (index == 0)
1544 sdma_gfx_preempt = mmSDMA0_GFX_PREEMPT;
1545 else
1546 sdma_gfx_preempt = mmSDMA1_GFX_PREEMPT;
1547
1548 /* assert preemption condition */
1549 amdgpu_ring_set_preempt_cond_exec(ring, false);
1550
1551 /* emit the trailing fence */
1552 ring->trail_seq += 1;
1553 amdgpu_ring_alloc(ring, 10);
1554 sdma_v5_0_ring_emit_fence(ring, ring->trail_fence_gpu_addr,
1555 ring->trail_seq, 0);
1556 amdgpu_ring_commit(ring);
1557
1558 /* assert IB preemption */
1559 WREG32(sdma_gfx_preempt, 1);
1560
1561 /* poll the trailing fence */
1562 for (i = 0; i < adev->usec_timeout; i++) {
1563 if (ring->trail_seq ==
1564 le32_to_cpu(*(ring->trail_fence_cpu_addr)))
1565 break;
1566 udelay(1);
1567 }
1568
1569 if (i >= adev->usec_timeout) {
1570 r = -EINVAL;
1571 DRM_ERROR("ring %d failed to be preempted\n", ring->idx);
1572 }
1573
1574 /* deassert IB preemption */
1575 WREG32(sdma_gfx_preempt, 0);
1576
1577 /* deassert the preemption condition */
1578 amdgpu_ring_set_preempt_cond_exec(ring, true);
1579 return r;
1580 }
1581
sdma_v5_0_set_trap_irq_state(struct amdgpu_device * adev,struct amdgpu_irq_src * source,unsigned type,enum amdgpu_interrupt_state state)1582 static int sdma_v5_0_set_trap_irq_state(struct amdgpu_device *adev,
1583 struct amdgpu_irq_src *source,
1584 unsigned type,
1585 enum amdgpu_interrupt_state state)
1586 {
1587 u32 sdma_cntl;
1588
1589 if (!amdgpu_sriov_vf(adev)) {
1590 u32 reg_offset = (type == AMDGPU_SDMA_IRQ_INSTANCE0) ?
1591 sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_CNTL) :
1592 sdma_v5_0_get_reg_offset(adev, 1, mmSDMA0_CNTL);
1593
1594 sdma_cntl = RREG32(reg_offset);
1595 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE,
1596 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
1597 WREG32(reg_offset, sdma_cntl);
1598 }
1599
1600 return 0;
1601 }
1602
sdma_v5_0_process_trap_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)1603 static int sdma_v5_0_process_trap_irq(struct amdgpu_device *adev,
1604 struct amdgpu_irq_src *source,
1605 struct amdgpu_iv_entry *entry)
1606 {
1607 uint32_t mes_queue_id = entry->src_data[0];
1608
1609 DRM_DEBUG("IH: SDMA trap\n");
1610
1611 if (adev->enable_mes && (mes_queue_id & AMDGPU_FENCE_MES_QUEUE_FLAG)) {
1612 struct amdgpu_mes_queue *queue;
1613
1614 mes_queue_id &= AMDGPU_FENCE_MES_QUEUE_ID_MASK;
1615
1616 spin_lock(&adev->mes.queue_id_lock);
1617 queue = idr_find(&adev->mes.queue_id_idr, mes_queue_id);
1618 if (queue) {
1619 DRM_DEBUG("process smda queue id = %d\n", mes_queue_id);
1620 amdgpu_fence_process(queue->ring);
1621 }
1622 spin_unlock(&adev->mes.queue_id_lock);
1623 return 0;
1624 }
1625
1626 switch (entry->client_id) {
1627 case SOC15_IH_CLIENTID_SDMA0:
1628 switch (entry->ring_id) {
1629 case 0:
1630 amdgpu_fence_process(&adev->sdma.instance[0].ring);
1631 break;
1632 case 1:
1633 /* XXX compute */
1634 break;
1635 case 2:
1636 /* XXX compute */
1637 break;
1638 case 3:
1639 /* XXX page queue*/
1640 break;
1641 }
1642 break;
1643 case SOC15_IH_CLIENTID_SDMA1:
1644 switch (entry->ring_id) {
1645 case 0:
1646 amdgpu_fence_process(&adev->sdma.instance[1].ring);
1647 break;
1648 case 1:
1649 /* XXX compute */
1650 break;
1651 case 2:
1652 /* XXX compute */
1653 break;
1654 case 3:
1655 /* XXX page queue*/
1656 break;
1657 }
1658 break;
1659 }
1660 return 0;
1661 }
1662
sdma_v5_0_process_illegal_inst_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)1663 static int sdma_v5_0_process_illegal_inst_irq(struct amdgpu_device *adev,
1664 struct amdgpu_irq_src *source,
1665 struct amdgpu_iv_entry *entry)
1666 {
1667 return 0;
1668 }
1669
sdma_v5_0_update_medium_grain_clock_gating(struct amdgpu_device * adev,bool enable)1670 static void sdma_v5_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
1671 bool enable)
1672 {
1673 uint32_t data, def;
1674 int i;
1675
1676 for (i = 0; i < adev->sdma.num_instances; i++) {
1677 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
1678 /* Enable sdma clock gating */
1679 def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL));
1680 data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
1681 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1682 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1683 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1684 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1685 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1686 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1687 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
1688 if (def != data)
1689 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data);
1690 } else {
1691 /* Disable sdma clock gating */
1692 def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL));
1693 data |= (SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
1694 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1695 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1696 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1697 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1698 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1699 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1700 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
1701 if (def != data)
1702 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data);
1703 }
1704 }
1705 }
1706
sdma_v5_0_update_medium_grain_light_sleep(struct amdgpu_device * adev,bool enable)1707 static void sdma_v5_0_update_medium_grain_light_sleep(struct amdgpu_device *adev,
1708 bool enable)
1709 {
1710 uint32_t data, def;
1711 int i;
1712
1713 for (i = 0; i < adev->sdma.num_instances; i++) {
1714 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
1715 /* Enable sdma mem light sleep */
1716 def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL));
1717 data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1718 if (def != data)
1719 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data);
1720
1721 } else {
1722 /* Disable sdma mem light sleep */
1723 def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL));
1724 data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1725 if (def != data)
1726 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data);
1727
1728 }
1729 }
1730 }
1731
sdma_v5_0_set_clockgating_state(void * handle,enum amd_clockgating_state state)1732 static int sdma_v5_0_set_clockgating_state(void *handle,
1733 enum amd_clockgating_state state)
1734 {
1735 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1736
1737 if (amdgpu_sriov_vf(adev))
1738 return 0;
1739
1740 switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) {
1741 case IP_VERSION(5, 0, 0):
1742 case IP_VERSION(5, 0, 2):
1743 case IP_VERSION(5, 0, 5):
1744 sdma_v5_0_update_medium_grain_clock_gating(adev,
1745 state == AMD_CG_STATE_GATE);
1746 sdma_v5_0_update_medium_grain_light_sleep(adev,
1747 state == AMD_CG_STATE_GATE);
1748 break;
1749 default:
1750 break;
1751 }
1752
1753 return 0;
1754 }
1755
sdma_v5_0_set_powergating_state(void * handle,enum amd_powergating_state state)1756 static int sdma_v5_0_set_powergating_state(void *handle,
1757 enum amd_powergating_state state)
1758 {
1759 return 0;
1760 }
1761
sdma_v5_0_get_clockgating_state(void * handle,u64 * flags)1762 static void sdma_v5_0_get_clockgating_state(void *handle, u64 *flags)
1763 {
1764 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1765 int data;
1766
1767 if (amdgpu_sriov_vf(adev))
1768 *flags = 0;
1769
1770 /* AMD_CG_SUPPORT_SDMA_MGCG */
1771 data = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_CLK_CTRL));
1772 if (!(data & SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK))
1773 *flags |= AMD_CG_SUPPORT_SDMA_MGCG;
1774
1775 /* AMD_CG_SUPPORT_SDMA_LS */
1776 data = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_POWER_CNTL));
1777 if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK)
1778 *flags |= AMD_CG_SUPPORT_SDMA_LS;
1779 }
1780
sdma_v5_0_print_ip_state(void * handle,struct drm_printer * p)1781 static void sdma_v5_0_print_ip_state(void *handle, struct drm_printer *p)
1782 {
1783 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1784 int i, j;
1785 uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_5_0);
1786 uint32_t instance_offset;
1787
1788 if (!adev->sdma.ip_dump)
1789 return;
1790
1791 drm_printf(p, "num_instances:%d\n", adev->sdma.num_instances);
1792 for (i = 0; i < adev->sdma.num_instances; i++) {
1793 instance_offset = i * reg_count;
1794 drm_printf(p, "\nInstance:%d\n", i);
1795
1796 for (j = 0; j < reg_count; j++)
1797 drm_printf(p, "%-50s \t 0x%08x\n", sdma_reg_list_5_0[j].reg_name,
1798 adev->sdma.ip_dump[instance_offset + j]);
1799 }
1800 }
1801
sdma_v5_0_dump_ip_state(void * handle)1802 static void sdma_v5_0_dump_ip_state(void *handle)
1803 {
1804 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1805 int i, j;
1806 uint32_t instance_offset;
1807 uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_5_0);
1808
1809 if (!adev->sdma.ip_dump)
1810 return;
1811
1812 amdgpu_gfx_off_ctrl(adev, false);
1813 for (i = 0; i < adev->sdma.num_instances; i++) {
1814 instance_offset = i * reg_count;
1815 for (j = 0; j < reg_count; j++)
1816 adev->sdma.ip_dump[instance_offset + j] =
1817 RREG32(sdma_v5_0_get_reg_offset(adev, i,
1818 sdma_reg_list_5_0[j].reg_offset));
1819 }
1820 amdgpu_gfx_off_ctrl(adev, true);
1821 }
1822
1823 static const struct amd_ip_funcs sdma_v5_0_ip_funcs = {
1824 .name = "sdma_v5_0",
1825 .early_init = sdma_v5_0_early_init,
1826 .late_init = NULL,
1827 .sw_init = sdma_v5_0_sw_init,
1828 .sw_fini = sdma_v5_0_sw_fini,
1829 .hw_init = sdma_v5_0_hw_init,
1830 .hw_fini = sdma_v5_0_hw_fini,
1831 .suspend = sdma_v5_0_suspend,
1832 .resume = sdma_v5_0_resume,
1833 .is_idle = sdma_v5_0_is_idle,
1834 .wait_for_idle = sdma_v5_0_wait_for_idle,
1835 .soft_reset = sdma_v5_0_soft_reset,
1836 .set_clockgating_state = sdma_v5_0_set_clockgating_state,
1837 .set_powergating_state = sdma_v5_0_set_powergating_state,
1838 .get_clockgating_state = sdma_v5_0_get_clockgating_state,
1839 .dump_ip_state = sdma_v5_0_dump_ip_state,
1840 .print_ip_state = sdma_v5_0_print_ip_state,
1841 };
1842
1843 static const struct amdgpu_ring_funcs sdma_v5_0_ring_funcs = {
1844 .type = AMDGPU_RING_TYPE_SDMA,
1845 .align_mask = 0xf,
1846 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
1847 .support_64bit_ptrs = true,
1848 .secure_submission_supported = true,
1849 .get_rptr = sdma_v5_0_ring_get_rptr,
1850 .get_wptr = sdma_v5_0_ring_get_wptr,
1851 .set_wptr = sdma_v5_0_ring_set_wptr,
1852 .emit_frame_size =
1853 5 + /* sdma_v5_0_ring_init_cond_exec */
1854 6 + /* sdma_v5_0_ring_emit_hdp_flush */
1855 3 + /* hdp_invalidate */
1856 6 + /* sdma_v5_0_ring_emit_pipeline_sync */
1857 /* sdma_v5_0_ring_emit_vm_flush */
1858 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
1859 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 * 2 +
1860 10 + 10 + 10, /* sdma_v5_0_ring_emit_fence x3 for user fence, vm fence */
1861 .emit_ib_size = 5 + 7 + 6, /* sdma_v5_0_ring_emit_ib */
1862 .emit_ib = sdma_v5_0_ring_emit_ib,
1863 .emit_mem_sync = sdma_v5_0_ring_emit_mem_sync,
1864 .emit_fence = sdma_v5_0_ring_emit_fence,
1865 .emit_pipeline_sync = sdma_v5_0_ring_emit_pipeline_sync,
1866 .emit_vm_flush = sdma_v5_0_ring_emit_vm_flush,
1867 .emit_hdp_flush = sdma_v5_0_ring_emit_hdp_flush,
1868 .test_ring = sdma_v5_0_ring_test_ring,
1869 .test_ib = sdma_v5_0_ring_test_ib,
1870 .insert_nop = sdma_v5_0_ring_insert_nop,
1871 .pad_ib = sdma_v5_0_ring_pad_ib,
1872 .emit_wreg = sdma_v5_0_ring_emit_wreg,
1873 .emit_reg_wait = sdma_v5_0_ring_emit_reg_wait,
1874 .emit_reg_write_reg_wait = sdma_v5_0_ring_emit_reg_write_reg_wait,
1875 .init_cond_exec = sdma_v5_0_ring_init_cond_exec,
1876 .preempt_ib = sdma_v5_0_ring_preempt_ib,
1877 };
1878
sdma_v5_0_set_ring_funcs(struct amdgpu_device * adev)1879 static void sdma_v5_0_set_ring_funcs(struct amdgpu_device *adev)
1880 {
1881 int i;
1882
1883 for (i = 0; i < adev->sdma.num_instances; i++) {
1884 adev->sdma.instance[i].ring.funcs = &sdma_v5_0_ring_funcs;
1885 adev->sdma.instance[i].ring.me = i;
1886 }
1887 }
1888
1889 static const struct amdgpu_irq_src_funcs sdma_v5_0_trap_irq_funcs = {
1890 .set = sdma_v5_0_set_trap_irq_state,
1891 .process = sdma_v5_0_process_trap_irq,
1892 };
1893
1894 static const struct amdgpu_irq_src_funcs sdma_v5_0_illegal_inst_irq_funcs = {
1895 .process = sdma_v5_0_process_illegal_inst_irq,
1896 };
1897
sdma_v5_0_set_irq_funcs(struct amdgpu_device * adev)1898 static void sdma_v5_0_set_irq_funcs(struct amdgpu_device *adev)
1899 {
1900 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE0 +
1901 adev->sdma.num_instances;
1902 adev->sdma.trap_irq.funcs = &sdma_v5_0_trap_irq_funcs;
1903 adev->sdma.illegal_inst_irq.funcs = &sdma_v5_0_illegal_inst_irq_funcs;
1904 }
1905
1906 /**
1907 * sdma_v5_0_emit_copy_buffer - copy buffer using the sDMA engine
1908 *
1909 * @ib: indirect buffer to copy to
1910 * @src_offset: src GPU address
1911 * @dst_offset: dst GPU address
1912 * @byte_count: number of bytes to xfer
1913 * @copy_flags: copy flags for the buffers
1914 *
1915 * Copy GPU buffers using the DMA engine (NAVI10).
1916 * Used by the amdgpu ttm implementation to move pages if
1917 * registered as the asic copy callback.
1918 */
sdma_v5_0_emit_copy_buffer(struct amdgpu_ib * ib,uint64_t src_offset,uint64_t dst_offset,uint32_t byte_count,uint32_t copy_flags)1919 static void sdma_v5_0_emit_copy_buffer(struct amdgpu_ib *ib,
1920 uint64_t src_offset,
1921 uint64_t dst_offset,
1922 uint32_t byte_count,
1923 uint32_t copy_flags)
1924 {
1925 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1926 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) |
1927 SDMA_PKT_COPY_LINEAR_HEADER_TMZ((copy_flags & AMDGPU_COPY_FLAGS_TMZ) ? 1 : 0);
1928 ib->ptr[ib->length_dw++] = byte_count - 1;
1929 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1930 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1931 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1932 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1933 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1934 }
1935
1936 /**
1937 * sdma_v5_0_emit_fill_buffer - fill buffer using the sDMA engine
1938 *
1939 * @ib: indirect buffer to fill
1940 * @src_data: value to write to buffer
1941 * @dst_offset: dst GPU address
1942 * @byte_count: number of bytes to xfer
1943 *
1944 * Fill GPU buffers using the DMA engine (NAVI10).
1945 */
sdma_v5_0_emit_fill_buffer(struct amdgpu_ib * ib,uint32_t src_data,uint64_t dst_offset,uint32_t byte_count)1946 static void sdma_v5_0_emit_fill_buffer(struct amdgpu_ib *ib,
1947 uint32_t src_data,
1948 uint64_t dst_offset,
1949 uint32_t byte_count)
1950 {
1951 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL);
1952 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1953 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1954 ib->ptr[ib->length_dw++] = src_data;
1955 ib->ptr[ib->length_dw++] = byte_count - 1;
1956 }
1957
1958 static const struct amdgpu_buffer_funcs sdma_v5_0_buffer_funcs = {
1959 .copy_max_bytes = 0x400000,
1960 .copy_num_dw = 7,
1961 .emit_copy_buffer = sdma_v5_0_emit_copy_buffer,
1962
1963 .fill_max_bytes = 0x400000,
1964 .fill_num_dw = 5,
1965 .emit_fill_buffer = sdma_v5_0_emit_fill_buffer,
1966 };
1967
sdma_v5_0_set_buffer_funcs(struct amdgpu_device * adev)1968 static void sdma_v5_0_set_buffer_funcs(struct amdgpu_device *adev)
1969 {
1970 if (adev->mman.buffer_funcs == NULL) {
1971 adev->mman.buffer_funcs = &sdma_v5_0_buffer_funcs;
1972 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
1973 }
1974 }
1975
1976 static const struct amdgpu_vm_pte_funcs sdma_v5_0_vm_pte_funcs = {
1977 .copy_pte_num_dw = 7,
1978 .copy_pte = sdma_v5_0_vm_copy_pte,
1979 .write_pte = sdma_v5_0_vm_write_pte,
1980 .set_pte_pde = sdma_v5_0_vm_set_pte_pde,
1981 };
1982
sdma_v5_0_set_vm_pte_funcs(struct amdgpu_device * adev)1983 static void sdma_v5_0_set_vm_pte_funcs(struct amdgpu_device *adev)
1984 {
1985 unsigned i;
1986
1987 if (adev->vm_manager.vm_pte_funcs == NULL) {
1988 adev->vm_manager.vm_pte_funcs = &sdma_v5_0_vm_pte_funcs;
1989 for (i = 0; i < adev->sdma.num_instances; i++) {
1990 adev->vm_manager.vm_pte_scheds[i] =
1991 &adev->sdma.instance[i].ring.sched;
1992 }
1993 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;
1994 }
1995 }
1996
1997 const struct amdgpu_ip_block_version sdma_v5_0_ip_block = {
1998 .type = AMD_IP_BLOCK_TYPE_SDMA,
1999 .major = 5,
2000 .minor = 0,
2001 .rev = 0,
2002 .funcs = &sdma_v5_0_ip_funcs,
2003 };
2004