1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (C) 2021, Intel Corporation. */
3
4 #ifndef _ICE_PTP_HW_H_
5 #define _ICE_PTP_HW_H_
6 #include <linux/dpll.h>
7
8 enum ice_ptp_tmr_cmd {
9 ICE_PTP_INIT_TIME,
10 ICE_PTP_INIT_INCVAL,
11 ICE_PTP_ADJ_TIME,
12 ICE_PTP_ADJ_TIME_AT_TIME,
13 ICE_PTP_READ_TIME,
14 ICE_PTP_NOP,
15 };
16
17 enum ice_ptp_serdes {
18 ICE_PTP_SERDES_1G,
19 ICE_PTP_SERDES_10G,
20 ICE_PTP_SERDES_25G,
21 ICE_PTP_SERDES_40G,
22 ICE_PTP_SERDES_50G,
23 ICE_PTP_SERDES_100G
24 };
25
26 enum ice_ptp_link_spd {
27 ICE_PTP_LNK_SPD_1G,
28 ICE_PTP_LNK_SPD_10G,
29 ICE_PTP_LNK_SPD_25G,
30 ICE_PTP_LNK_SPD_25G_RS,
31 ICE_PTP_LNK_SPD_40G,
32 ICE_PTP_LNK_SPD_50G,
33 ICE_PTP_LNK_SPD_50G_RS,
34 ICE_PTP_LNK_SPD_100G_RS,
35 NUM_ICE_PTP_LNK_SPD /* Must be last */
36 };
37
38 enum ice_ptp_fec_mode {
39 ICE_PTP_FEC_MODE_NONE,
40 ICE_PTP_FEC_MODE_CLAUSE74,
41 ICE_PTP_FEC_MODE_RS_FEC
42 };
43
44 enum eth56g_res_type {
45 ETH56G_PHY_REG_PTP,
46 ETH56G_PHY_MEM_PTP,
47 ETH56G_PHY_REG_XPCS,
48 ETH56G_PHY_REG_MAC,
49 ETH56G_PHY_REG_GPCS,
50 NUM_ETH56G_PHY_RES
51 };
52
53 enum ice_eth56g_link_spd {
54 ICE_ETH56G_LNK_SPD_1G,
55 ICE_ETH56G_LNK_SPD_2_5G,
56 ICE_ETH56G_LNK_SPD_10G,
57 ICE_ETH56G_LNK_SPD_25G,
58 ICE_ETH56G_LNK_SPD_40G,
59 ICE_ETH56G_LNK_SPD_50G,
60 ICE_ETH56G_LNK_SPD_50G2,
61 ICE_ETH56G_LNK_SPD_100G,
62 ICE_ETH56G_LNK_SPD_100G2,
63 NUM_ICE_ETH56G_LNK_SPD /* Must be last */
64 };
65
66 /**
67 * struct ice_phy_reg_info_eth56g - ETH56G PHY register parameters
68 * @base: base address for each PHY block
69 * @step: step between PHY lanes
70 *
71 * Characteristic information for the various PHY register parameters in the
72 * ETH56G devices
73 */
74 struct ice_phy_reg_info_eth56g {
75 u32 base[NUM_ETH56G_PHY_RES];
76 u32 step;
77 };
78
79 /**
80 * struct ice_time_ref_info_e82x
81 * @pll_freq: Frequency of PLL that drives timer ticks in Hz
82 * @nominal_incval: increment to generate nanoseconds in GLTSYN_TIME_L
83 * @pps_delay: propagation delay of the PPS output signal
84 *
85 * Characteristic information for the various TIME_REF sources possible in the
86 * E822 devices
87 */
88 struct ice_time_ref_info_e82x {
89 u64 pll_freq;
90 u64 nominal_incval;
91 u8 pps_delay;
92 };
93
94 /**
95 * struct ice_vernier_info_e82x
96 * @tx_par_clk: Frequency used to calculate P_REG_PAR_TX_TUS
97 * @rx_par_clk: Frequency used to calculate P_REG_PAR_RX_TUS
98 * @tx_pcs_clk: Frequency used to calculate P_REG_PCS_TX_TUS
99 * @rx_pcs_clk: Frequency used to calculate P_REG_PCS_RX_TUS
100 * @tx_desk_rsgb_par: Frequency used to calculate P_REG_DESK_PAR_TX_TUS
101 * @rx_desk_rsgb_par: Frequency used to calculate P_REG_DESK_PAR_RX_TUS
102 * @tx_desk_rsgb_pcs: Frequency used to calculate P_REG_DESK_PCS_TX_TUS
103 * @rx_desk_rsgb_pcs: Frequency used to calculate P_REG_DESK_PCS_RX_TUS
104 * @tx_fixed_delay: Fixed Tx latency measured in 1/100th nanoseconds
105 * @pmd_adj_divisor: Divisor used to calculate PDM alignment adjustment
106 * @rx_fixed_delay: Fixed Rx latency measured in 1/100th nanoseconds
107 *
108 * Table of constants used during as part of the Vernier calibration of the Tx
109 * and Rx timestamps. This includes frequency values used to compute TUs per
110 * PAR/PCS clock cycle, and static delay values measured during hardware
111 * design.
112 *
113 * Note that some values are not used for all link speeds, and the
114 * P_REG_DESK_PAR* registers may represent different clock markers at
115 * different link speeds, either the deskew marker for multi-lane link speeds
116 * or the Reed Solomon gearbox marker for RS-FEC.
117 */
118 struct ice_vernier_info_e82x {
119 u32 tx_par_clk;
120 u32 rx_par_clk;
121 u32 tx_pcs_clk;
122 u32 rx_pcs_clk;
123 u32 tx_desk_rsgb_par;
124 u32 rx_desk_rsgb_par;
125 u32 tx_desk_rsgb_pcs;
126 u32 rx_desk_rsgb_pcs;
127 u32 tx_fixed_delay;
128 u32 pmd_adj_divisor;
129 u32 rx_fixed_delay;
130 };
131
132 #define ICE_ETH56G_MAC_CFG_RX_OFFSET_INT GENMASK(19, 9)
133 #define ICE_ETH56G_MAC_CFG_RX_OFFSET_FRAC GENMASK(8, 0)
134 #define ICE_ETH56G_MAC_CFG_FRAC_W 9
135 /**
136 * struct ice_eth56g_mac_reg_cfg - MAC config values for specific PTP registers
137 * @tx_mode: Tx timestamp compensation mode
138 * @tx_mk_dly: Tx timestamp marker start strobe delay
139 * @tx_cw_dly: Tx timestamp codeword start strobe delay
140 * @rx_mode: Rx timestamp compensation mode
141 * @rx_mk_dly: Rx timestamp marker start strobe delay
142 * @rx_cw_dly: Rx timestamp codeword start strobe delay
143 * @blks_per_clk: number of blocks transferred per clock cycle
144 * @blktime: block time, fixed point
145 * @mktime: marker time, fixed point
146 * @tx_offset: total Tx offset, fixed point
147 * @rx_offset: total Rx offset, contains value for bitslip/deskew, fixed point
148 *
149 * All fixed point registers except Rx offset are 23 bit unsigned ints with
150 * a 9 bit fractional.
151 * Rx offset is 11 bit unsigned int with a 9 bit fractional.
152 */
153 struct ice_eth56g_mac_reg_cfg {
154 struct {
155 u8 def;
156 u8 rs;
157 } tx_mode;
158 u8 tx_mk_dly;
159 struct {
160 u8 def;
161 u8 onestep;
162 } tx_cw_dly;
163 struct {
164 u8 def;
165 u8 rs;
166 } rx_mode;
167 struct {
168 u8 def;
169 u8 rs;
170 } rx_mk_dly;
171 struct {
172 u8 def;
173 u8 rs;
174 } rx_cw_dly;
175 u8 blks_per_clk;
176 u16 blktime;
177 u16 mktime;
178 struct {
179 u32 serdes;
180 u32 no_fec;
181 u32 fc;
182 u32 rs;
183 u32 sfd;
184 u32 onestep;
185 } tx_offset;
186 struct {
187 u32 serdes;
188 u32 no_fec;
189 u32 fc;
190 u32 rs;
191 u32 sfd;
192 u32 bs_ds;
193 } rx_offset;
194 };
195
196 extern
197 const struct ice_eth56g_mac_reg_cfg eth56g_mac_cfg[NUM_ICE_ETH56G_LNK_SPD];
198
199 /**
200 * struct ice_cgu_pll_params_e82x - E82X CGU parameters
201 * @refclk_pre_div: Reference clock pre-divisor
202 * @feedback_div: Feedback divisor
203 * @frac_n_div: Fractional divisor
204 * @post_pll_div: Post PLL divisor
205 *
206 * Clock Generation Unit parameters used to program the PLL based on the
207 * selected TIME_REF frequency.
208 */
209 struct ice_cgu_pll_params_e82x {
210 u32 refclk_pre_div;
211 u32 feedback_div;
212 u32 frac_n_div;
213 u32 post_pll_div;
214 };
215
216 #define E810C_QSFP_C827_0_HANDLE 2
217 #define E810C_QSFP_C827_1_HANDLE 3
218 enum ice_e810_c827_idx {
219 C827_0,
220 C827_1
221 };
222
223 enum ice_phy_rclk_pins {
224 ICE_RCLKA_PIN = 0, /* SCL pin */
225 ICE_RCLKB_PIN, /* SDA pin */
226 };
227
228 #define ICE_E810_RCLK_PINS_NUM (ICE_RCLKB_PIN + 1)
229 #define ICE_E82X_RCLK_PINS_NUM (ICE_RCLKA_PIN + 1)
230 #define E810T_CGU_INPUT_C827(_phy, _pin) ((_phy) * ICE_E810_RCLK_PINS_NUM + \
231 (_pin) + ZL_REF1P)
232
233 enum ice_zl_cgu_in_pins {
234 ZL_REF0P = 0,
235 ZL_REF0N,
236 ZL_REF1P,
237 ZL_REF1N,
238 ZL_REF2P,
239 ZL_REF2N,
240 ZL_REF3P,
241 ZL_REF3N,
242 ZL_REF4P,
243 ZL_REF4N,
244 NUM_ZL_CGU_INPUT_PINS
245 };
246
247 enum ice_zl_cgu_out_pins {
248 ZL_OUT0 = 0,
249 ZL_OUT1,
250 ZL_OUT2,
251 ZL_OUT3,
252 ZL_OUT4,
253 ZL_OUT5,
254 ZL_OUT6,
255 NUM_ZL_CGU_OUTPUT_PINS
256 };
257
258 enum ice_si_cgu_in_pins {
259 SI_REF0P = 0,
260 SI_REF0N,
261 SI_REF1P,
262 SI_REF1N,
263 SI_REF2P,
264 SI_REF2N,
265 SI_REF3,
266 SI_REF4,
267 NUM_SI_CGU_INPUT_PINS
268 };
269
270 enum ice_si_cgu_out_pins {
271 SI_OUT0 = 0,
272 SI_OUT1,
273 SI_OUT2,
274 SI_OUT3,
275 SI_OUT4,
276 NUM_SI_CGU_OUTPUT_PINS
277 };
278
279 struct ice_cgu_pin_desc {
280 char *name;
281 u8 index;
282 enum dpll_pin_type type;
283 u32 freq_supp_num;
284 struct dpll_pin_frequency *freq_supp;
285 };
286
287 extern const struct
288 ice_cgu_pll_params_e82x e822_cgu_params[NUM_ICE_TIME_REF_FREQ];
289
290 /**
291 * struct ice_cgu_pll_params_e825c - E825C CGU parameters
292 * @tspll_ck_refclkfreq: tspll_ck_refclkfreq selection
293 * @tspll_ndivratio: ndiv ratio that goes directly to the pll
294 * @tspll_fbdiv_intgr: TS PLL integer feedback divide
295 * @tspll_fbdiv_frac: TS PLL fractional feedback divide
296 * @ref1588_ck_div: clock divider for tspll ref
297 *
298 * Clock Generation Unit parameters used to program the PLL based on the
299 * selected TIME_REF/TCXO frequency.
300 */
301 struct ice_cgu_pll_params_e825c {
302 u32 tspll_ck_refclkfreq;
303 u32 tspll_ndivratio;
304 u32 tspll_fbdiv_intgr;
305 u32 tspll_fbdiv_frac;
306 u32 ref1588_ck_div;
307 };
308
309 extern const struct
310 ice_cgu_pll_params_e825c e825c_cgu_params[NUM_ICE_TIME_REF_FREQ];
311
312 #define E810C_QSFP_C827_0_HANDLE 2
313 #define E810C_QSFP_C827_1_HANDLE 3
314
315 /* Table of constants related to possible ETH56G PHY resources */
316 extern const struct ice_phy_reg_info_eth56g eth56g_phy_res[NUM_ETH56G_PHY_RES];
317
318 /* Table of constants related to possible TIME_REF sources */
319 extern const struct ice_time_ref_info_e82x e822_time_ref[NUM_ICE_TIME_REF_FREQ];
320
321 /* Table of constants for Vernier calibration on E822 */
322 extern const struct ice_vernier_info_e82x e822_vernier[NUM_ICE_PTP_LNK_SPD];
323
324 /* Increment value to generate nanoseconds in the GLTSYN_TIME_L register for
325 * the E810 devices. Based off of a PLL with an 812.5 MHz frequency.
326 */
327 #define ICE_E810_PLL_FREQ 812500000
328 #define ICE_PTP_NOMINAL_INCVAL_E810 0x13b13b13bULL
329 #define E810_OUT_PROP_DELAY_NS 1
330
331 /* Device agnostic functions */
332 u8 ice_get_ptp_src_clock_index(struct ice_hw *hw);
333 bool ice_ptp_lock(struct ice_hw *hw);
334 void ice_ptp_unlock(struct ice_hw *hw);
335 void ice_ptp_src_cmd(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd);
336 int ice_ptp_init_time(struct ice_hw *hw, u64 time);
337 int ice_ptp_write_incval(struct ice_hw *hw, u64 incval);
338 int ice_ptp_write_incval_locked(struct ice_hw *hw, u64 incval);
339 int ice_ptp_adj_clock(struct ice_hw *hw, s32 adj);
340 int ice_ptp_clear_phy_offset_ready_e82x(struct ice_hw *hw);
341 int ice_read_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx, u64 *tstamp);
342 int ice_clear_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx);
343 void ice_ptp_reset_ts_memory(struct ice_hw *hw);
344 int ice_ptp_init_phc(struct ice_hw *hw);
345 void ice_ptp_init_hw(struct ice_hw *hw);
346 int ice_get_phy_tx_tstamp_ready(struct ice_hw *hw, u8 block, u64 *tstamp_ready);
347 int ice_ptp_one_port_cmd(struct ice_hw *hw, u8 configured_port,
348 enum ice_ptp_tmr_cmd configured_cmd);
349
350 /* E822 family functions */
351 int ice_read_quad_reg_e82x(struct ice_hw *hw, u8 quad, u16 offset, u32 *val);
352 int ice_write_quad_reg_e82x(struct ice_hw *hw, u8 quad, u16 offset, u32 val);
353 void ice_ptp_reset_ts_memory_quad_e82x(struct ice_hw *hw, u8 quad);
354
355 /**
356 * ice_e82x_time_ref - Get the current TIME_REF from capabilities
357 * @hw: pointer to the HW structure
358 *
359 * Returns the current TIME_REF from the capabilities structure.
360 */
ice_e82x_time_ref(struct ice_hw * hw)361 static inline enum ice_time_ref_freq ice_e82x_time_ref(struct ice_hw *hw)
362 {
363 return hw->func_caps.ts_func_info.time_ref;
364 }
365
366 /**
367 * ice_set_e82x_time_ref - Set new TIME_REF
368 * @hw: pointer to the HW structure
369 * @time_ref: new TIME_REF to set
370 *
371 * Update the TIME_REF in the capabilities structure in response to some
372 * change, such as an update to the CGU registers.
373 */
374 static inline void
ice_set_e82x_time_ref(struct ice_hw * hw,enum ice_time_ref_freq time_ref)375 ice_set_e82x_time_ref(struct ice_hw *hw, enum ice_time_ref_freq time_ref)
376 {
377 hw->func_caps.ts_func_info.time_ref = time_ref;
378 }
379
ice_e82x_pll_freq(enum ice_time_ref_freq time_ref)380 static inline u64 ice_e82x_pll_freq(enum ice_time_ref_freq time_ref)
381 {
382 return e822_time_ref[time_ref].pll_freq;
383 }
384
ice_e82x_nominal_incval(enum ice_time_ref_freq time_ref)385 static inline u64 ice_e82x_nominal_incval(enum ice_time_ref_freq time_ref)
386 {
387 return e822_time_ref[time_ref].nominal_incval;
388 }
389
ice_e82x_pps_delay(enum ice_time_ref_freq time_ref)390 static inline u64 ice_e82x_pps_delay(enum ice_time_ref_freq time_ref)
391 {
392 return e822_time_ref[time_ref].pps_delay;
393 }
394
395 /* E822 Vernier calibration functions */
396 int ice_stop_phy_timer_e82x(struct ice_hw *hw, u8 port, bool soft_reset);
397 int ice_start_phy_timer_e82x(struct ice_hw *hw, u8 port);
398 int ice_phy_cfg_tx_offset_e82x(struct ice_hw *hw, u8 port);
399 int ice_phy_cfg_rx_offset_e82x(struct ice_hw *hw, u8 port);
400 int ice_phy_cfg_intr_e82x(struct ice_hw *hw, u8 quad, bool ena, u8 threshold);
401
402 /* E810 family functions */
403 int ice_read_sma_ctrl_e810t(struct ice_hw *hw, u8 *data);
404 int ice_write_sma_ctrl_e810t(struct ice_hw *hw, u8 data);
405 int ice_read_pca9575_reg_e810t(struct ice_hw *hw, u8 offset, u8 *data);
406 bool ice_is_pca9575_present(struct ice_hw *hw);
407 int ice_cgu_get_num_pins(struct ice_hw *hw, bool input);
408 enum dpll_pin_type ice_cgu_get_pin_type(struct ice_hw *hw, u8 pin, bool input);
409 struct dpll_pin_frequency *
410 ice_cgu_get_pin_freq_supp(struct ice_hw *hw, u8 pin, bool input, u8 *num);
411 const char *ice_cgu_get_pin_name(struct ice_hw *hw, u8 pin, bool input);
412 int ice_get_cgu_state(struct ice_hw *hw, u8 dpll_idx,
413 enum dpll_lock_status last_dpll_state, u8 *pin,
414 u8 *ref_state, u8 *eec_mode, s64 *phase_offset,
415 enum dpll_lock_status *dpll_state);
416 int ice_get_cgu_rclk_pin_info(struct ice_hw *hw, u8 *base_idx, u8 *pin_num);
417 int ice_cgu_get_output_pin_state_caps(struct ice_hw *hw, u8 pin_id,
418 unsigned long *caps);
419
420 /* ETH56G family functions */
421 int ice_ptp_read_tx_hwtstamp_status_eth56g(struct ice_hw *hw, u32 *ts_status);
422 int ice_stop_phy_timer_eth56g(struct ice_hw *hw, u8 port, bool soft_reset);
423 int ice_start_phy_timer_eth56g(struct ice_hw *hw, u8 port);
424 int ice_phy_cfg_tx_offset_eth56g(struct ice_hw *hw, u8 port);
425 int ice_phy_cfg_rx_offset_eth56g(struct ice_hw *hw, u8 port);
426 int ice_phy_cfg_intr_eth56g(struct ice_hw *hw, u8 port, bool ena, u8 threshold);
427 int ice_phy_cfg_ptp_1step_eth56g(struct ice_hw *hw, u8 port);
428
429 #define ICE_ETH56G_NOMINAL_INCVAL 0x140000000ULL
430 #define ICE_ETH56G_NOMINAL_PCS_REF_TUS 0x100000000ULL
431 #define ICE_ETH56G_NOMINAL_PCS_REF_INC 0x300000000ULL
432 #define ICE_ETH56G_NOMINAL_THRESH4 0x7777
433 #define ICE_ETH56G_NOMINAL_TX_THRESH 0x6
434
435 /**
436 * ice_get_base_incval - Get base clock increment value
437 * @hw: pointer to the HW struct
438 *
439 * Return: base clock increment value for supported PHYs, 0 otherwise
440 */
ice_get_base_incval(struct ice_hw * hw)441 static inline u64 ice_get_base_incval(struct ice_hw *hw)
442 {
443 switch (hw->ptp.phy_model) {
444 case ICE_PHY_ETH56G:
445 return ICE_ETH56G_NOMINAL_INCVAL;
446 case ICE_PHY_E810:
447 return ICE_PTP_NOMINAL_INCVAL_E810;
448 case ICE_PHY_E82X:
449 return ice_e82x_nominal_incval(ice_e82x_time_ref(hw));
450 default:
451 return 0;
452 }
453 }
454
455 #define PFTSYN_SEM_BYTES 4
456
457 #define ICE_PTP_CLOCK_INDEX_0 0x00
458 #define ICE_PTP_CLOCK_INDEX_1 0x01
459
460 /* PHY timer commands */
461 #define SEL_CPK_SRC 8
462 #define SEL_PHY_SRC 3
463
464 /* Time Sync command Definitions */
465 #define GLTSYN_CMD_INIT_TIME BIT(0)
466 #define GLTSYN_CMD_INIT_INCVAL BIT(1)
467 #define GLTSYN_CMD_INIT_TIME_INCVAL (BIT(0) | BIT(1))
468 #define GLTSYN_CMD_ADJ_TIME BIT(2)
469 #define GLTSYN_CMD_ADJ_INIT_TIME (BIT(2) | BIT(3))
470 #define GLTSYN_CMD_READ_TIME BIT(7)
471
472 /* PHY port Time Sync command definitions */
473 #define PHY_CMD_INIT_TIME BIT(0)
474 #define PHY_CMD_INIT_INCVAL BIT(1)
475 #define PHY_CMD_ADJ_TIME (BIT(0) | BIT(1))
476 #define PHY_CMD_ADJ_TIME_AT_TIME (BIT(0) | BIT(2))
477 #define PHY_CMD_READ_TIME (BIT(0) | BIT(1) | BIT(2))
478
479 #define TS_CMD_MASK_E810 0xFF
480 #define TS_CMD_MASK 0xF
481 #define SYNC_EXEC_CMD 0x3
482 #define TS_CMD_RX_TYPE ICE_M(0x18, 0x4)
483
484 /* Macros to derive port low and high addresses on both quads */
485 #define P_Q0_L(a, p) ((((a) + (0x2000 * (p)))) & 0xFFFF)
486 #define P_Q0_H(a, p) ((((a) + (0x2000 * (p)))) >> 16)
487 #define P_Q1_L(a, p) ((((a) - (0x2000 * ((p) - ICE_PORTS_PER_QUAD)))) & 0xFFFF)
488 #define P_Q1_H(a, p) ((((a) - (0x2000 * ((p) - ICE_PORTS_PER_QUAD)))) >> 16)
489
490 /* PHY QUAD register base addresses */
491 #define Q_0_BASE 0x94000
492 #define Q_1_BASE 0x114000
493
494 /* Timestamp memory reset registers */
495 #define Q_REG_TS_CTRL 0x618
496 #define Q_REG_TS_CTRL_S 0
497 #define Q_REG_TS_CTRL_M BIT(0)
498
499 /* Timestamp availability status registers */
500 #define Q_REG_TX_MEMORY_STATUS_L 0xCF0
501 #define Q_REG_TX_MEMORY_STATUS_U 0xCF4
502
503 /* Tx FIFO status registers */
504 #define Q_REG_FIFO23_STATUS 0xCF8
505 #define Q_REG_FIFO01_STATUS 0xCFC
506 #define Q_REG_FIFO02_S 0
507 #define Q_REG_FIFO02_M ICE_M(0x3FF, 0)
508 #define Q_REG_FIFO13_S 10
509 #define Q_REG_FIFO13_M ICE_M(0x3FF, 10)
510
511 /* Interrupt control Config registers */
512 #define Q_REG_TX_MEM_GBL_CFG 0xC08
513 #define Q_REG_TX_MEM_GBL_CFG_LANE_TYPE_S 0
514 #define Q_REG_TX_MEM_GBL_CFG_LANE_TYPE_M BIT(0)
515 #define Q_REG_TX_MEM_GBL_CFG_TX_TYPE_M ICE_M(0xFF, 1)
516 #define Q_REG_TX_MEM_GBL_CFG_INTR_THR_M ICE_M(0x3F, 9)
517 #define Q_REG_TX_MEM_GBL_CFG_INTR_ENA_M BIT(15)
518
519 /* Tx Timestamp data registers */
520 #define Q_REG_TX_MEMORY_BANK_START 0xA00
521
522 /* PHY port register base addresses */
523 #define P_0_BASE 0x80000
524 #define P_4_BASE 0x106000
525
526 /* Timestamp init registers */
527 #define P_REG_RX_TIMER_INC_PRE_L 0x46C
528 #define P_REG_RX_TIMER_INC_PRE_U 0x470
529 #define P_REG_TX_TIMER_INC_PRE_L 0x44C
530 #define P_REG_TX_TIMER_INC_PRE_U 0x450
531
532 /* Timestamp match and adjust target registers */
533 #define P_REG_RX_TIMER_CNT_ADJ_L 0x474
534 #define P_REG_RX_TIMER_CNT_ADJ_U 0x478
535 #define P_REG_TX_TIMER_CNT_ADJ_L 0x454
536 #define P_REG_TX_TIMER_CNT_ADJ_U 0x458
537
538 /* Timestamp capture registers */
539 #define P_REG_RX_CAPTURE_L 0x4D8
540 #define P_REG_RX_CAPTURE_U 0x4DC
541 #define P_REG_TX_CAPTURE_L 0x4B4
542 #define P_REG_TX_CAPTURE_U 0x4B8
543
544 /* Timestamp PHY incval registers */
545 #define P_REG_TIMETUS_L 0x410
546 #define P_REG_TIMETUS_U 0x414
547
548 #define P_REG_40B_LOW_M GENMASK(7, 0)
549 #define P_REG_40B_HIGH_S 8
550
551 /* PHY window length registers */
552 #define P_REG_WL 0x40C
553
554 #define PTP_VERNIER_WL 0x111ed
555
556 /* PHY start registers */
557 #define P_REG_PS 0x408
558 #define P_REG_PS_START_S 0
559 #define P_REG_PS_START_M BIT(0)
560 #define P_REG_PS_BYPASS_MODE_S 1
561 #define P_REG_PS_BYPASS_MODE_M BIT(1)
562 #define P_REG_PS_ENA_CLK_S 2
563 #define P_REG_PS_ENA_CLK_M BIT(2)
564 #define P_REG_PS_LOAD_OFFSET_S 3
565 #define P_REG_PS_LOAD_OFFSET_M BIT(3)
566 #define P_REG_PS_SFT_RESET_S 11
567 #define P_REG_PS_SFT_RESET_M BIT(11)
568
569 /* PHY offset valid registers */
570 #define P_REG_TX_OV_STATUS 0x4D4
571 #define P_REG_TX_OV_STATUS_OV_S 0
572 #define P_REG_TX_OV_STATUS_OV_M BIT(0)
573 #define P_REG_RX_OV_STATUS 0x4F8
574 #define P_REG_RX_OV_STATUS_OV_S 0
575 #define P_REG_RX_OV_STATUS_OV_M BIT(0)
576
577 /* PHY offset ready registers */
578 #define P_REG_TX_OR 0x45C
579 #define P_REG_RX_OR 0x47C
580
581 /* PHY total offset registers */
582 #define P_REG_TOTAL_RX_OFFSET_L 0x460
583 #define P_REG_TOTAL_RX_OFFSET_U 0x464
584 #define P_REG_TOTAL_TX_OFFSET_L 0x440
585 #define P_REG_TOTAL_TX_OFFSET_U 0x444
586
587 /* Timestamp PAR/PCS registers */
588 #define P_REG_UIX66_10G_40G_L 0x480
589 #define P_REG_UIX66_10G_40G_U 0x484
590 #define P_REG_UIX66_25G_100G_L 0x488
591 #define P_REG_UIX66_25G_100G_U 0x48C
592 #define P_REG_DESK_PAR_RX_TUS_L 0x490
593 #define P_REG_DESK_PAR_RX_TUS_U 0x494
594 #define P_REG_DESK_PAR_TX_TUS_L 0x498
595 #define P_REG_DESK_PAR_TX_TUS_U 0x49C
596 #define P_REG_DESK_PCS_RX_TUS_L 0x4A0
597 #define P_REG_DESK_PCS_RX_TUS_U 0x4A4
598 #define P_REG_DESK_PCS_TX_TUS_L 0x4A8
599 #define P_REG_DESK_PCS_TX_TUS_U 0x4AC
600 #define P_REG_PAR_RX_TUS_L 0x420
601 #define P_REG_PAR_RX_TUS_U 0x424
602 #define P_REG_PAR_TX_TUS_L 0x428
603 #define P_REG_PAR_TX_TUS_U 0x42C
604 #define P_REG_PCS_RX_TUS_L 0x430
605 #define P_REG_PCS_RX_TUS_U 0x434
606 #define P_REG_PCS_TX_TUS_L 0x438
607 #define P_REG_PCS_TX_TUS_U 0x43C
608 #define P_REG_PAR_RX_TIME_L 0x4F0
609 #define P_REG_PAR_RX_TIME_U 0x4F4
610 #define P_REG_PAR_TX_TIME_L 0x4CC
611 #define P_REG_PAR_TX_TIME_U 0x4D0
612 #define P_REG_PAR_PCS_RX_OFFSET_L 0x4E8
613 #define P_REG_PAR_PCS_RX_OFFSET_U 0x4EC
614 #define P_REG_PAR_PCS_TX_OFFSET_L 0x4C4
615 #define P_REG_PAR_PCS_TX_OFFSET_U 0x4C8
616 #define P_REG_LINK_SPEED 0x4FC
617 #define P_REG_LINK_SPEED_SERDES_S 0
618 #define P_REG_LINK_SPEED_SERDES_M ICE_M(0x7, 0)
619 #define P_REG_LINK_SPEED_FEC_MODE_S 3
620 #define P_REG_LINK_SPEED_FEC_MODE_M ICE_M(0x3, 3)
621 #define P_REG_LINK_SPEED_FEC_MODE(reg) \
622 (((reg) & P_REG_LINK_SPEED_FEC_MODE_M) >> \
623 P_REG_LINK_SPEED_FEC_MODE_S)
624
625 /* PHY timestamp related registers */
626 #define P_REG_PMD_ALIGNMENT 0x0FC
627 #define P_REG_RX_80_TO_160_CNT 0x6FC
628 #define P_REG_RX_80_TO_160_CNT_RXCYC_S 0
629 #define P_REG_RX_80_TO_160_CNT_RXCYC_M BIT(0)
630 #define P_REG_RX_40_TO_160_CNT 0x8FC
631 #define P_REG_RX_40_TO_160_CNT_RXCYC_S 0
632 #define P_REG_RX_40_TO_160_CNT_RXCYC_M ICE_M(0x3, 0)
633
634 /* Rx FIFO status registers */
635 #define P_REG_RX_OV_FS 0x4F8
636 #define P_REG_RX_OV_FS_FIFO_STATUS_S 2
637 #define P_REG_RX_OV_FS_FIFO_STATUS_M ICE_M(0x3FF, 2)
638
639 /* Timestamp command registers */
640 #define P_REG_TX_TMR_CMD 0x448
641 #define P_REG_RX_TMR_CMD 0x468
642
643 /* E810 timesync enable register */
644 #define ETH_GLTSYN_ENA(_i) (0x03000348 + ((_i) * 4))
645
646 /* E810 shadow init time registers */
647 #define ETH_GLTSYN_SHTIME_0(i) (0x03000368 + ((i) * 32))
648 #define ETH_GLTSYN_SHTIME_L(i) (0x0300036C + ((i) * 32))
649
650 /* E810 shadow time adjust registers */
651 #define ETH_GLTSYN_SHADJ_L(_i) (0x03000378 + ((_i) * 32))
652 #define ETH_GLTSYN_SHADJ_H(_i) (0x0300037C + ((_i) * 32))
653
654 /* E810 timer command register */
655 #define E810_ETH_GLTSYN_CMD 0x03000344
656
657 /* Source timer incval macros */
658 #define INCVAL_HIGH_M 0xFF
659
660 /* Timestamp block macros */
661 #define TS_VALID BIT(0)
662 #define TS_LOW_M 0xFFFFFFFF
663 #define TS_HIGH_M 0xFF
664 #define TS_HIGH_S 32
665
666 #define TS_PHY_LOW_M 0xFF
667 #define TS_PHY_HIGH_M 0xFFFFFFFF
668 #define TS_PHY_HIGH_S 8
669
670 #define BYTES_PER_IDX_ADDR_L_U 8
671 #define BYTES_PER_IDX_ADDR_L 4
672
673 /* Tx timestamp low latency read definitions */
674 #define TS_LL_READ_RETRIES 200
675 #define TS_LL_READ_TS_HIGH GENMASK(23, 16)
676 #define TS_LL_READ_TS_IDX GENMASK(29, 24)
677 #define TS_LL_READ_TS_INTR BIT(30)
678 #define TS_LL_READ_TS BIT(31)
679
680 /* Internal PHY timestamp address */
681 #define TS_L(a, idx) ((a) + ((idx) * BYTES_PER_IDX_ADDR_L_U))
682 #define TS_H(a, idx) ((a) + ((idx) * BYTES_PER_IDX_ADDR_L_U + \
683 BYTES_PER_IDX_ADDR_L))
684
685 /* External PHY timestamp address */
686 #define TS_EXT(a, port, idx) ((a) + (0x1000 * (port)) + \
687 ((idx) * BYTES_PER_IDX_ADDR_L_U))
688
689 #define LOW_TX_MEMORY_BANK_START 0x03090000
690 #define HIGH_TX_MEMORY_BANK_START 0x03090004
691
692 /* E810T SMA controller pin control */
693 #define ICE_SMA1_DIR_EN_E810T BIT(4)
694 #define ICE_SMA1_TX_EN_E810T BIT(5)
695 #define ICE_SMA2_UFL2_RX_DIS_E810T BIT(3)
696 #define ICE_SMA2_DIR_EN_E810T BIT(6)
697 #define ICE_SMA2_TX_EN_E810T BIT(7)
698
699 #define ICE_SMA1_MASK_E810T (ICE_SMA1_DIR_EN_E810T | \
700 ICE_SMA1_TX_EN_E810T)
701 #define ICE_SMA2_MASK_E810T (ICE_SMA2_UFL2_RX_DIS_E810T | \
702 ICE_SMA2_DIR_EN_E810T | \
703 ICE_SMA2_TX_EN_E810T)
704 #define ICE_ALL_SMA_MASK_E810T (ICE_SMA1_MASK_E810T | \
705 ICE_SMA2_MASK_E810T)
706
707 #define ICE_SMA_MIN_BIT_E810T 3
708 #define ICE_SMA_MAX_BIT_E810T 7
709 #define ICE_PCA9575_P1_OFFSET 8
710
711 /* E810T PCA9575 IO controller registers */
712 #define ICE_PCA9575_P0_IN 0x0
713
714 /* E810T PCA9575 IO controller pin control */
715 #define ICE_E810T_P0_GNSS_PRSNT_N BIT(4)
716
717 /* ETH56G PHY register addresses */
718 /* Timestamp PHY incval registers */
719 #define PHY_REG_TIMETUS_L 0x8
720 #define PHY_REG_TIMETUS_U 0xC
721
722 /* Timestamp PCS registers */
723 #define PHY_PCS_REF_TUS_L 0x18
724 #define PHY_PCS_REF_TUS_U 0x1C
725
726 /* Timestamp PCS ref incval registers */
727 #define PHY_PCS_REF_INC_L 0x20
728 #define PHY_PCS_REF_INC_U 0x24
729
730 /* Timestamp init registers */
731 #define PHY_REG_RX_TIMER_INC_PRE_L 0x64
732 #define PHY_REG_RX_TIMER_INC_PRE_U 0x68
733 #define PHY_REG_TX_TIMER_INC_PRE_L 0x44
734 #define PHY_REG_TX_TIMER_INC_PRE_U 0x48
735
736 /* Timestamp match and adjust target registers */
737 #define PHY_REG_RX_TIMER_CNT_ADJ_L 0x6C
738 #define PHY_REG_RX_TIMER_CNT_ADJ_U 0x70
739 #define PHY_REG_TX_TIMER_CNT_ADJ_L 0x4C
740 #define PHY_REG_TX_TIMER_CNT_ADJ_U 0x50
741
742 /* Timestamp command registers */
743 #define PHY_REG_TX_TMR_CMD 0x40
744 #define PHY_REG_RX_TMR_CMD 0x60
745
746 /* Phy offset ready registers */
747 #define PHY_REG_TX_OFFSET_READY 0x54
748 #define PHY_REG_RX_OFFSET_READY 0x74
749
750 /* Phy total offset registers */
751 #define PHY_REG_TOTAL_TX_OFFSET_L 0x38
752 #define PHY_REG_TOTAL_TX_OFFSET_U 0x3C
753 #define PHY_REG_TOTAL_RX_OFFSET_L 0x58
754 #define PHY_REG_TOTAL_RX_OFFSET_U 0x5C
755
756 /* Timestamp capture registers */
757 #define PHY_REG_TX_CAPTURE_L 0x78
758 #define PHY_REG_TX_CAPTURE_U 0x7C
759 #define PHY_REG_RX_CAPTURE_L 0x8C
760 #define PHY_REG_RX_CAPTURE_U 0x90
761
762 /* Memory status registers */
763 #define PHY_REG_TX_MEMORY_STATUS_L 0x80
764 #define PHY_REG_TX_MEMORY_STATUS_U 0x84
765
766 /* Interrupt config register */
767 #define PHY_REG_TS_INT_CONFIG 0x88
768
769 /* XIF mode config register */
770 #define PHY_MAC_XIF_MODE 0x24
771 #define PHY_MAC_XIF_1STEP_ENA_M ICE_M(0x1, 5)
772 #define PHY_MAC_XIF_TS_BIN_MODE_M ICE_M(0x1, 11)
773 #define PHY_MAC_XIF_TS_SFD_ENA_M ICE_M(0x1, 20)
774 #define PHY_MAC_XIF_GMII_TS_SEL_M ICE_M(0x1, 21)
775
776 /* GPCS config register */
777 #define PHY_GPCS_CONFIG_REG0 0x268
778 #define PHY_GPCS_CONFIG_REG0_TX_THR_M ICE_M(0xF, 24)
779 #define PHY_GPCS_BITSLIP 0x5C
780
781 #define PHY_TS_INT_CONFIG_THRESHOLD_M ICE_M(0x3F, 0)
782 #define PHY_TS_INT_CONFIG_ENA_M BIT(6)
783
784 /* 1-step PTP config */
785 #define PHY_PTP_1STEP_CONFIG 0x270
786 #define PHY_PTP_1STEP_T1S_UP64_M ICE_M(0xF, 4)
787 #define PHY_PTP_1STEP_T1S_DELTA_M ICE_M(0xF, 8)
788 #define PHY_PTP_1STEP_PEER_DELAY(_port) (0x274 + 4 * (_port))
789 #define PHY_PTP_1STEP_PD_ADD_PD_M ICE_M(0x1, 0)
790 #define PHY_PTP_1STEP_PD_DELAY_M ICE_M(0x3fffffff, 1)
791 #define PHY_PTP_1STEP_PD_DLY_V_M ICE_M(0x1, 31)
792
793 /* Macros to derive offsets for TimeStampLow and TimeStampHigh */
794 #define PHY_TSTAMP_L(x) (((x) * 8) + 0)
795 #define PHY_TSTAMP_U(x) (((x) * 8) + 4)
796
797 #define PHY_REG_REVISION 0x85000
798
799 #define PHY_REG_DESKEW_0 0x94
800 #define PHY_REG_DESKEW_0_RLEVEL GENMASK(6, 0)
801 #define PHY_REG_DESKEW_0_RLEVEL_FRAC GENMASK(9, 7)
802 #define PHY_REG_DESKEW_0_RLEVEL_FRAC_W 3
803 #define PHY_REG_DESKEW_0_VALID GENMASK(10, 10)
804
805 #define PHY_REG_GPCS_BITSLIP 0x5C
806 #define PHY_REG_SD_BIT_SLIP(_port_offset) (0x29C + 4 * (_port_offset))
807 #define PHY_REVISION_ETH56G 0x10200
808 #define PHY_VENDOR_TXLANE_THRESH 0x2000C
809
810 #define PHY_MAC_TSU_CONFIG 0x40
811 #define PHY_MAC_TSU_CFG_RX_MODE_M ICE_M(0x7, 0)
812 #define PHY_MAC_TSU_CFG_RX_MII_CW_DLY_M ICE_M(0x7, 4)
813 #define PHY_MAC_TSU_CFG_RX_MII_MK_DLY_M ICE_M(0x7, 8)
814 #define PHY_MAC_TSU_CFG_TX_MODE_M ICE_M(0x7, 12)
815 #define PHY_MAC_TSU_CFG_TX_MII_CW_DLY_M ICE_M(0x1F, 16)
816 #define PHY_MAC_TSU_CFG_TX_MII_MK_DLY_M ICE_M(0x1F, 21)
817 #define PHY_MAC_TSU_CFG_BLKS_PER_CLK_M ICE_M(0x1, 28)
818 #define PHY_MAC_RX_MODULO 0x44
819 #define PHY_MAC_RX_OFFSET 0x48
820 #define PHY_MAC_RX_OFFSET_M ICE_M(0xFFFFFF, 0)
821 #define PHY_MAC_TX_MODULO 0x4C
822 #define PHY_MAC_BLOCKTIME 0x50
823 #define PHY_MAC_MARKERTIME 0x54
824 #define PHY_MAC_TX_OFFSET 0x58
825
826 #define PHY_PTP_INT_STATUS 0x7FD140
827
828 #endif /* _ICE_PTP_HW_H_ */
829